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SystemVerilog for Verification:
( Z2 z- ^+ {' t+ _A Guide to Learning the Testbench Language Features
. e. ^7 Q0 Q( t9 I" B1. VERIFICATION GUIDELINES 1& ~8 |# e, H. X, D0 d
1.1 Introduction 1
4 c" f5 Q6 h8 y' T1.2 The Verification Process 2
2 s1 l; Z! |# s- f" v1 g. F1.3 The Verification Plan 48 Q" H5 M$ _$ c# d& I; c
1.4 The Verification Methodology Manual 4) ^& E) D4 Y5 Z- ]% z2 P G
1.5 Basic Testbench Functionality 5
/ K) d% I( W' W1.6 Directed Testing 54 \# ^9 n% x6 X' Y. @
1.7 Methodology Basics 7
' p, T( s, H# e( B: w1.8 Constrained-Random Stimulus 8
" K( l- ?" L5 G. W1.9 What Should You Randomize? 106 v% k2 a! g {
1.10 Functional Coverage 13
9 g7 z* j0 P4 F* o1.11 Testbench Components 15+ b8 w* { R7 l3 b% `; ^3 ^$ g5 S
1.12 Layered Testbench 16
\- {9 k9 ^5 C* M6 q5 W" D1.13 Building a Layered Testbench 22
% R# ^2 R; V+ b) ~% `1.14 Simulation Environment Phases 23: T0 e) |$ Y1 A- L. b" E# I
1.15 Maximum Code Reuse 24
, b/ d3 B7 b+ ~8 f% @% ^% M( \2 D1.16 Testbench Performance 24
: k9 {7 a4 }* y5 j: j% S' G* D1.17 Conclusion 25
. i: n- D* l) Z8 r1 {2. DATA TYPES 27
4 {2 n3 F" [7 N: B2.1 Introduction 27! @! v% e7 z0 z: j4 l
2.2 Built-in Data Types 27
" I, \8 x5 j H% Uviii SystemVerilog for Verification, O, p& W% M- v, ^! @4 @
2.3 Fixed-Size Arrays 29# [3 U4 J+ J* G% `8 H
2.4 Dynamic Arrays 346 @: ]2 X k$ }
2.5 Queues 36) j2 ]" I4 R/ Q7 v0 ~: S/ E
2.6 Associative Arrays 37
1 m3 n0 ^7 \+ q% K2.7 Linked Lists 39% J, h4 H5 o6 b6 d" S/ H+ U
2.8 Array Methods 407 \% y8 P$ \7 {% g" B, s0 n
2.9 Choosing a Storage Type 42- [' q( n1 K& \, {* Z0 `* ~8 I. c
2.10 Creating New Types with typedef 45. x# x; k) \5 C% x8 q1 s: m
2.11 Creating User-Defined Structures 46
2 K% S# l9 P0 M+ [" o2.12 Enumerated Types 47
/ [2 b: w7 {) U. p, S% m, s( u% v2.13 Constants 51" C4 j- W- ~% H2 l) P" O# w
2.14 Strings 51, `4 ]3 R- p/ b3 S# D2 P
2.15 Expression Width 52
) q" R' K2 m/ K2 k0 Z2.16 Net Types 53
* T! h0 w! H- A6 q9 L5 r2.17 Conclusion 53* G7 C' m$ l) H. |# H+ ` f
3. PROCEDURAL STATEMENTS AND ROUTINES 55. D3 G, y: n% r; u" l' @/ S
3.1 Introduction 55
; q0 j2 Z9 m: L: [3.2 Procedural Statements 55
# {2 I" I L; [+ [. T3.3 Tasks, Functions, and Void Functions 562 E, H) c2 _0 p- q* r
3.4 Task and Function Overview 57
G/ G3 i, x/ Z3.5 Routine Arguments 57
0 ?( w- {" W" m# o6 ~4 ]; K* V7 H3.6 Returning from a Routine 62
% x& }3 g X$ n/ [ U0 F0 M3.7 Local Data Storage 62
' R: |3 M n: _9 O" _5 X6 a3.8 Time Values 64' Y& |$ o: Z5 ? n, e8 y
3.9 Conclusion 65- o( E. I& R5 |' \5 q" K! e
4. BASIC OOP 67
; S* q( F1 Z, o& m! Z7 r8 z4 |4.1 Introduction 67" Q+ E: w* C* T* l
4.2 Think of Nouns, not Verbs 67
9 y5 y$ b7 o: H9 B9 S" F* S% o4.3 Your First Class 68
9 S, O U% a2 V0 u% K1 P4.4 Where to Define a Class 69
$ | ?& W- Y- c5 r4.5 OOP Terminology 69
; ~' D/ O2 P1 a2 O, v4 W4 `- `4.6 Creating New Objects 70/ `$ b, C2 }7 x
4.7 Object Deallocation 747 ^# T' _! P/ N8 S- a
4.8 Using Objects 761 A8 r9 S. ]9 N& L6 }
4.9 Static Variables vs. Global Variables 762 C2 e, d2 B3 U9 w) {+ u- t s
4.10 Class Routines 780 L# J9 B/ D9 ~, ?0 _; i' G
4.11 Defining Routines Outside of the Class 79
% b/ Y* o$ B$ y+ Y5 D1 d4.12 Scoping Rules 811 B% c u r9 {6 c
4.13 Using One Class Inside Another 85
+ ] h+ N) A* o+ V4.14 Understanding Dynamic Objects 875 c; w- ` f1 J3 F3 c5 \, |0 \8 u
4.15 Copying Objects 91, V- T9 O6 a, \4 i( m" u; p8 e
4.16 Public vs. Private 957 B7 [0 X/ `$ {. q0 D$ J
Contents ix
! N, U m `8 D* a4.17 Straying Off Course 96
/ I) _* A& z# a0 u8 w4.18 Building a Testbench 963 t) {) n0 c* P4 O8 v
4.19 Conclusion 97
9 B$ \+ V9 o$ c4 t# Q5. CONNECTING THE TESTBENCH AND DESIGN 99
7 P- R0 _" I; V$ B5.1 Introduction 99
9 F+ m' ]6 N. u3 E2 g8 c5 V5.2 Separating the Testbench and Design 99" [9 ?: w$ v+ s7 q7 C8 m
5.3 The Interface Construct 102' L2 u: ] p8 { E
5.4 Stimulus Timing 108% A! `! g0 N" Z5 E$ N4 m$ S! L- d
5.5 Interface Driving and Sampling 114
4 G5 O# ^/ i) m0 w' F1 Q5.6 Connecting It All Together 121( u9 t! w( G2 ~. ]3 R. g7 [# `
5.7 Top-Level Scope 121$ X$ O& O+ ?! }/ x
5.8 Program – Module Interactions 123
* F7 Q" K) A" w7 G4 E6 W( l' m5.9 SystemVerilog Assertions 124
+ d# J$ m# {8 {: ~: k9 j) L5.10 The Four-Port ATM Router 126
- e4 w( l1 P; q5.11 Conclusion 1341 h; n& x/ q( U2 V7 i; _
6. RANDOMIZATION 135
4 n& C/ ?3 H) K! E7 l( V6.1 Introduction 135
" o, |) n8 q7 `6.2 What to Randomize 136
% [! l5 C) g! o+ @7 C6 b6.3 Randomization in SystemVerilog 138
5 |! |; V n+ A6.4 Constraint Details 141/ W* r6 b9 D+ ?
6.5 Solution Probabilities 149
, c' N/ A7 L; D+ O6.6 Controlling Multiple Constraint Blocks 154: i. G2 g d% z
6.7 Valid Constraints 1549 \% b0 [& j' h; w
6.8 In-line Constraints 1559 n2 T: m0 y6 |2 X$ X) Q
6.9 The pre_randomize and post_randomize Functions 1569 V: Y7 d) J+ q* N
6.10 Constraints Tips and Techniques 158( U' `8 x) j# v$ z. u; j( M9 e
6.11 Common Randomization Problems 164* u5 _, q& U2 B7 B. C. |: t- W1 b- q
6.12 Iterative and Array Constraints 165: L4 z0 _3 O; m, E
6.13 Atomic Stimulus Generation vs. Scenario Generation 172
: F7 ?, s3 c: z# P5 }/ c, b6.14 Random Control 175
% I- M$ F$ ~2 v7 p6.15 Random Generators 1778 n, b: p6 g. Y$ }0 B1 E9 ]
6.16 Random Device Configuration 180
0 o } ~& e2 k( s0 c: h* w; b6.17 Conclusion 1828 M* R1 R# w! T8 A
7. THREADS AND INTERPROCESS COMMUNICATION 183
}7 `8 ?9 G$ f) A( @7.1 Introduction 183
8 ~; }9 Q3 j" [. K/ p+ g7.2 Working with Threads 184
2 l8 @( e1 G8 N: B2 M; i/ R7.3 Interprocess Communication 194
- n4 e+ C8 Z1 y7.4 Events 195/ M% g: q5 ~4 B$ r7 B- j. X% {# l
7.5 Semaphores 1995 l, r0 F! E- m
7.6 Mailboxes 201& Y% ?. ]2 g: r8 u. \2 q
7.7 Building a Testbench with Threads and IPC 2105 G- ]3 q( b5 Q5 {2 }, M3 d
x SystemVerilog for Verification
6 f! _4 \! F6 H' ?( m( f. C# o) ~7 C7.8 Conclusion 2146 _5 v3 b" T! B, [! U
8. ADVANCED OOP AND GUIDELINES 215
2 r9 ?! ~/ A3 M6 i$ `: m8.1 Introduction 215% D/ _* Q, d7 i1 |1 m
8.2 Introduction to Inheritance 216
4 A7 m* K/ N) v5 o0 G8.3 Factory Patterns 221
+ |* m# U, y6 ^% R: l+ u8.4 Type Casting and Virtual Methods 225
: n& z, k, L" M0 R E/ K) R K8.5 Composition, Inheritance, and Alternatives 2287 C- e" y5 Y# [3 ?2 N4 P: T5 K
8.6 Copying an Object 233
" [. ]" z: W. l! \5 A# b8.7 Callbacks 236
4 a; ^2 f5 @4 ?7 M8.8 Conclusion 240) I2 c3 @0 g9 s+ m) J1 n. r
9. FUNCTIONAL COVERAGE 241- L* J$ I6 E2 Q) x
9.1 Introduction 241; B% w! I" {2 K/ h7 t6 r( W9 J- z
9.2 Coverage Types 243
- `# n- \) L- {% K; Y6 y2 K. d9.3 Functional Coverage Strategies 2464 I1 x1 I1 u- Y% o
9.4 Simple Functional Coverage Example 248
0 J# H4 c' x. T2 S9.5 Anatomy of a Cover Group 251 k- }: ], a6 e- l: @3 B# v
9.6 Triggering a Cover Group 253, d7 T2 w7 W g9 c. S5 f# Y" I$ m8 x) }# [
9.7 Data Sampling 256
0 @- O% p/ J5 ^9.8 Cross Coverage 265
5 E" H5 u0 A4 v4 g" r9.9 Coverage Options 272
2 X3 V0 P& `. u& j3 V, U" @9.10 Parameterized Cover Groups 274
# O: Q7 y1 t, ~1 }, D O: z7 A9.11 Analyzing Coverage Data 275
% u3 O. I' c2 ?4 t( w( B& Q* Y+ G9.12 Measuring Coverage Statistics During Simulation 276
8 Y% \ c. z/ O* g9.13 Conclusion 2774 B( f# l1 s7 E% k8 m+ C# U% P
10. ADVANCED INTERFACES 279
6 S7 j" q; U" H: |- ~10.1 Introduction 279) s7 g# G8 n6 P3 D# q+ T0 y- y7 P
10.2 Virtual Interfaces with the ATM Router 279; L) `& c8 n- u$ e' h2 U
10.3 Connecting to Multiple Design Configurations 284
& L* H, I$ P' f+ j" T- n10.4 Procedural Code in an Interface 2900 ^- U7 X* o: ~
10.5 Conclusion 294" R6 s- M# I& F: L% ~. a
References 295
3 l3 t0 |/ Q7 @/ p9 e$ Z, tIndex 297
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