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SystemVerilog for Verification:' y. Y/ _$ P; Z$ y; `& \
A Guide to Learning the Testbench Language Features
% M! U( Q/ e" G: i0 A) I3 H) p1 |+ N1. VERIFICATION GUIDELINES 1
* t' W/ O: n8 D1.1 Introduction 1
% A' z0 H' ^3 Q- q9 Z1.2 The Verification Process 2) B% {9 W7 w; J9 e1 P
1.3 The Verification Plan 4
# h# S: M, S+ p! n" s" c, M1.4 The Verification Methodology Manual 4
8 m1 ~* w) T' P0 ?1.5 Basic Testbench Functionality 5
+ l! |6 _/ Q9 j0 V- W8 N1.6 Directed Testing 5/ }! Q" R3 h i# X
1.7 Methodology Basics 7, w8 a7 |; ]+ B2 J( i; h: k' R
1.8 Constrained-Random Stimulus 8
" X6 ^; P6 P) b# T, e1.9 What Should You Randomize? 10) ?) o% t2 p6 q' N( H0 o! {) T1 j
1.10 Functional Coverage 13
' A, T" Q# ?+ r% B0 j& ~' K1.11 Testbench Components 15# l/ Z2 r. f! n' D# r- G
1.12 Layered Testbench 16' d) r; Z' d' e- q
1.13 Building a Layered Testbench 22
3 j ^, |- o; z, {8 H) |1.14 Simulation Environment Phases 23
+ e: S2 o3 o6 d& D1.15 Maximum Code Reuse 24$ E3 z- @( r( ] g( E
1.16 Testbench Performance 24
9 @, c6 M8 D3 Y }/ D) W/ ?- B1.17 Conclusion 25
3 B8 k) H1 `3 \3 C Q( Y2. DATA TYPES 27
# E3 O q" j ]( l% \, o9 j9 y2.1 Introduction 278 B) N3 Q1 J9 q( t3 E: M
2.2 Built-in Data Types 27. {' z* H$ ?7 h, b0 y7 p* b2 p
viii SystemVerilog for Verification7 B$ m S0 w- B) |0 {; i! U. y+ U
2.3 Fixed-Size Arrays 29
- z3 ]9 x8 h9 _. [7 q6 R8 L# s5 Q2.4 Dynamic Arrays 344 j2 ]8 _2 K9 ?7 _/ m
2.5 Queues 36* N- I5 P4 Q j1 m3 o
2.6 Associative Arrays 37, ?" |8 T8 H e/ u) ^
2.7 Linked Lists 39+ g5 _4 V! C% ^+ I* T' q. `
2.8 Array Methods 40- W& c, J4 C; w' T
2.9 Choosing a Storage Type 42
0 `9 `6 Y% C, \' [: P2.10 Creating New Types with typedef 459 U N- t! z& ]2 H7 V: B8 F
2.11 Creating User-Defined Structures 46* L* a# Z1 X+ f: ?
2.12 Enumerated Types 47 f' u' K7 h6 w9 U: y+ ]. t
2.13 Constants 51& N, I g! F3 k# O0 N0 y
2.14 Strings 51& o5 V0 d9 ^% _' C' C
2.15 Expression Width 521 X4 y# T @5 \2 f' w
2.16 Net Types 53; e* W0 L' v/ K( U% k3 v
2.17 Conclusion 53
& T. n+ S' m1 g3. PROCEDURAL STATEMENTS AND ROUTINES 55
+ p' h) j) g# O2 R) p# b; n3.1 Introduction 55) c$ o5 f: ?! e5 u% i2 Y. J3 x
3.2 Procedural Statements 55 s- s8 j% g. s$ `5 l1 i+ \
3.3 Tasks, Functions, and Void Functions 56& I6 O: s$ |; h& ]& c: \6 [
3.4 Task and Function Overview 579 D* X! m! K3 ?* x3 R! M. v* I
3.5 Routine Arguments 57* w [" ?; f4 q$ Z! V
3.6 Returning from a Routine 62
- W' }9 z' Z4 n3 r8 g' {! ]3.7 Local Data Storage 62
6 n2 T6 h. I& r0 v3.8 Time Values 64
+ h; q7 p& z+ V/ |3.9 Conclusion 65
1 U3 h; f. B; Z% K H) d! U4. BASIC OOP 67
0 {, \8 l5 N( ?* v4.1 Introduction 67
; _3 @0 |3 w7 g; o2 d% J2 i& J4 `4.2 Think of Nouns, not Verbs 67
9 P) W# V/ n( \6 r3 Q! {+ w7 g6 I4.3 Your First Class 68
& k7 Q1 V6 @& \) W5 s4 `* c# F4 r# g4.4 Where to Define a Class 69
6 F8 Z, U' @' f' v& E! i9 f4.5 OOP Terminology 69, l7 u2 ~$ w7 s/ d
4.6 Creating New Objects 70
8 m% z+ i W Q9 s7 f4.7 Object Deallocation 74! V% {0 t+ E" C# W- R3 F. A
4.8 Using Objects 76
5 n# N9 E; F0 v* U+ b! a3 F- M4.9 Static Variables vs. Global Variables 76
; e4 o7 Y! L9 J5 Y% T( \/ \- _4.10 Class Routines 78 F* q. T# O$ c; L& Q
4.11 Defining Routines Outside of the Class 79- D; g0 K; S$ a; a
4.12 Scoping Rules 81
, V, v) n" f. [$ T1 ^. Q$ {4.13 Using One Class Inside Another 857 ^3 h. L" c- I# n2 ?
4.14 Understanding Dynamic Objects 87
$ C3 E5 i% u( i" C6 L4.15 Copying Objects 91
8 K- b, P- |4 u9 \9 h, j4.16 Public vs. Private 95
' _# B! x t2 q7 @ z7 r* QContents ix
& I+ X+ P$ C5 Q4.17 Straying Off Course 965 T! b- D1 A: x
4.18 Building a Testbench 967 f h. ]# Y5 g3 n1 `4 @, L
4.19 Conclusion 97, Q) n7 S. z7 ?" _
5. CONNECTING THE TESTBENCH AND DESIGN 99
0 w1 p& H0 a- ~5.1 Introduction 991 j0 s7 j+ {$ s5 c; I8 `
5.2 Separating the Testbench and Design 99 Y2 H% k. l y% `. B
5.3 The Interface Construct 102$ `4 f3 R: Z& X
5.4 Stimulus Timing 108
. Y1 w4 x' {8 x% l! b% M6 X' P5.5 Interface Driving and Sampling 114
/ ]4 c) X* ?/ q# p9 {* o5.6 Connecting It All Together 121
# v- Q& X2 }; O1 n2 g" k5.7 Top-Level Scope 1218 G( a$ \6 u! r7 U2 I2 M( y1 x+ v
5.8 Program – Module Interactions 123& A6 N' V. z+ C- }
5.9 SystemVerilog Assertions 1240 Q* J; z0 B, j( b3 }& h# z: U
5.10 The Four-Port ATM Router 126
' s/ Q4 l4 D6 o E2 y5.11 Conclusion 1342 K. E! I3 K$ p+ P
6. RANDOMIZATION 135
/ _ S4 R# [5 F6 ]9 p' p# w6.1 Introduction 135/ @4 Z- l! y C$ q/ [5 ?5 ?/ F
6.2 What to Randomize 136. N4 t- h: T% @0 e
6.3 Randomization in SystemVerilog 138
, p# }4 Z G. O# o- i9 g# T6.4 Constraint Details 141
0 j8 E$ q3 [( k5 n6.5 Solution Probabilities 149
- b& F3 s3 r( l2 F8 k6.6 Controlling Multiple Constraint Blocks 154
& z2 S8 D/ i; Z0 D3 X! g/ F6.7 Valid Constraints 154
% i1 ~+ c- z/ G; a& n6 T6.8 In-line Constraints 1552 i$ M' |" S" T" D8 n( A7 @ Z
6.9 The pre_randomize and post_randomize Functions 156
/ `9 c; y* v/ I& \8 g- R6.10 Constraints Tips and Techniques 158
! M% s3 Q* B1 C- D' M6.11 Common Randomization Problems 164+ h7 I. A" n9 k* O& _% Z6 r/ m) {& O
6.12 Iterative and Array Constraints 165
/ v) G" R7 e6 t+ R H4 y6.13 Atomic Stimulus Generation vs. Scenario Generation 172
z8 G. U) b$ u4 N/ x. P/ V: D6.14 Random Control 175
) X/ {# w3 ]% b" C+ B" M6.15 Random Generators 177
8 `8 T' e" w; l' K/ w9 l }6.16 Random Device Configuration 180
, a' O5 B! V% v5 V6.17 Conclusion 182/ K! u9 [6 l' `/ T' B0 M! p0 L
7. THREADS AND INTERPROCESS COMMUNICATION 183
2 ?9 N$ A" Y3 Y" k" N( C1 u7.1 Introduction 183
$ m" t" P) Y( l3 L( K: @7.2 Working with Threads 184
; g1 f u/ v7 ]7 m4 U/ Z2 k7.3 Interprocess Communication 194
8 j" A1 ^: ~4 H A+ Z4 a. _1 ^7.4 Events 195
7 B. p) I* i6 V/ U2 t, X" O$ B3 g7.5 Semaphores 199. o# ^- j/ K3 ]; o1 ^, X9 E' L
7.6 Mailboxes 201% O4 O4 X: M% e. m: _3 r) r0 V
7.7 Building a Testbench with Threads and IPC 2102 p% e" D- g# r3 u
x SystemVerilog for Verification1 x0 P( f/ L1 ]$ |" B3 x% Y k
7.8 Conclusion 214, ]. L, R' |: y
8. ADVANCED OOP AND GUIDELINES 215
- V6 C6 ?' n. l# H. G! p$ ?8.1 Introduction 215
2 t; i8 T5 A) e2 B2 J4 S) l8 ^8.2 Introduction to Inheritance 2168 O& @4 }& r; h' k! p/ a2 q) I
8.3 Factory Patterns 221" u1 B4 @ L! v. V- P0 `
8.4 Type Casting and Virtual Methods 225
" r; F0 U4 z4 |7 s: ?8 W+ T8.5 Composition, Inheritance, and Alternatives 228
) u- {) L# ?0 G+ U, A/ c8.6 Copying an Object 233
4 G% T. r2 _! b+ [- m8.7 Callbacks 236
% k; h" S* a; K4 @! `$ E, S$ I6 N8.8 Conclusion 240; j7 m6 l* o) u4 q7 R, u
9. FUNCTIONAL COVERAGE 241
" Y6 e4 _$ s5 i* A9.1 Introduction 241
6 g6 \) ~6 ~) f- T9.2 Coverage Types 243
6 W1 z) k+ |7 s2 ]$ j9.3 Functional Coverage Strategies 246
# ~) B" {3 ]! y9.4 Simple Functional Coverage Example 248
' v% P7 V; p& ]4 K% A! }* I9.5 Anatomy of a Cover Group 251
/ }. R; s0 s0 s+ N. N+ H9.6 Triggering a Cover Group 253
' B1 b4 }5 I7 F9.7 Data Sampling 256, q3 u0 H7 u! `2 @
9.8 Cross Coverage 265
+ `" j5 n: I" L, n8 F9.9 Coverage Options 272' M* c; m' [0 l& ^# q$ p* i3 q
9.10 Parameterized Cover Groups 274* j2 T' @9 w# B; y+ U: W3 \
9.11 Analyzing Coverage Data 275. E) G0 c0 r0 v9 W# j* ]0 m
9.12 Measuring Coverage Statistics During Simulation 2764 J% T+ ?9 C# w' ]# C3 n- Y5 \" I
9.13 Conclusion 277
! e# Z) m$ K! Q. F, l+ J$ J: p10. ADVANCED INTERFACES 279' e; ~" k% m8 I+ O8 V! h
10.1 Introduction 279* p- { a1 O. F4 `+ e# z, D
10.2 Virtual Interfaces with the ATM Router 279
) y' A( O% A, |" Y( a* j10.3 Connecting to Multiple Design Configurations 284
* s+ z( [7 s, x0 h; X- |, R10.4 Procedural Code in an Interface 2907 [/ W7 q {9 [3 ~! _' D
10.5 Conclusion 2941 K1 b( ~5 ^$ u. M; b5 S
References 2953 j+ j, `0 b' n; t! k+ B: a4 J
Index 297" e# f1 @, M1 |
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