SystemVerilog for Verification

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SystemVerilog for Verification:
# j% v6 k$ d) A- F& O0 n* eA Guide to Learning the Testbench Language Features
1. VERIFICATION GUIDELINES 1
1.1 Introduction 1
1.2 The Verification Process 2
) g3 b( s8 H2 B1.3 The Verification Plan 4
1.4 The Verification Methodology Manual 4
1.5 Basic Testbench Functionality 5
1.6 Directed Testing 5
+ Z) D4 r& F9 V1.7 Methodology Basics 7
" r- p0 V, X' o. I4 i& [- o1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
, f. n: j( r4 }1.10 Functional Coverage 13
) i/ N  U! z  i# Q2 f; N2 u1.11 Testbench Components 15
1.12 Layered Testbench 16
8 ?9 G( J/ F% ?, F+ `1.13 Building a Layered Testbench 22
1.14 Simulation Environment Phases 23
1.15 Maximum Code Reuse 24
1.16 Testbench Performance 24
# d( }: ~% ^: U1.17 Conclusion 25
2. DATA TYPES 27
2 C0 n: M" F) R. [2.1 Introduction 27
2.2 Built-in Data Types 27
viii SystemVerilog for Verification
2.3 Fixed-Size Arrays 29
2.4 Dynamic Arrays 34
2.5 Queues 36
: D( x4 |7 ]. l. H2.6 Associative Arrays 37
1 P  @0 y9 O$ g7 T2.7 Linked Lists 39
2.8 Array Methods 40
2.9 Choosing a Storage Type 42
2.10 Creating New Types with typedef 45
2.11 Creating User-Defined Structures 46
2.12 Enumerated Types 47
2.13 Constants 51
2.14 Strings 51
# R- u0 {6 k# z4 r2.15 Expression Width 52
$ g4 T+ X+ h5 \: c6 t2.16 Net Types 53
9 g7 C, b' h' }1 p' F% u. B8 Q4 w2.17 Conclusion 53
3. PROCEDURAL STATEMENTS AND ROUTINES 55
3.1 Introduction 55
3.2 Procedural Statements 55
. Z+ R% m) C3 O8 N5 q3.3 Tasks, Functions, and Void Functions 56
3.4 Task and Function Overview 57
' z6 ^' R& Z9 g& Y* F3.5 Routine Arguments 57
3.6 Returning from a Routine 62
# `2 ~0 q* k8 Y* ]! A3.7 Local Data Storage 62
3.8 Time Values 64
) p  e, G+ n' D$ J3.9 Conclusion 65
  l: c, o! K, d, n( S# X4. BASIC OOP 67
4.1 Introduction 67
, B' @- t1 q  o. t4.2 Think of Nouns, not Verbs 67
4.3 Your First Class 68
" |; y( D9 p$ f5 h' M' A  P4.4 Where to Define a Class 69
/ i( u$ G0 Y: n: s' _# S9 d4.5 OOP Terminology 69
, H: |- S& M2 ]$ P0 V4.6 Creating New Objects 70
# b8 O( o2 J; B4 k8 Y6 n- U4.7 Object Deallocation 74
4.8 Using Objects 76
$ f  x* e1 \3 `2 J& Z% Q. B7 I4.9 Static Variables vs. Global Variables 76
4.10 Class Routines 78
4.11 Defining Routines Outside of the Class 79
4.12 Scoping Rules 81
; R+ w5 i+ P0 `6 k  t5 X4.13 Using One Class Inside Another 85
+ p) u& m! F$ K/ P4.14 Understanding Dynamic Objects 87
4.15 Copying Objects 91
4.16 Public vs. Private 95
Contents ix
, x$ @" x, i' f/ o8 N! Y& m) j, E4.17 Straying Off Course 96
4.18 Building a Testbench 96
5 |: w; S4 a0 y; n+ y$ _: S4.19 Conclusion 97
+ }& {- a, t% L) q5. CONNECTING THE TESTBENCH AND DESIGN 99
6 v7 c7 r. y/ j7 ~/ D5.1 Introduction 99
, B0 ^( y6 t* x+ F3 N5.2 Separating the Testbench and Design 99
5.3 The Interface Construct 102
: F$ |. [& C( H2 J! s5.4 Stimulus Timing 108
: `" C& D+ Y# q8 c# O5.5 Interface Driving and Sampling 114
5.6 Connecting It All Together 121
. r% a" |4 x5 B5 m4 K$ }5.7 Top-Level Scope 121
5.8 Program – Module Interactions 123
5.9 SystemVerilog Assertions 124
5.10 The Four-Port ATM Router 126
* X# v! G8 q+ x2 A" q5.11 Conclusion 134
6. RANDOMIZATION 135
1 N7 ~6 Y* N% f9 l/ a6 O. E4 E6.1 Introduction 135
- |7 Y+ u. D; ~! D9 ^3 p6 y6.2 What to Randomize 136
6.3 Randomization in SystemVerilog 138
6.4 Constraint Details 141
6.5 Solution Probabilities 149
" l' D6 H; Q! c. z6.6 Controlling Multiple Constraint Blocks 154
2 S7 I8 c6 }% b9 |4 n6.7 Valid Constraints 154
9 Y* o+ y* q% x8 ?1 J' `6.8 In-line Constraints 155
/ p$ S" ]2 Z# I/ ~5 A3 E6.9 The pre_randomize and post_randomize Functions 156
6.10 Constraints Tips and Techniques 158
6.11 Common Randomization Problems 164
* ]6 V; |) [$ ?/ p$ }1 I& k6.12 Iterative and Array Constraints 165
" }0 R6 ~$ O, x  K7 r3 y6.13 Atomic Stimulus Generation vs. Scenario Generation 172
6.14 Random Control 175
6.15 Random Generators 177
) ?8 P  m3 V0 E: O* }7 K6.16 Random Device Configuration 180
6.17 Conclusion 182
7. THREADS AND INTERPROCESS COMMUNICATION 183
, _% e6 ?$ C$ w7.1 Introduction 183
7.2 Working with Threads 184
7.3 Interprocess Communication 194
: i- g$ j$ ^6 \7.4 Events 195
, r& X/ X; X. P6 c+ k7.5 Semaphores 199
- O# a$ X! U! n: r7.6 Mailboxes 201
$ y  B* ~: S1 W7.7 Building a Testbench with Threads and IPC 210
7 @4 _9 Z: z! Wx SystemVerilog for Verification
0 \& A& i2 P! V8 i# V3 n2 ?7.8 Conclusion 214
% {! s9 ]  P3 u$ w0 n. ~: e# n8. ADVANCED OOP AND GUIDELINES 215
8.1 Introduction 215
( W1 |% ]7 y" j/ j6 N4 ~7 Z8.2 Introduction to Inheritance 216
8.3 Factory Patterns 221
* |8 E( h/ @" E9 S8.4 Type Casting and Virtual Methods 225
8.5 Composition, Inheritance, and Alternatives 228
8.6 Copying an Object 233
8.7 Callbacks 236
8.8 Conclusion 240
- P( l6 C. ~( z3 R( @9 U: Z9. FUNCTIONAL COVERAGE 241
3 ~$ ^6 l) [. h# V8 R6 n9.1 Introduction 241
& V( w: H6 o0 v' p; d, H9.2 Coverage Types 243
2 F, @8 T1 b& E9 h9.3 Functional Coverage Strategies 246
) k( V! ^& [  m" Z* c. `9.4 Simple Functional Coverage Example 248
7 O5 W" f3 n2 }; R! D4 b9.5 Anatomy of a Cover Group 251
9.6 Triggering a Cover Group 253
9.7 Data Sampling 256
9.8 Cross Coverage 265
0 I8 n0 @" p4 {3 v- J$ T$ X( r9.9 Coverage Options 272
2 a; I3 ]# [$ w- r; G9.10 Parameterized Cover Groups 274
9.11 Analyzing Coverage Data 275
9.12 Measuring Coverage Statistics During Simulation 276
9.13 Conclusion 277
8 Y0 |$ U. j: n10. ADVANCED INTERFACES 279
10.1 Introduction 279
' W/ m5 B; y6 t0 s: o1 f0 h10.2 Virtual Interfaces with the ATM Router 279
3 x3 ^, ~) D; G/ P9 r, h10.3 Connecting to Multiple Design Configurations 284
10.4 Procedural Code in an Interface 290
10.5 Conclusion 294
+ J  H% V# [/ w) L. [References 295
Index 297
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