SystemVerilog for Verification

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& L* _, }/ g8 B8 S- Y% [% Z. KSystemVerilog for Verification:
A Guide to Learning the Testbench Language Features
1. VERIFICATION GUIDELINES 1
. V: t! y. D. g, P1.1 Introduction 1
0 N% @4 N! @) p: }8 ^. o- Q1.2 The Verification Process 2
% f* D! {6 K( V. {; Q1.3 The Verification Plan 4
1.4 The Verification Methodology Manual 4
  q& ~/ ?8 I2 R/ L: T$ i* l9 F) T, {" V1.5 Basic Testbench Functionality 5
1.6 Directed Testing 5
% T3 ^) G$ A& j: F+ Z1 k; D! m1.7 Methodology Basics 7
1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
1.10 Functional Coverage 13
7 X3 k4 b  k: e& f8 `5 u! N) n1.11 Testbench Components 15
1.12 Layered Testbench 16
+ l* g0 m) W+ Z% ?) q: ]0 D1.13 Building a Layered Testbench 22
1.14 Simulation Environment Phases 23
. D( j! t+ H& O1.15 Maximum Code Reuse 24
& V" @$ n1 ~7 O- h, g' y1.16 Testbench Performance 24
1.17 Conclusion 25
2 @; o8 }: p0 n. D2. DATA TYPES 27
2.1 Introduction 27
2.2 Built-in Data Types 27
! a; n0 n5 B, @1 Fviii SystemVerilog for Verification
2.3 Fixed-Size Arrays 29
! {# H( P4 g) P9 M* ]( O2.4 Dynamic Arrays 34
+ S9 G9 `* X' Q: r4 T  C, C3 Y2.5 Queues 36
2.6 Associative Arrays 37
0 u1 I; Q$ Q5 k6 k2 M/ P9 K8 M2.7 Linked Lists 39
, U$ {! |  v% X# N, C  @1 h) W2.8 Array Methods 40
; Z3 X9 j9 ?/ ]" V: I% \+ n( ^2.9 Choosing a Storage Type 42
$ N& }4 Z) k( C2.10 Creating New Types with typedef 45
2.11 Creating User-Defined Structures 46
2.12 Enumerated Types 47
2.13 Constants 51
+ L; x( Z$ {" F7 w$ P2.14 Strings 51
2.15 Expression Width 52
2.16 Net Types 53
2.17 Conclusion 53
* {$ S2 r6 J" C4 }- j) [8 o3. PROCEDURAL STATEMENTS AND ROUTINES 55
3.1 Introduction 55
3.2 Procedural Statements 55
3.3 Tasks, Functions, and Void Functions 56
3.4 Task and Function Overview 57
8 u4 ^$ a& e1 U- w0 |+ D2 Q  ?* B3.5 Routine Arguments 57
3.6 Returning from a Routine 62
3.7 Local Data Storage 62
3.8 Time Values 64
3.9 Conclusion 65
% x/ c& I2 r  b+ E; w4. BASIC OOP 67
5 S0 }' l* Y- H( U  e4.1 Introduction 67
4.2 Think of Nouns, not Verbs 67
4.3 Your First Class 68
4.4 Where to Define a Class 69
4 g" G  L9 H! U, k4.5 OOP Terminology 69
3 c" ~6 K, b  P' W8 }' c0 ]4.6 Creating New Objects 70
$ L" Z& ~( p- N. A8 X4.7 Object Deallocation 74
! S  p7 T* q' H/ D4.8 Using Objects 76
  N; C: D  |/ t, k0 C4.9 Static Variables vs. Global Variables 76
4.10 Class Routines 78
4.11 Defining Routines Outside of the Class 79
4.12 Scoping Rules 81
4.13 Using One Class Inside Another 85
  h; V) f7 [$ b2 q0 x% u4 A% t% d4.14 Understanding Dynamic Objects 87
% D3 p3 J2 t! @0 N0 C& X, Y( V! V4.15 Copying Objects 91
, F& t9 H  n+ k( `: N; |1 ~) l4.16 Public vs. Private 95
Contents ix
' h- T2 B! \6 e( x4.17 Straying Off Course 96
4.18 Building a Testbench 96
4.19 Conclusion 97
+ H+ L8 A2 T) A; E8 _5. CONNECTING THE TESTBENCH AND DESIGN 99
5.1 Introduction 99
; ^: ^$ G* O: U- c4 F5 I3 [- @% z9 z5.2 Separating the Testbench and Design 99
# Q  r8 F: o7 H" u; a( T! d8 _5.3 The Interface Construct 102
$ h, S/ c! D! {3 y7 [  G/ {5.4 Stimulus Timing 108
, @$ a5 A* l& t. X5 x% O/ j4 G- b7 E6 {5.5 Interface Driving and Sampling 114
5.6 Connecting It All Together 121
5.7 Top-Level Scope 121
1 a! ^5 H' c, N/ W) s5.8 Program – Module Interactions 123
5.9 SystemVerilog Assertions 124
8 A2 T# d& @# t2 `$ B5.10 The Four-Port ATM Router 126
5.11 Conclusion 134
6. RANDOMIZATION 135
6.1 Introduction 135
6.2 What to Randomize 136
: |2 w% e$ Y+ o  }# y: I  Q! [6.3 Randomization in SystemVerilog 138
1 o, p0 j9 v2 ?: i% V8 Q# c6.4 Constraint Details 141
9 B% K2 a* Q+ O; F: y8 z6.5 Solution Probabilities 149
6.6 Controlling Multiple Constraint Blocks 154
6.7 Valid Constraints 154
6.8 In-line Constraints 155
6.9 The pre_randomize and post_randomize Functions 156
& u- v0 x8 t' s, M+ ~* h0 M6.10 Constraints Tips and Techniques 158
6.11 Common Randomization Problems 164
) K% `$ ~& T3 o5 b' t6.12 Iterative and Array Constraints 165
& T$ Z4 o0 K; B0 ^' c5 p6 l7 d6.13 Atomic Stimulus Generation vs. Scenario Generation 172
6.14 Random Control 175
$ \: y3 s3 K" l6 M& U% F* B6.15 Random Generators 177
6.16 Random Device Configuration 180
2 K0 M  o2 B7 T+ v& r* ]1 |6.17 Conclusion 182
* U, {2 }& y7 K/ O" i7. THREADS AND INTERPROCESS COMMUNICATION 183
7.1 Introduction 183
# f5 V2 A. b& U( k- o7 v. K7.2 Working with Threads 184
: @6 w. {- ^6 M* q1 ?% r; X1 H6 J7.3 Interprocess Communication 194
7.4 Events 195
; B0 @2 L  ?1 A9 e, Z3 e7.5 Semaphores 199
- K8 s- q5 ?+ V" I$ e9 ]7.6 Mailboxes 201
& P1 I7 d, ~5 Y7.7 Building a Testbench with Threads and IPC 210
x SystemVerilog for Verification
, J% G' T# R2 Q( T* ]9 c( @  @7.8 Conclusion 214
* o0 a9 i& _, x" q9 V$ M8. ADVANCED OOP AND GUIDELINES 215
8.1 Introduction 215
/ ?; D4 J( S- @" b. m0 ?8.2 Introduction to Inheritance 216
8.3 Factory Patterns 221
8.4 Type Casting and Virtual Methods 225
7 G5 E: X0 n9 r5 {4 {8.5 Composition, Inheritance, and Alternatives 228
8.6 Copying an Object 233
. o: Y+ {1 [4 z" @8.7 Callbacks 236
8.8 Conclusion 240
9. FUNCTIONAL COVERAGE 241
9.1 Introduction 241
9.2 Coverage Types 243
9.3 Functional Coverage Strategies 246
0 ?% F- l6 k; A% H9.4 Simple Functional Coverage Example 248
9.5 Anatomy of a Cover Group 251
9.6 Triggering a Cover Group 253
! O0 B# l, J4 m! ~% B9.7 Data Sampling 256
9.8 Cross Coverage 265
9.9 Coverage Options 272
9.10 Parameterized Cover Groups 274
9.11 Analyzing Coverage Data 275
7 l0 H, |* n2 k' P7 I+ ]& X# b9.12 Measuring Coverage Statistics During Simulation 276
' a4 j& Y% q) x( o2 D9.13 Conclusion 277
9 h% V1 R& b$ T  g10. ADVANCED INTERFACES 279
2 X" a9 ~+ I) }: i1 p. K10.1 Introduction 279
10.2 Virtual Interfaces with the ATM Router 279
10.3 Connecting to Multiple Design Configurations 284
10.4 Procedural Code in an Interface 290
10.5 Conclusion 294
$ ^. k8 a; L3 t9 v& {; Z. S/ YReferences 295
Index 297

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