SystemVerilog for Verification

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SystemVerilog for Verification:
5 m2 P3 P5 n3 ]0 n1 ZA Guide to Learning the Testbench Language Features
0 m7 H; H: m, e" \; _3 @1. VERIFICATION GUIDELINES 1
1.1 Introduction 1
! r$ l5 u3 ~0 n" g6 u9 Y1.2 The Verification Process 2
1.3 The Verification Plan 4
/ j. Z3 x7 o# L! l* _) T; V1.4 The Verification Methodology Manual 4
1.5 Basic Testbench Functionality 5
1.6 Directed Testing 5
1.7 Methodology Basics 7
! [* {4 @) z( M1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
1.10 Functional Coverage 13
1.11 Testbench Components 15
1.12 Layered Testbench 16
5 q. \& x5 m1 R1.13 Building a Layered Testbench 22
, C4 H! a5 S: Y! C1.14 Simulation Environment Phases 23
% l6 V9 X- C2 \1.15 Maximum Code Reuse 24
1.16 Testbench Performance 24
6 b' {' b) w- P/ o  @/ _- P. V# m1.17 Conclusion 25
2. DATA TYPES 27
2.1 Introduction 27
- m5 }) ^' G$ m( m3 p2.2 Built-in Data Types 27
) t$ U4 c+ y2 _' J6 @viii SystemVerilog for Verification
+ l: c4 b* K  r2.3 Fixed-Size Arrays 29
3 N& t8 X1 N0 `  @2.4 Dynamic Arrays 34
2.5 Queues 36
8 z8 a# b3 n& w( p/ V2.6 Associative Arrays 37
2.7 Linked Lists 39
2.8 Array Methods 40
! |6 ^6 |- g* l) _$ D2.9 Choosing a Storage Type 42
2.10 Creating New Types with typedef 45
" `/ Z4 [. p9 U5 O, N& H: ^5 A1 Q2.11 Creating User-Defined Structures 46
0 w6 G* ]% ]3 j* j! l; z5 N; ~2.12 Enumerated Types 47
2 y3 p$ e; @. l4 {4 c2.13 Constants 51
2.14 Strings 51
2.15 Expression Width 52
2 [7 z; F# r6 w2.16 Net Types 53
2.17 Conclusion 53
' ~6 G( T0 J. h3. PROCEDURAL STATEMENTS AND ROUTINES 55
  N4 w; M. s: L5 Z! y3.1 Introduction 55
$ p: P" p: R* v# Q1 i/ E3.2 Procedural Statements 55
3.3 Tasks, Functions, and Void Functions 56
4 S5 `: `$ I9 C' y3.4 Task and Function Overview 57
3.5 Routine Arguments 57
: y& ]( z& R- v$ S6 G! R+ T3.6 Returning from a Routine 62
3.7 Local Data Storage 62
8 X9 L) j) Z8 l3 f; D" Z3.8 Time Values 64
* `) j: N' [) c5 n' |3.9 Conclusion 65
, i, ^* u8 k+ S" `8 b: {4. BASIC OOP 67
4.1 Introduction 67
, H% o/ @& i& h2 {0 G0 w4.2 Think of Nouns, not Verbs 67
$ t. a4 l# p/ e$ d9 Z4.3 Your First Class 68
4.4 Where to Define a Class 69
4.5 OOP Terminology 69
2 H" [1 A! O9 |/ P2 E1 F4.6 Creating New Objects 70
2 n2 g/ M7 U% s9 T2 Q4.7 Object Deallocation 74
4.8 Using Objects 76
1 V  y9 e, Q  s" m- I% E1 p; z' l4.9 Static Variables vs. Global Variables 76
4.10 Class Routines 78
' c) Z, M- V& G$ j4.11 Defining Routines Outside of the Class 79
7 O( ]1 G& M; W/ j3 u4.12 Scoping Rules 81
4.13 Using One Class Inside Another 85
4.14 Understanding Dynamic Objects 87
; l+ @6 v- F7 v+ B  W4.15 Copying Objects 91
4.16 Public vs. Private 95
. z! M4 `5 {; j1 x" vContents ix
4.17 Straying Off Course 96
6 s) o  X3 R1 F" R9 x8 n4.18 Building a Testbench 96
4.19 Conclusion 97
5. CONNECTING THE TESTBENCH AND DESIGN 99
9 V3 g7 D" y: F3 s4 Z$ T5.1 Introduction 99
5.2 Separating the Testbench and Design 99
. m" b6 W4 d$ L' ~1 R; W5.3 The Interface Construct 102
( E! r( w5 I6 }1 w/ q9 b5.4 Stimulus Timing 108
5.5 Interface Driving and Sampling 114
0 s+ Q6 g0 V/ H! q+ v5 u5.6 Connecting It All Together 121
5.7 Top-Level Scope 121
5.8 Program – Module Interactions 123
# ?" o% B$ o; I5.9 SystemVerilog Assertions 124
: ]- n' ~5 c3 M& X; O  f6 [0 A5.10 The Four-Port ATM Router 126
. V0 J# b# H5 P5.11 Conclusion 134
6. RANDOMIZATION 135
6.1 Introduction 135
" C" j! @/ s1 C  h6.2 What to Randomize 136
! }6 j" U% H1 M& X; h$ A6.3 Randomization in SystemVerilog 138
! P" s; A# n7 [. p6.4 Constraint Details 141
" f  i1 l4 I1 A' J$ e( G2 Y6.5 Solution Probabilities 149
: X! U- u! F+ P+ G4 O6.6 Controlling Multiple Constraint Blocks 154
6.7 Valid Constraints 154
6.8 In-line Constraints 155
6.9 The pre_randomize and post_randomize Functions 156
6 b2 L+ Y% h' h: U: c$ [6.10 Constraints Tips and Techniques 158
6.11 Common Randomization Problems 164
, i% M# l( k2 S5 |/ @0 V' Q6.12 Iterative and Array Constraints 165
& l. f' q) `, M& y/ d6.13 Atomic Stimulus Generation vs. Scenario Generation 172
6.14 Random Control 175
4 e3 U9 M( S0 T8 R& X6.15 Random Generators 177
: t( H; k, ]4 L0 f9 Z6.16 Random Device Configuration 180
6.17 Conclusion 182
- l0 q* [3 b; K: s( Y1 ?( Q7. THREADS AND INTERPROCESS COMMUNICATION 183
7.1 Introduction 183
* K0 z& ]5 i! D) y7.2 Working with Threads 184
( E8 `9 V  z. L, P7.3 Interprocess Communication 194
7.4 Events 195
' n/ t2 B& N8 s9 y  T( x4 H/ c6 d7.5 Semaphores 199
7.6 Mailboxes 201
8 k, z& j; G! p( \+ f# F  o7.7 Building a Testbench with Threads and IPC 210
x SystemVerilog for Verification
7.8 Conclusion 214
8 m1 R- a. r; G1 H3 E9 ~6 K$ ^8. ADVANCED OOP AND GUIDELINES 215
  \- p$ @. M8 u1 Y8.1 Introduction 215
8.2 Introduction to Inheritance 216
7 ~2 b2 w0 I' X5 A3 G+ u8.3 Factory Patterns 221
4 f( Z0 \; N* {9 I: \, y( y4 T. R8.4 Type Casting and Virtual Methods 225
$ A1 _2 j; s4 [8.5 Composition, Inheritance, and Alternatives 228
8.6 Copying an Object 233
8.7 Callbacks 236
8.8 Conclusion 240
9. FUNCTIONAL COVERAGE 241
9.1 Introduction 241
: h8 j7 G9 j9 ~9.2 Coverage Types 243
) B5 f0 @$ q1 w8 v" L5 w9.3 Functional Coverage Strategies 246
& i- d: B( ]9 _% ?! d: {- k- Z9.4 Simple Functional Coverage Example 248
' i* T, ]. \! O" m9.5 Anatomy of a Cover Group 251
9.6 Triggering a Cover Group 253
9.7 Data Sampling 256
9.8 Cross Coverage 265
* D2 G; q$ ?! c& B, Q9.9 Coverage Options 272
9.10 Parameterized Cover Groups 274
; X0 K' Q- h* B8 C9.11 Analyzing Coverage Data 275
9.12 Measuring Coverage Statistics During Simulation 276
9.13 Conclusion 277
8 |  T3 p3 @( C/ }2 ^10. ADVANCED INTERFACES 279
8 j: u: T. q1 g' b3 i) Z! h! C/ d10.1 Introduction 279
" b8 z2 \6 @" e0 o7 C3 ]9 K10.2 Virtual Interfaces with the ATM Router 279
. K% g/ {. |5 B10.3 Connecting to Multiple Design Configurations 284
1 L) S& g; e7 R6 ]* K, C/ V- F10.4 Procedural Code in an Interface 290
10.5 Conclusion 294
References 295
. \  |( v: m# J2 p/ Z* dIndex 297

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