求助！模块分析，十万火急，望各位大大分析下啊

amd521

我做的是出租车计费系统，VHDL语言做的，也就是从网上下载的。请问一下下面的程序中SE模块和DI模块是干什么用的啊？拜托帮忙，快答辩了！3.3.1
" N: V/ @$ r! \# m模块
& j5 v! T; j7 g! ?) q' ?  X! Y$ WJIFEI
的实现

该模块是模拟汽车启动，停止，暂停加速。模块如图4：

CLKSTART CHEFEI[12...0]STOP LUC[12...0]PAUSEJS 8 @- `, z& N  p  l5 R

! K  U5 A% W$ c5 r( u  _

图 4
9 u, X8 P% ]0 s- P  F! wJIFEI模 块

输入端口
' g' j7 I: B! y  \% j  |1 [8 L6 JSTART、STOP、PAUSE、JS
! [% |  [/ Q- n- m3 E0 v" d分别为汽车起动、停止、暂停、加速按键。程序如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity jifei is

port (clk,start,stop,pause,js:in std_logic;

chefei,lucut integer range 0 to 8000);

end jifei;

architecture rtl of jifei is begin process(clk,start,stop,pause,js) variable a,b:std_logic;

variable aa:integer range 0 to 100; variable chf,lc:integer range 0 to 8000; variable num:integer range 0 to 9;

begin if(clk'event and clk='1')then if(stop='0')then

chf:=0;

num:=0;

b:='1';

aa:=0; lc:=0; elsif(start='0')then b:='0';

chf:=700;

lc:=0;

elsif(start='1' and js='1'and pause='1')then if(b='0')then

num:=num+1; end if; if(num=9)then lc:=lc+5; num:=0; aa:=aa+5;

end if;

elsif(start='1'and js='0'and pause='1')then lc:=lc+1;

aa:=aa+1; end if; if(aa>=100)then a:='1';

aa:=0; else a:='0'; end if;

if(lc<300)then null;

elsif(chf<2000 and a='1')then chf:=chf+220;

elsif(chf>=2000 and a='1')then chf:=chf+330;

end if;

end if; chefei<=chf; luc<=lc;

end process;

end rtl;

3.3.2
模块
' a; v8 x- l5 vX
的实现

模块X见图5。该模块把车费和路程转化为4位十进制数，daclk的频率要比 clk快得多。

AGE[3...0]        ASH[3...0]DACLK ABAI[3...0]ASCORE ' Z2 `) T% x; x# IAQIAN[3...0]BSCORE BGE[3...0BSHI[3...0]BBAI[3...0]BQIAN[3...0] / E- S7 K: K* M- L

5 \7 \; R& P7 T/ `* q2 @

图5 X模块

该模块的程序如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity x is

port(daclk:in std_logic; ascore,bscore:in integer range 0 to 8000; age,ashi,abai,aqian,bge,bshi,bbai,bqianut std_logic_vector(3 downto 0)); end x ;

architecture rtl of x is begin

process(daclk,ascore)

variable comb1:integer range 0 to 8000;

variable comb1a,comb1b,comb1c,comb1d:std_logic_vector(3 downto 0);

begin

if(daclk'event and daclk='1')then

if(comb1<ascore)then

if(comb1a=9 and comb1b=9 and comb1c=9)then comb1a:="0000";

comb1b:="0000"; comb1c:="0000"; comb1d:=comb1d+1; comb1:=comb1+1;

elsif(comb1a=9 and comb1b=9)then comb1a:="0000";

comb1b:="0000"; comb1:=comb1+1; comb1c:=comb1c+1; elsif(comb1a=9)then comb1a:="0000"; comb1b:= comb1b+1; comb1:= comb1+1; else

comb1a:= comb1a+1; comb1:= comb1+1; end if;

else

ashi<= comb1b; age<= comb1a; abai<= comb1c; aqian<= comb1d; comb1:=0; comb1a:="0000"; comb1b:="0000"; comb1c:="0000"; comb1d:="0000"; end if;

end if;

end process;

process(daclk,bscore)

variable comb2:integer range 0 to 8000;

variable comb2a,comb2b, comb2c,comb2d:std_logic_vector(3 downto 0);

begin

if(daclk'event and daclk='1')then if(comb2<bscore)then

if(comb2a=9 and comb2b=9 and comb2c=9)then comb2a:="0000";

comb2b:="0000"; comb2c:="0000"; comb2d:=comb2d+1; comb2:=comb2+1;

elsif(comb2a=9 and comb2b=9)then comb2a:="0000";

comb2b:="0000"; comb2:= comb2+1; comb2c:= comb2c+1; elsif(comb2a=9)then comb2a:="0000"; comb2b:=comb2b+1; comb2:=comb2+1;

else

comb2a:= comb2a+1; comb2:= comb2+1; end if;

else bshi<=comb2b; bge<=comb2a; bbai<=comb2c; bqian<=comb2d;

comb2:=0;

comb2a:="0000";

comb2b:="0000"; comb2c:="0000"; comb2d:="0000"; end if;

end if;

end process;

end rtl;

3.3.3
4 C* }% O! n. j2 T# K模块
/ U# r6 R: v: @6 m+ e1 yXXX1
; ]! a3 p( |. @/ b' N实现

模块XXX1见图6。经过该八进制模块将车费和路程显示出来。该设计采用的是共阴极七段数码管，根据16进制和七段显示段码表对应关系，用VHDL的CASE语句可方便的实现他们的译码。

动态扫描时利用人眼的视觉暂留原理，只要扫描频率不小于34HZ，人眼就感觉不到显示器的闪烁。本系统24HZ的扫描脉冲由相对应的外围电路提供。动态扫描电路设计的关键在于位选信号要与显示的数据在时序上一一对应，因此电路中必须提供同步脉冲信号。

C[2...0]A1[3...0]A2[3...0] A3[3...0] ( L( l) r" [7 o# z $ v4 X  Z# I% A2 J$ gDPA4[3...0]B1[3...0] % W$ h6 H0 {7 W& ^: P 2 F  w: g+ C, ?D[3...0]B2[3...0]B3[3...0]B4[3...0]

: k  E8 q! @8 J. m+ `3 O

图 6 模块XXX1

这里采用八位计数器提供同步脉冲，VHDL语言如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity XXX1 is

port(c:in std_logic_vector(2 downto 0);

dput std_logic;

a1,a2,a3,a4,b1,b2,b3,b4:in std_logic_vector(3 downto 0);

d:out std_logic_vector(3 downto 0));

end XXX1;

architecture rtl of xxx1 is begin process(c,a1,a2,a3,a4,b1,b2,b3,b4)

variable comb:std_logic_vector(2 downto 0);

begin

comb:=c;

case comb is when”000”=>d<=a1;

dp<=’0’;

when”001”=>d<=a2;

dp<=’0’;

when”010”=>d<=a3;

dp<=’1’;

when”011”=>d<=a4;

dp<=’0’

;
6 N0 S+ m# X* u# ?3 Kwhen”100”=>d<=b1;

dp<=’0’;

                  when”101”=>d<=b2;

dp<=’0’;

7 J% m5 {+ ]* l8 G' Q+ uwhen”110”=>d<=b3;

dp<=’1’;

when”111”=>d<=b4;

dp<=’0’;

when
others=>null;

end
2 F# q; ]3 `9 D1 ]. ycase;

end
( Y$ a" @5 P- |6 O. ?1 Fprocess;

end
7 h  K& c6 Y$ ^6 T* J; w; H  srtl;

3.3.4
模块
SE
( k- k) Z% O4 w- M; Y& J的实现

模块
SE
; \+ A, r) Z! j见图
* R% |/ F+ l* U+ x  D: n7：该模块是系统检测模块。

CLK 5 h+ l. P6 i$ r: x ( v' a0 A; j7 Q# a& J) `% CA[2...0]

图
& k) a5 F' \# k  S7 l! D1 K7
SE模
0 _' K4 O+ }: q* O块

模块SE程序如下：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity se is port(clk:in std_logic;

a:out std_logic_vector(2 downto 0));

end se;

architecture rtl of se is begin

process(clk)

variable b:std_logic_vector(2 downto 0);

begin

if(clk’event and clk=’1’)then if(b=”111”)then

b:=”000”;

else b:=b+1; end if; end if; a<=b;

end process;

end rtl;

3.3.5
模块
DI
  P, S. K' E' W, \7 Q的实现
, `9 V8 u; x" U) {

模块DI见图 8

D[3..0] 6 }% u/ o1 [" R% J & M# l7 X2 n! G" h: q& iQ[6..0]

2 Z  _3 Q- L' F* r2 q! F

1 ~  p" V; l9 ~4 a: F0 ~

( ?# \: d0 E+ D2 T5 L9 g, @& S, j4 Q
! t  b( `+ ]* R! N; O图8 DI模块

模块DI的程序如下

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity di is

port(d:in std_logic_vector(3 downto 0);

q:out std_logic_vector(6 downto 0));

end di;

architecture
! u( |2 x7 e7 X) H! t- Artl of di is begin

process(d)

begin

case d is when”0000”=>q<=”0111111”;

when”0001”=>q<=”0000110”;

when”0010”=>q<=”1011011”;

when”0011”=>q<=”1001111”;

when”0100”=>q<=”1100110”;

when”0101”=>q<=”1101101”;

when”0110”=>q<=”1111101”;

when”0111”=>q<=”0100111”;

when”1000”=>q<=”1101111”;

when others=>q<=”1101111”;

end case;

end process;

end rtl;

leiyanjiao

怎么分析呀，图看不到呀
) p9 S9 ^  ]. i1 U( UVHDL忘记的差不多了
6 O7 c  ?' _8 O外面的公司，用VERILOG的多些

amd521

回复 2# leiyanjiao
* ?+ W: z! _( k0 s5 c

    额，谢谢啊