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刚接触SQ仿真,遇到如下问题,请高手们不吝赐教:
+ l$ w. H* G" X' k; J& V2 `6 Q1.将IBIS模型转化为dml格式后,在Signal Model Assignment界面下,赋给芯片相应的模型后,发现芯片有部分管脚使用赋给的模型,而部分管脚却使用系统黙认的模型,这是为什么?编辑模型时,提示错误如下:! i+ S6 V" p- s# e8 p- |4 e+ B
model Hi3520V100_PBGA768 defines pin Y04 which doesn't exist in component SN2116_V83_FINAL U9! Z% Q0 p' [1 }1 E5 w
model Hi3520V100_PBGA768 defines pin Y03 which doesn't exist in component SN2116_V83_FINAL U9, u( N* Y U4 t- E
model Hi3520V100_PBGA768 defines pin Y02 which doesn't exist in component SN2116_V83_FINAL U9
7 d5 R3 M y+ a: D6 d8 Umodel Hi3520V100_PBGA768 defines pin Y01 which doesn't exist in component SN2116_V83_FINAL U9$ ^5 Z6 k/ f8 P. r
model Hi3520V100_PBGA768 defines pin W04 which doesn't exist in component SN2116_V83_FINAL U9 |, z+ P! ^% f. y* e+ y
model Hi3520V100_PBGA768 defines pin W03 which doesn't exist in component SN2116_V83_FINAL U9
( h! \* y# M4 d# Q0 I, Amodel Hi3520V100_PBGA768 defines pin W02 which doesn't exist in component SN2116_V83_FINAL U95 H; O) @% { {. ]1 X& ^
(注 该芯片是PGA封装,且厂家提供的PIN管脚是字母加数字的)
& n/ @8 _, D, R+ h2.提取网络时,在点击Reports查看报告和Waveforms查看波形时,弹出如下警告:) u4 i t2 L0 F c6 y
WARNINGS:; U: u; ~% [4 Z3 J; W
No 'V Measurement' is defined in the delay measurement fixture of model ATP8624_SP018W_PCIX. The buffer delay is assumed 0.2 h' e m7 g; |' M* J0 w
这是什么原因造成的?会产生什么影响?; H# _' ^* L6 X
再次谢谢大家。 |
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