六十进制计数器错误

淼森 · 发表于 2011-10-12 15:43

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六十进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_60 is
      port(clk,bcd1wr,bcd10wr,cin:in std_logic;
               co: out std_logic;
               datain: in std_logic_vector(3 downto 0);
               bcd1: out std_logic_vector(3 downto 0);
               bcd10: out std_logic_vector(2 downto 0));
end counter_60;

architecture rtl of counter_60 is
signal bcd1n:std_logic_vector(3 downto 0);
signal bcd10n:std_logic_vector(2 downto 0);
begin
      bcd1<=bcd1n;
      bcd10<=bcd10n;
      process(clk,bcd1wr,datain) is
      begin
            if(bcd1wr='1') then
                     bcd1n<=datain;
            elsif(clk'event and clk='1') then
                     if(cin='1') then
                              if(bcd1n=9) then
                                    bcd1n<="0000";
                              else
                                    bcd1n<=bcd1n+'1';
                              end if;
                     end if;
            end if;
      end process;

      process(clk,bcd10wr,datain) is
      begin
            if(bcd10wr='1') then
                     bcd10n<=datain(2 downto 0);
            elsif(clk'event and clk='1') then
                     if(cin='1' and bcd1n=9) then
                              if(bcd10n=5) then
                                    bcd10n<="000";
                              else
                                    bcd10n<=bcd10n+'1';
                              end if;
                     end if;
            end if;
      end process;

      process(bcd10n,bcd1n,cin) is
      begin
            if((cin='1') and (bcd1n=9) and (bcd10n=5)) then
                     co<='1';
            else
                     co<='0';
            end if;
      end process;
end rtl;
可以编译，但是仿真不合适，仿真不计数，请各位老师同仁指正，万分感谢

alec4050 · 发表于 2012-2-24 17:12

把赋值放到前面去，怎么会变， bcd1<=bcd1n;
bcd10<=bcd10n;放在最后

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六十进制计数器错误

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