错误如下 / ~. r; W' m% p9 k% L- jERRORack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which3 I% f9 }; r% M; t' r
require the combination of the following symbols into a single SLICE9 L& I/ A# m8 j
component: % U5 O% Y( i0 ~& X+ \6 h1 a FLOP symbol "Chain[37].uChain/Node[0].uNode0/uFdce" (Output Signal =, B; Z: x, F& q* a# t: R1 v
Chain[37].uChain/wOutA0<0>) , N! Q$ T+ ~. e FLOP symbol "Chain[37].uChain/Node[0].uNode1/uFdce" (Output Signal = ^* L+ \4 s4 Y8 i. K) v, d2 P Chain[37].uChain/wOutA1<0>) - W H) h! u3 K9 _) e/ F2 U2 O The set/reset signal Reset_IBUF_1 of register2 R% c% b& v6 |
Chain[37].uChain/Node[0].uNode1/uFdce doesn't match the existing usage of the ! m, ^# K9 h0 W' e, T- W SR MUX. The signal Reset_IBUF_2 already uses SR. Please correct the design7 b( H- m& P; b2 _5 k2 |
constraints accordingly.2 A$ x+ Z) {$ Z. j) e1 x
请大侠帮忙
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发表于 2012-6-8 17:35
ack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which3 I% f9 }; r% M; t' r
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