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Since the earliest days of microprocessors, system designers have been plagued by a problem in which the
% |9 p: t; M' R, L! l3 e8 ?speed of the CPU's operation exceeded the bandwidth of the memory subsystem to which it was connected.$ f. ^: U" f% b$ P& O8 f
To avoid wasting CPU cycles while waiting for the memory to fetch the requested data, the universally# x3 k, \6 y7 M* O" \3 f
adopted solution was to use an area of faster (and thus more expensive) memory to cache main memory data.
! n, a1 I. a k( ~+ s9 R% P9 ^# S& ?4 }; kThis solution allowed the CPU to operate at its natural speed as long as the data it required was available in
3 B9 N( H w3 x4 s p. kthe cache. |
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