请帮我看下下面的代码错在什么地方，谢谢！

freeunix · 发表于 2013-7-24 15:01

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我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书，下面的代码是本书的第第一章的第三段代码，我使用QII 11.0WEB版本无论如何无法正确编译，总是提示10559错误，请各位高手帮我看下问题所在，谢谢！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter8bit is
  port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));
  end counter8bit;
architecture counter of counter8bit is
   signal count_in: std_logic_vector( 0 to 7);
   begin
   process(input,reset)
      begin
      wait until rising_edge(input);
   if reset='1' then
   count_in<=(others =>'0');
elsif enable= '1'  then
   if (count_in="11111110")  then
      count_in<="00000000";
   else
   count_in<=count_in+1;
   end if;
   end if;
   end process;
   end counter;


lInfo: *******************************************************************
Info: Running Quartus II Create Symbol File
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
Info: Processing started: Wed Jul 24 14:43:41 2013
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
Info: Processing started: Wed Jul 24 14:43:41 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_
Error (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared
Error (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"
Error (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared
Error: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings