8片 DDR Layout Guidelines and Topology:

tzwhzf

Layout Guidelines and Topology:
The following are the routing guidelines followed for DDR memory interface section:
1. Controlled impedance for single ended trace is Z0 = 60 ohm.
, @% W* x' b$ Q5 b0 G* K; m2 q2. DQ, strobe, and clock signals are referenced to VSS.
3. Address, command, and control signals are referenced to VDD.
, m2 I: [, s: M' h3 t5 A1 _% V1 V4. The length of address, command, and control signals are matched to clock with +/- 100 mil
tolerance.
5. DQ <0..7> & DM signals are length matched with respect to DQS with +/- 100 mil tolerance
(byte lane).
; _/ N2 V# V$ x7 m+ n6. Each byte lanes are routed on same layer.
/ V. _0 e, h) v) u! K# f7. Byte lane to byte lane is matched to clock with +/- 500 mils.
# \2 u6 n( n) n$ Z3 @9 t8. CK & CK# are matched with +/- 30 mil and are routed as diff pair with 120 ohm differential
8 z2 ~8 q7 h4 c! c- H$ q/ ?impedance.
2 o+ ^1 ?$ c4 g: \2 C4 h. i7 R+ e9. Clock - pair to pair matching tolerance is +/- 30 mil.
10. Trace to trace spacing is 2X and signal group to group spacing is 3X.
2 R5 O" I0 M* L11. DQS signals are routed in the middle of the byte lane (DQ<0..7>).
3 g3 k3 r7 T! D8 D) M$ r/ v7 o12. Clock trace split point to DRAM is less than 1 inch.
; U$ O  E. R3 j3 c! {  u5 ]13. VTT and VREF islands are separated with the minimum spacing of 150mils.
1 z% ]) a9 m' c, \1 z14. VTT island width = 150 mil min.; 250 mil preferred.
15. VREF signal is routed with 20–25 mil minimum trace.
15. All signals are routed with minimum of 3X spacing between other signals
) [, e+ I4 c6 W! W! }16. Layer biasing is followed for dual strip layers.
Figure 1 shows the data bus topology and figure 2 shows the address/control bus topology.

tzwhzf

元件放置方法：
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# q' C+ M+ t. Q数据线拓扑：
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! z. w6 }* U. P- [& {) _: w地址线拓扑：
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+ l2 Y! p! S: h9 x% ^$ p时钟线拓扑：

一粒沙

瞄 画个立体的更直观
8 A( ?# d$ }- @% ?2 }

xieyifu

谢谢楼主，学习了

wanghanq

原档

lbq211

谢谢楼主、楼上的