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本帖最后由 lvsy 于 2014-4-16 10:05 编辑
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; H |7 u* Q# G2 }" f* u. {可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。9 n& d- j- o5 x
" k8 o# O' Y& t: \0 e1 y' i如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。* ~8 ~$ p' x& }( A- K
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The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The
: {+ c# h0 b6 E, J f5 Uconfiguration interfaces include the JTAG pins in bank 0, the dedicated configuration pins
" v3 {6 E7 D" @. X+ O/ e3 @in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To* [- z( D7 [. ~1 m ?6 s
support the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,2 \! b4 _) W; F6 J) t
the following is required:( G0 @2 r" h$ E* g/ Q, E' F
• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)6 z) `4 s* G6 _) P
or Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15: f, k, x6 ~1 ~4 \+ ~$ \0 z
for 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for" N4 R# I4 Q1 I- T
1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V
% |: X2 y* W( ^2 o% v(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for
3 \ W) s2 Q& S/ t! l4 |( Oconfiguration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.$ T; s, I+ o: l) I/ K
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发表于 2014-4-15 18:32
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