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更新内容：: g0 w8 c y# w8 _
DATE: 03-29-2013 HOTFIX VERSION: 0069 Y* m+ G) k' j6 h3 T, }) \1 {
===================================================================================================================================
; }" p; H9 Z4 Y& M1 f; r* Y! b. y1 aCCRID PRODUCT PRODUCTLEVEL2 TITLE
# f U8 o$ l1 `5 ?4 z! O===================================================================================================================================
" ]& D( d5 J& H) y$ [5 }* W6 B; Y110139 FIRST_ENCOUNTE GUI Error in Save OA Design form4 `+ W6 U# W: e# f' |! L- x* }9 t
625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.
, h% ]2 V3 S8 g' W642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep
' D4 V" q" F9 F- Q F' D650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".
: m- J& D4 S0 p/ s653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend6 Q7 q) |. i0 o1 K
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect/ n# X" s- p2 I4 t! {
787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics- Q. N8 b d# S1 g1 U! A- i) W
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other
d$ t2 M* d/ y834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming
& f, P2 t1 @8 _6 }2 Q835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol.9 v; N4 L' J; a( T
868981 SCM SETUP SCM responds slow when trying to browse signal integrity
; ]5 u- U6 A4 k X* y% X, m/ e871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
% d- W( c' s3 e D- M' h8 @873917 CONCEPT_HDL CORE Markers dialog is not refreshed) \+ D& ^# @ e
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License# ? N# b/ E8 {7 }
888290 APD DIE_GENERATOR Die Generation Improvement1 L8 R" s0 B8 Y2 [5 ?5 F' V
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator; t/ O9 h0 H8 A' n9 U! E3 Z2 {5 M
902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice1 P8 @( w& V( _: W1 Z/ h
908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM
8 u: L M6 h3 }6 W% ?922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols4 X' u) a8 ~/ l( k
923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences
& r- o# F9 ], C; L; C935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC, j) R4 B8 ^7 t! N& j8 |" O
945393 FSP OTHER group contigous pin support enhancement
! X' W' W1 k/ z* }0 Z' X1 R* k969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database
. j) ?' B/ W+ M1 Z* L' S0 u9 n1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
, Y# w2 `' x7 _4 w3 i1 [6 b1005812 F2B BOM bomhdl fails on bigger SCM Projects
3 B V, B1 F( k1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture# w4 ~3 D3 N* n4 L& y
1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names
, u: F% o* Y. s0 m3 _2 }1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net5 R f: r2 z: l% S
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
- q ~# v2 Y. G2 h- b3 s1032387 FSP OTHER Pointer to set Mapping file for project based library.+ P) ~8 C) n! a) A0 ~
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 縋LL PLL_3 does not exist in device instance�3 Y( F, _6 d2 I
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart
; b0 ~* S T: _" q1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding# |' l+ E) X0 a; ^+ \4 R
1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages., r; Q% x5 D8 B) _! O: `3 @+ \, y
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type( ^" g. I- e' b& {5 E3 i& i# N) d
1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll# g$ V( l/ w; U8 N+ n0 W, F* j( |1 X1 \2 V
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation
) F7 o; |6 d& [0 n+ p: F( d) g3 E1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects
$ F/ E* ]) l' v8 G1 _4 h1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus5 F1 c) `. Q% d3 l7 L
1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts( Y3 Y- K7 V0 k3 G5 l( Q+ F' m
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs
/ O1 ~2 z8 P& e5 |1065636 CONCEPT_HDL OTHER Text not visible in published pdf
: w, B+ J4 ?" ]/ U) f3 ^. |1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings
7 z# O2 W* V% Z; n! x! T1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary
% W% p$ B* L' l8 u1 o, U1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts) L: m$ t/ U5 Z2 F: S( u) J7 s
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic
7 r2 X, B ~0 {1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down
" y0 J8 {2 a* U/ _. _# N1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45
" g4 e+ b: [5 F4 }6 X% g' I1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal% U% L E' E) c3 w9 T2 V! ~, ^
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
0 j( M% q# J& N& w1 v1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.3 r ]* D$ m2 o9 \+ U6 U a
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3)
' u) ~4 o. P1 D! G, Q1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die
& X0 I# ?& U7 F) `3 G& g: k5 K P1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic
3 E$ Y+ a: O' y0 G O# c$ B# Y) ] s1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut
2 P6 H& |- a# d8 Z/ O1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects" H- K9 h( T( r& v* W( j
1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format
& S" E% C% Z2 p" T' G- E1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net- J3 J) S) o3 d/ Y3 m. Z
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic. D& E9 g, a+ f
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible0 |3 C) z$ t; @3 v3 q2 z/ Z( `
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars.3 N3 F0 w3 ^& n
1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently.
/ Z! @$ n5 Z% b1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors+ a/ E- d$ F) ?3 D
1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.( e- n" y1 D& l x" P4 q: f0 L: }
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition
; a e6 l' k% l Q+ D. c# D1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor1 _) T" e. R% _6 Y/ k0 i3 X9 Y
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options4 _) O9 g* t( L9 `% X$ f5 C' k( _
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5- f) G' {4 x Z6 R. F: b/ Q/ T
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file.$ I- b3 H; q/ L4 K1 Z' A# a
1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate
2 M, n2 W7 z( N e! v1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 3
2 f: Q8 g+ H9 ~' Y' X1078270 SCM UI Physical net is not unique or not valid1 g& Z; N1 ]2 s+ h3 y8 x
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted: v& b3 u; l, `) ^) _/ Q0 T
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle6 w1 p; r- E8 c- }7 A. O( H$ x
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs, l' v" t, C4 r
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"# I* V1 H2 |5 s; ?5 m! R" y- @
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters
6 J, d: \. E7 B! X) l1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
7 A) D8 @2 W% L2 o4 s3 H1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license
% q8 b7 N5 K: B/ R, x# `, M v1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd
) _: p; c$ @' Q4 l1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error+ `3 s4 v3 b2 Q+ E
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated.0 V% v: T8 ` P# c
1081760 FSP CONFIG_SETTINGS Content of 縁PGA Input/Output Onchip termination� columns resets after update csv command
6 L0 K- T" B$ U# I1082220 FLOWS OTHER Error SPCOCV-353% J) F, Z" r0 d3 o2 J4 ~( W1 N5 n
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols.5 q3 d9 y9 a( C
1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command
0 a5 u5 f, [# t' t1082737 CAPTURE GENERAL The 緼rea select� icon shows wrong icon in Capture canvas.9 _1 y" _' G0 B
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name
! F( ~5 M. g) c/ n& O; w) V1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
- Y/ f: b9 n8 n4 }4 V1 }. \1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher' G, i) [! C* m8 B
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI; b& A: |6 g7 m' a* t9 V
1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file
9 g1 _/ d) A* \7 U1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void.
- C- s2 b% R6 f" V7 E5 D3 i1 [1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates
+ i& w0 I+ Z& U5 h) `# d! W Z1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters% ]: n u3 [! `, g) F; n$ I5 ?$ s% M4 V5 W
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.
2 u1 S" A9 N$ s/ J& M: j @1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results- z7 [% C7 f* C W
1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file.
8 F* N7 a' i4 K. W% ^7 ^1085891 ALLEGRO_EDITOR INTERACTIV about DRC update7 t& e/ W ?9 d" Q) L2 r
1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO
2 d7 w: d( m/ m- E/ T) `9 Q1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working1 K9 T* v- `/ ^' D o) v
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
( g4 ~+ f2 g: f; n V1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design
1 Z1 V/ i) W4 R/ u1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated
9 H2 k; E5 P8 i+ D5 B9 ^1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins3 Y( ^; K6 x! Q2 o2 R5 q( o! h
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
- d4 y" s* p' c$ Z1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times.
5 i/ Z+ ?: I3 }. s. Z% S5 m1087221 CONCEPT_HDL OTHER Part manager could not update any parts.
& C' a* g) U5 e0 D" {1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space
0 Y( v8 A3 y9 [# ^# T8 J( f1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too
U, [0 G# X% ?( F5 B" @( e1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice+ S6 Z% o* g) ~/ |6 s% D. J
1088231 F2B PACKAGERXL Design fails to package in 16.5$ J) B- e! Z9 Z$ J
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.. D0 C. ^/ i% m$ C) p8 Z& ]
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor
. `" M1 L! |3 Q1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager6 A2 i: X3 O B0 s4 W
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?( G$ K+ x. M) g4 W3 ^7 \- u; ], f
1089259 SCM IMPORTS Cannot import block into ASA design% e# u1 c- H7 Q7 E
1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form
4 B3 v/ P7 S* \( M1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project
( ] T8 h! _% \6 k. e0 S9 p& Q' |9 s1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory
, V7 q, G6 q6 ?: C9 h# |+ v3 L1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor.
" k: u. w2 v0 l( H' s1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165
2 `8 J6 b0 d5 D1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message.
5 ~; p2 f7 L8 D7 o% [1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-228 U- w0 a: D, `% t9 l& Y
1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet.
3 d9 y4 x) _5 L% G7 y! p# a1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation.
8 ^- q8 W; X0 L6 ^, u w9 T! C1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled
2 O9 @1 j/ p0 m6 d$ z: U1091359 CAPTURE GENERAL Toolbar Customization missing description
8 v2 @4 {! o- d# T% {1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive
! H( w7 {& Q% r* N3 H* N# p1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time
% \9 B/ v0 S1 p; {- m1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5
% @) v- T( l7 H5 Z& i1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design1 [$ [4 t$ ~* C1 e$ T8 L
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled6 R& s1 C8 I3 V! s3 y, l
1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters) s: ^% ^6 O+ E7 M, c, K
1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error
: N7 R+ m% x1 k/ Z/ P* y2 [; A1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder
3 q `% \2 X0 w3 L5 J1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor
7 Z% H; u" q. p' O5 U1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license.
w( U( [' l6 _& a' r5 m1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time' d' }9 x1 Z3 X
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save.% L9 O) R4 e: o/ g
1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?
5 L- N. z: U. Q, v9 G1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic1 W8 r/ ]+ w% h
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.52 l. Z: Q9 M# L; o# p' V
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet: I$ @; O+ {1 ]9 {; u. m; c
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die# ` ?0 z# ]9 v$ W# ?' {/ Y- M
1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block) t& A7 T. p- J; b$ l$ s+ z
1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3* X- R( A' ~( o: X
1095861 F2B BOM Using Upper-case Input produces incorrect BOM results5 v; ~7 P: t. O1 v- f# S& `; g" a
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import6 I. v" E1 R) G6 a% x% _( U
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically
" I' x! o" }# `; s) d1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias: m s& I* I; {( m+ D. \! [2 R
1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate
( W3 Q1 b. u6 A0 H0 Y! \1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors
}' e( k, d) A1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL
1 B# E* X$ T; J' R2 v3 \, {1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.
, K$ G# b( T1 s: K. M9 G/ c. w1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side7 ]0 w$ ?4 M, c' {
1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command
) o+ R0 p" |/ ^! ~1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character.
$ c6 A5 i* i! ^1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives+ o* m/ |- _5 o
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork. L4 U: l" }% W! U/ U+ v( _7 s
1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts
( d0 ]5 P* }' V1 I' n- N9 G' L1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy
# }) L. Y) J# j; y2 {1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances.
- u( U7 ]' }: {! p; Q1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties7 c5 [4 |6 q+ b) H, U6 ~% {& `- _
1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.6
9 L! F0 A. N% e/ z2 ]" L# ]1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad0 J' f! _) k& Q+ [% x7 o0 h A+ a
1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3' k. `. g/ s% R
1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad
6 T) G" n4 ~ E2 V9 x0 ^1 c& z1 u1103703 F2B DESIGNSYNC Toolcrash with Design Differences
* }+ G4 b% D4 I6 R9 ?1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view5 ^/ z/ ~% t, u
1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6% X1 v2 x/ Z1 q5 \
1104121 PSPICE AA_OPT 縋arameter Selection� window not showing all the components : on WinXP
9 |5 h: | A6 h+ Z. A; {8 g# G1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly5 Z8 ^& [% b/ N- k L3 l1 e& U. k! }8 Q
1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM
( @ q! |9 K; r5 z1 d$ T1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule.
5 F6 n7 e8 N* F1 \/ L5 I1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires.9 C- @& W* g) a/ r J) G9 t
1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form
% x: d+ n2 {+ c; x1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part
* ]2 R0 O3 C, f: V1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked
1 K: [& p* d- F8 y* \' `9 J1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax k8 _. g+ ~4 b% i& g" f: P
1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6
' T$ e: T3 R5 S# ]" f1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only
. j0 k& }0 D0 t( N5 K& d# T! ]' l1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid
, \9 Y9 y0 i3 q. S/ H1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.
$ E1 C* ^9 f- _( l' ~4 R! k, I& s2 k1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param
- n* S- q# R1 ` _, d! P9 \ }: T1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish5 e. G. V, G2 ]* ^ n. M5 q. C
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).
+ v i. ^; ~1 O/ [* q3 m1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke$ g) {3 @6 c2 P! R
1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.
7 X; l6 d" d7 J1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode5 u4 I$ D: Y, m% G9 B. }
1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs: |& V( G+ s) S+ X: \/ l! n2 T
1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.6
) g, O' i; h+ ~5 J1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.9 ?! n: c M! t, A. z9 m. }0 m
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON8 ]0 o& @' E) X+ H/ s
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6$ K. D% _9 p7 m' E; h( m5 N* J
1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset: I4 i7 p+ U+ Z1 G* P) ^
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters8 B6 i3 a* d' D3 `- d
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend
& [* i0 E, d) g# p/ R2 J1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP
- p: Q/ E6 N; v$ ]6 j! I D1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint
% \. b: Q' d5 e( `+ O, z/ R1112774 GRE CORE Allegro GRE not able to commit plan after topological plan1 W3 f5 b8 d1 N# {: J0 V# k
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.
" W! s% m8 K# ]0 q: e1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file7 I. c7 \+ [( v- {" G4 O3 v
1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6
1 a. }7 m' I" }1 d" x* z% l: L4 I
DATE: 03-7-2013 HOTFIX VERSION: 005
. b5 X7 r' i2 M& E( ~. V===================================================================================================================================
6 N4 \, X) r# {* u; uCCRID PRODUCT PRODUCTLEVEL2 TITLE
/ _' j+ l7 d) ?3 l; v8 g; v) v===================================================================================================================================2 x0 ?5 f& Z- E
1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 11026 `7 d. f8 l: w
1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed
) @- s5 O# V% P+ c! Z0 V; T& ^* `1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently
$ Y, R0 x$ A3 c' O/ {# W/ G( t1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind
! z( w0 R- `7 m1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view+ G; p9 a1 l d0 {2 s! \& O
1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed
( H1 p. J' E( {7 B1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM
1 l9 F- N. t5 Q1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6
6 Q# J/ x0 p7 M9 i1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.5 {' f u& d9 F0 W" ~
1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design
) k1 t) j/ O+ @1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional
9 t% m0 T; y, i! k: ]! L: w1 e7 k+ s6 S2 ], i
DATE: 02-22-2013 HOTFIX VERSION: 004
( I: h# ^- S: H: P& U===================================================================================================================================
( ~, ]- v% A; f1 c" `6 mCCRID PRODUCT PRODUCTLEVEL2 TITLE
! J P3 u% V+ U: V( O- ^===================================================================================================================================9 ?& @5 R) t D' @" a
1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly X( o6 v$ U" @+ l! o
1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing5 P; R9 e- S" V! c" @
1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM
7 P( {# }) d' d4 J- \6 I1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition, x$ m9 I! [3 r3 L$ {9 q4 K+ A
1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend
2 c- [$ N' j u# ^+ z0 M$ `& r1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report! l) W% ]/ h8 M) m, w! F9 D6 M
1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command8 y. C7 J" g- [2 @
1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit., i$ q7 N. i' \) ^
1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat
D, Z+ ]8 P3 g( @5 i' p1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated.
6 d1 @# n& X- h! [8 g+ l, _1 V% k6 ^7 q L5 u4 b
DATE: 02-8-2013 HOTFIX VERSION: 003
5 m' G% Z7 s+ ~; N===================================================================================================================================
; o7 j- e2 ^$ h4 ^9 g4 X4 bCCRID PRODUCT PRODUCTLEVEL2 TITLE" @! S0 g( \: r1 t: h
===================================================================================================================================; G3 b, G; D( n; p9 O0 D% I
1077728 APD EXTRACT Extracta.exe generate the incorrect result
& Q' k; }, d8 C9 a6 z8 G# u1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF
1 ]6 g* c" ]5 b4 T! t1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer
/ @0 C3 f1 ~* n- l1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing.
- V. X# |. N4 o. M8 }1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on
/ ?: e! P ^% _0 F, }6 O1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent8 q1 ` m9 T e: g6 N
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command
$ @+ I1 l2 {# T9 r" ~0 S1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor' i6 e$ i R% q0 P
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn縯 show up after 縎uppress unconnected pads� option.
* B f B. C9 B! g4 {1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff
! s% ]0 ~; O6 Q7 [8 t5 o, t1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible
c; C0 E! L) W8 v* d1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35 \6 H( E) d' t/ o# J3 R9 e
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component.
J- _+ C) i; A! V2 @5 `; g& t2 f1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.' l$ I# T" W9 P p. A3 j
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.
j( N, n5 f0 T& H# N9 u
/ w8 R# [8 \0 C/ s. `6 f1 i! f( RDATE: 1-25-2013 HOTFIX VERSION: 002
! }8 o6 ~1 @% u0 D e: z* p% Q. k===================================================================================================================================$ m9 v9 {) m+ p; u3 _* B& h
CCRID PRODUCT PRODUCTLEVEL2 TITLE8 Q1 C( U3 j9 |6 y+ Y
===================================================================================================================================; A8 x, {8 w7 Q- M9 D% M3 m
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute4 p# e' ?$ c1 t4 ^: `! Q
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
4 [: I/ M9 _( H1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes' B( Y! N# l, g! }& U8 m
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable9 \$ V' L2 w. k) \4 v [
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
' N z5 l. B- b, ~- n1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
) \6 q& ]/ J( j1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
# l, P3 w* A5 c: G1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
' O7 k% q- b& d H2 P( N3 L1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6- k( V5 Q+ o& G
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.0 L4 g' ]: o% a% v8 v; N8 K6 d1 a
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
8 U# r9 p" m B+ K1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
+ Q7 M) z; s. `' J8 ^- ^3 c& i1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0& l! n0 E; j2 b
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white
5 k) R5 B( g2 R2 g! I5 j% ?1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure: @4 M& h6 P6 n4 y! b: g4 A
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer. [8 x) x6 u- ^4 Q* c1 `
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.$ G: N' ]1 T y/ u7 t" Y
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.' O, U$ R4 f& P( i- `+ r
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.3 ^" J8 _1 C+ A& [: l' n
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6
8 d0 P& R2 x& N- _! c b1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
' _# @" a3 ?. l" _1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file) P9 X. V" i) C& J, H: ~- U
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing." X+ v. ?: Q1 u# a7 Z* N U
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
% z# `2 \+ m; t7 ?& v) f1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties- {$ U4 z9 K9 b7 P& I/ Y& \: G
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
' V* |* }+ a3 D" w$ [. w" x: _1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric( P% y; z) P. s. b; T( K" x
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
9 b# V8 z I: K x6 v+ u/ ^1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue4 N" H u5 W( \0 y& m F# J6 i0 n
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command3 j, ?. c* R$ P
1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
Y' R8 }& N" p3 [% x- ~* J1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
1 Z$ T, G( H) X$ T! r" g/ g {1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.$ {& N$ J4 y3 c$ B' f0 X
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function. y2 s& r2 o" Y6 }1 z( }) ~( L; g
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.9 U. U/ W2 h1 d! h
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?0 z7 M7 b; t5 P) E) v+ Y
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group: c+ q, }0 X/ K; x/ b2 N
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
4 n( ]. r1 w; H0 w1090689 ADW LRM LRM: Unable to select any Row regardless of Status
( g0 q( s0 g0 D1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle% {+ K! w, _2 R! c5 R
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas. `! C9 G8 c' T9 n5 o
1091218 ADW LRM LRM is not worked for the block design of included project' I0 ~2 F' m9 e+ e. m
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads- x: f. G4 |% y! L; ~1 S3 n, N* i6 R
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
5 _8 i6 A8 x9 {* L1092916 CAPTURE OTHER Capture crash
: i6 q% Q6 a' h! w8 ^2 C! Z1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database$ g3 H g, H4 W
5 A c5 V }0 ~
DATE: 12-18-2012 HOTFIX VERSION: 001! u# T( W& G2 [+ k3 \
===================================================================================================================================
2 M/ f* r7 m3 ~2 _% |# ECCRID PRODUCT PRODUCTLEVEL2 TITLE
- X5 n r& ^0 R===================================================================================================================================9 r9 h- D% |9 Z" U
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap) |- S* e7 w; J6 E+ D4 o6 M9 _
745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched5 g7 H. Y2 F: O& I
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted% l0 n- p7 k$ q7 O4 y) D: Y. f
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash8 `4 R( G; ?# ^0 G1 M
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments/ a) M$ F: A; a& T
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore y0 N7 n' Z7 r$ c* K
923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties1 x+ Q3 }/ x9 r0 C6 A1 o L
938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
0 p$ G; h2 Z- y3 b- \947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape.; Q3 A" R8 G. s7 a
968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
, Q: K: r, \9 z2 y976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
# k# q' i3 n9 y7 P4 U981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected.
/ D( x q7 e- F" C7 j982273 SCM OTHER Package radio button is grayed out
% }& n( b! Z# v3 u# J988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command5 j( x# j6 B! q. R
989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode, O% ^! Y) Y2 x
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34).
: Y9 b" b' P; f) Y996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections2 Y M( N' s9 e5 @7 o; y; n8 g
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used? |3 z8 f4 Q b+ w
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model
# ~: R9 a* z% ?0 y% w" [1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
. E6 {' r' E; ~+ H3 t1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg
$ W# j+ U2 v" H! y1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.3 q }0 c% V3 j( l. k; J$ d
1016859 SCM REPORTS dsreportgen exits with %errorlevel%
* D8 b3 ?" Y5 g6 J! Y' K; [1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin8 ~4 {; X8 l8 j& P4 X. S/ j
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs
m- g8 w( k. [$ c1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts: {) V, d/ i/ @ n% j# W/ F
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
9 P9 {) R3 ]& M, Q: D% F1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire.
* J/ n8 d+ S* t2 M1 v5 z1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button$ l) M, X% u: @
1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out, Y1 Q5 U& I: |/ [
1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist( ~8 l1 M A& c3 Y: _+ v. Z
1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed5 l6 j" Y0 `+ g7 ~% m7 \3 V5 O
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product/ G1 a* \9 ?9 E7 v: p+ F) j
1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
7 I e5 W/ k1 `; j9 {! c1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it.
/ D' a1 m4 B8 G! e4 L* b* _4 U8 f1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
8 V, v5 b' F, q+ u1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol
) f1 @$ u/ F; X1038285 SCM UI Restore the option to launch DE-HDL after schgen.9 o; b8 a, I5 t
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
( d4 h+ t! v5 t5 O* \# c2 w1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro% G. S6 w8 D& U/ [# L: ^) S
1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected
7 k+ w# c$ _$ q, Y6 i1 X0 j" v1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing
6 z9 G' {- \! m" ?9 A* `5 P0 a1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.
. S. W, U9 P: r- T6 W: |1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work.( q7 ] Q$ V- b9 y* K
1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu* W, T7 N" g% K6 y5 K
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab.7 z3 O/ m, X6 N1 Y3 o( m
1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow0 Q% o+ J8 y4 p5 Q. t( B6 y
1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory
# e* h8 M; `8 b: ~; j1 R1043903 GRE GLOBAL This design crashes during planning phases in GRE.
. ^# A! q# E, s1044029 PSPICE ENCRYPTION Encrypted lib not working for attached
0 R: v3 @, D: [! n- F, X1 N) ]& c1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory) ]) z6 m5 l. Z! y. c( M5 h
1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.
3 w, C6 X. z& m" Z, h. Y1044577 GRE CORE Plan > Topological either crashes or hangs GRE
0 G P2 \' k5 d1044687 TDA CORE tda does not get launched if java is not installed* U: S8 `+ a5 O) _% H; ?
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die
) s+ ]( [& ]9 w% K5 e8 @$ _2 L7 T1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.8 Y4 M) }* `8 Q: S, t$ b3 \/ T" t
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board?
1 X, g1 \' Z9 |1 U# z3 _* T1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51.& B) d% o7 Z* v& Y5 F0 _; ~8 Q& d* \
1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.0 u- x* ^8 _# A: O' D" q
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow
/ k* P5 i; P! I0 v; v* @! ?1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.
% r7 R/ z; k& @* G( u1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill
G) X$ ]8 _; \- ~, T$ J+ T1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond.
0 W/ f1 s, f/ m) w+ B3 c/ ^1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5
& S- K' @/ K4 G* q$ v% I7 T1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5 x8 s4 w) h0 ?" q2 r% K
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value7 s V+ \& h- Y
1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version* ^, X& v% p) C% W5 F5 ]8 d
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn縯.+ `. |$ I. T. c% L7 Q" }9 p
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC.
; D7 C9 B, ~! }0 l% \ O3 h1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.9 N2 s% Z9 n% L$ y1 K
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes
0 ?3 M, a& S9 [% Z" B8 m" `0 d1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.) t4 v7 ~) a; D5 m) k. I6 p. A
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
0 V8 L& l9 }2 C, f* K3 y1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file! X3 L2 ]5 x- z9 X! X
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors
4 f& T. C" o. F6 `+ F1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated.
9 u- f3 w; ]/ t1 I1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts.% I4 A" P# f8 N' b# C4 H
1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design
% ?6 O% C" E8 U1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs$ J4 t$ q& F) U- m! ^# k) U
1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label0 a/ x5 H: n; y! A \2 P
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction.& Y, _6 Z# \1 M/ P2 V
1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy
0 n4 ~4 I" f. b j0 O6 k) d1 K4 p" d3 d1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down3 }& I' u Q( g/ W' Y3 V
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection
$ j+ }9 x* j# A1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible.
. W9 F! ]1 J- B$ L! ^1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views
" X3 | L1 I x& z/ ~3 |+ O1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline' n# k+ p; {6 _ z" L& n
1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design.- S2 y* h6 s7 I; P
1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.$ E! A5 H5 X. N! f. x% a6 h
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move
5 s! c9 }2 L% ?/ U3 X( l- N; G( V1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value8 C P2 E* g: B
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer
; W7 J0 U+ k" x% `1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report
7 T2 m l8 m+ S l, V1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value.3 @% A3 i' a1 G F$ `
1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete4 Z- I- P; m! [6 J: @( T
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
0 X& z) K) a' P; [0 s1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets
4 b% r( z. M2 r |5 f; c( U9 K9 h1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?% t: C: h a. Z, d* q
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.2 g% Q" ?( p) Y# Q C' `
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.
5 ]' X" l: [# f) {1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00" ?, C* {- G" m* y) b) b# c/ w- j4 R% `
1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
9 E% S! J9 c7 M) F4 w: u. X1 Z* t1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.
: ]! H9 h/ Z( M8 R1063284 PCB_LIBRARIAN OTHER PDV Save As is broken
" p3 U0 v6 t+ }1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs1 j E% c: G; U' r V5 j% y
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.' U" q# }5 c' S: g' w
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.
+ q6 k7 Q' f) e9 i) S4 x1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design
# M, r! N6 c+ E$ {# e1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV6 Y) R, f* h- t
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green.
" s2 I. q! J n1 O1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X
6 I* W& B2 I% x% I, Y' ~1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application! m2 ?" p# M4 O1 _" g
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report
5 f8 K; L4 s7 x: l& y0 ~1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
; Q% H( m! _0 Z1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic$ u; |, C/ P$ ?" O* u9 D" T- S
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.: B6 W5 x- T/ O) I% }
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file5 M! V9 x; i2 V0 Z% b7 ?$ d" T% d
1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 縞hange properties� command# N" ]9 U3 D. r0 r0 Z# e. N- o
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended3 u7 h3 h9 o; _
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067
$ w% r6 b9 n1 \/ P! B% ^5 w1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design# |/ [6 R! T7 @+ T2 ~3 u; O& P" z
1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify
! t9 V- {$ ?9 f [( Q+ H; l; T1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids
' d" z+ X2 A8 i e6 q7 m1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes) i/ ]( x( K, x2 D+ Y8 M( x5 {* O) X
1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
6 S* {( F9 w( t6 u# U+ x% T$ P& v1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal
6 p+ Q- ^* a$ L( P, I( p+ W; r {" Q1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.
% i, c7 c( J" W; f) H1 H* P- W1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
/ \8 z q4 h9 p, A' b6 u% h, i/ x: c1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5 M7 q6 w/ L! V/ \- R1 _2 ?/ f" R5 H
1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode. B& L z# G! [, \ D0 J
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
5 Q( W6 i5 r5 v: j( g9 T# R: c; x6 f1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor6 q- |5 N. q8 K
1073464 SCM SCHGEN Schgen never completes.
" k- z5 }) j7 |: s4 t# K% x1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory- X$ T0 H2 @1 U* G
1073745 CONCEPT_HDL CORE Import design fails
; Z% j8 Q9 Y U5 K2 I1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin'
: ]2 W- C, K \: }( J* ?# x8 `1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE6 f$ g" a! H9 ] f3 ?( P0 o7 Y
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist
; C0 w7 f. N& V. E5 c3 k7 c1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter" r) K1 W5 E r7 P
1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal* U; ]+ F; h- r+ @/ t7 Z$ K/ _
1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.2 ?7 k! N2 B" \
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI
/ L1 k( {/ C% P1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block5 t; q: C) U, L" c
1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer$ G. x. P+ ~4 c1 v0 R! Y
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces
, K7 c( W, H" \2 }$ i1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2
4 E/ y- M- m) O3 d2 a' S1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix) j3 x: U, q1 \- b a7 x
1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
! Z) G& L; x9 U* x1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
1 }, y; l6 e4 \3 N1 P" B$ L+ x1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas.
3 g- U8 F1 |$ ?0 L9 ?' Y0 D1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value
' n6 |! ~' o; I R7 B% B1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6( A) W9 c, \8 k* r) ]
1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey0 a+ H' \+ O# m6 ^# s1 m5 B
1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database. S( P6 Z) W6 s% I; }, ]
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset
* W, ?. Y) M W$ Q: U& l1077169 APD SHAPE Shape > Check is producing bogus results.2 F! B4 I( @5 H7 K$ s1 g/ f- A
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board.
" _, y' w' A0 { a/ Y n# N% q1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim
. C' o- A, L' U% d; U1078380 SCM OTHER Custom template works in Windows but not Linux+ l8 o% b- f7 B4 q
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.! @# V5 R8 Z+ j8 \7 ?
1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide
1 J1 e1 `; Z8 q u% A- Q1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
7 v9 V# W- m; d1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"" b' |/ y$ s( G; c: V
1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text
$ x3 Y; f9 a/ K( L( E. \1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control
; P) J$ H$ E7 ^/ P( O1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.
0 [" K, a" d1 b- @, l7 N1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.
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发表于 2013-3-29 16:28
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