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ction 1: Getting Started
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This first section is meant to get a user up and running as quickly as possible. It touches ) L3 G# g E; I7 q- f6 r5 y4 A
on multiple topics that are detailed later, and is meant for application and a quick understanding. & g2 D1 a- U; f
That being said, I think all users should look through this section and make sure they understand
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/ a" n' A' Z$ V* A! u U The last portion of Getting Started covers analyzing results, which is an integral part of : L+ T% U7 V: t; r/ @, M% _& ^+ S
entering constraints. One can't enter core timing or I/O constraints without being able to read the 7 N/ o/ ?. F# L: h+ v( ^4 x
analysis reports, so it is recommended to read that section in conjunction with the information at
+ s0 O& r5 Z4 N3 c# Y5 ythe beginning. $ T1 e- S$ Y( L* t; X" ^
. m9 T8 C* P/ S. c4 S" D& CQuartus Setup ! h% r/ K+ B+ m; Z- W. j1 @
Within Quartus, there are a number of quick steps for setting up your design with
) f7 N5 R' {# x, vTimeQuest. These are accessed through the pull-down menu Assignments -> Settings: ( n& w" A) ^+ e: }
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7 k6 K) k* l' u9 I& B7 j: T1) Along the left panel, select Timing Analysis Settings and select the "Use TimeQuest…" radio
9 F+ k& ]7 y! n% R. Zbutton. The Classic Timing Analyzer is the old timing analysis engine, which is not
0 O% M# ^9 e: ?! l/ yrecommended for any new designs or architectures, and will eventually become obsolete. # G) `) ?1 |2 {$ x7 H
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2) Select TimeQuest Timing Analyzer in the left panel. The screenshot should look like below,
/ u: _) \( V4 q( g. I- V9 q, cwhereby the user can add a new SDC file. SDC stands for Synopsys Design Constraint, which is
/ n' G/ T1 h& O1 B; V: bthe format TimeQuest uses, along with many other tools. If no .sdc file exists, we will create it
0 J9 ~, x1 d6 [* z2 rin the next section. Note that SDC files are analyzed in the order listed, top to bottom. 5 U2 O! @! b1 I2 f
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