数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。

zhangsong123

通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
6 Y) o( ]+ k# S/ B' Voutput [7:0]led;
output [5:0]led_seg;
output SOS_En_Sig;
; U2 |9 y9 a1 E1 m& V" [0 dparameter seg_num0=8'hc0,
          seg_num1=8'hf9,
             seg_num2=8'ha4,
. y# X; y, }# ^4 o5 t9 ^7 y             seg_num3=8'hb0,
5 X/ y  N9 b7 r7 w             seg_num4=8'h99,
" p* I* }; K. q5 q             seg_num5=8'h92,
             seg_num6=8'h82,
             seg_num7=8'hf8,
( p- l5 R. [& b$ X& x& M2 n             seg_num8=8'h80,
0 {7 `4 |- c. d1 h6 t2 k/ T4 C             seg_num9=8'h90;
& F: D! A( L* v0 n; iparameter seg_en0=6'b111110,
          seg_en1=6'b111101,
             seg_en2=6'b111011,
* j3 Y- i/ F/ f3 A             seg_en3=6'b110111,
  }" i: v% _  a             seg_en4=6'b101111,
4 A. I* Q: i$ @7 g& ]             seg_en5=6'b011111;
reg [26:0]count;
6 J5 k, n0 A+ B4 S( ?reg [3:0] count1;
+ V, m1 e2 H3 R& q. B  \reg [3:0] count2;
reg [7:0] led_reg;
  l" Y7 F. i: c; Z1 hreg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n) count<=27'd0;
else if(count==27'd49_999_999) count<=27'd0;
else count<=count+1'b1;
wire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
0 X1 O# K5 Y, [% W/ F" f5 Zif(!rst_n)
begin
count1<=4'd0;
3 I) Q! L, t5 x+ v7 fcount2<=4'd4;
end
else if((count1==4'd0)&&(count2==4'd0))
0 |, ]8 \4 U. ^% E% nbegin
' t. F# x5 S% H& N3 A, }2 ?2 ]count1<=4'd0;
4 B" G' K) A4 scount2<=4'd4;
end
else if(count1==4'd0)
% ~1 w4 i, G" L2 @  @8 m5 Ybegin
count2<= count2-1'b1;
count1<=4'd9;
  z; @4 X, C$ c, tend
+ U  c" X" {. G. ?! Selse count1<=count1-1'b1;
reg [26:0]count_1ms;//
% r+ S8 z. i% V" qalways@(posedge clk or negedge rst_n)
( J. e5 Q3 \+ k+ T( m' Kif(!rst_n) count_1ms<=27'd0;  
: A3 }0 @1 U% K; }else if(count_1ms==27'd49_999) count_1ms<=27'd0;
; f- v4 `% P$ G0 d0 p8 p3 p: x' Uelse count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
//
! D5 H( l1 T# I& [8 a0 j" p% ]reg [1:0]state;
always@(posedge clk_dis or negedge rst_n)
if(!rst_n)
begin
. p1 a$ r' h1 f! X5 u# nled_reg<=8'hff;
led_seg_reg<=6'b111111;
state<=2'b00;
0 f& L& v1 {8 A8 u/ F. d' Qend
9 I) |. X/ ?: S$ r$ [) a, uelse if(state==2'b00)
8 X% K. a  {7 t6 m+ ]( Bbegin
state<=2'b01;
# K( d& j* r, c, j3 }led_seg_reg<=6'b111101;
case(count2)
4'd0: led_reg<=seg_num0;  
4'd1: led_reg<=seg_num1;  
/ A8 P8 e" l3 K2 j+ _7 \1 r2 v) @( N; ?4'd2:led_reg<=seg_num2;
4'd3: led_reg<=seg_num3;  
! e  K  E9 I9 r. q% Z* l: L4'd4: led_reg<=seg_num4;  
4'd5: led_reg<=seg_num5;  
4'd6: led_reg<=seg_num6;  
4'd7: led_reg<=seg_num7;  
4'd8: led_reg<=seg_num8;   
4'd9: led_reg<=seg_num9;  
: n! {+ S8 a5 y! r1 F; ~default: led_reg<=seg_num0;  
endcase
" ]# ^/ H( W9 d: dend
else if(state==2'b01)
begin
2 p/ \: r% I/ Q: i, |state<=2'b00;
4 ^+ ?# s; {5 nled_seg_reg<=6'b111110;
case(count1)
# N) _2 p6 z. d4'd0:led_reg<=seg_num0;
6 ]* A- N4 O- w  D/ u5 d: I4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
4'd5:led_reg<=seg_num5;
" R, C9 Y% @: W4'd6:led_reg<=seg_num6;
1 P! p- t; s& H5 N' f( t4'd7:led_reg<=seg_num7;
4'd8:led_reg<=seg_num8;
7 b( l4 Z+ c- X4'd9:led_reg<=seg_num9;
4 U2 L" o/ O; N" F& v& ddefault:led_reg<=seg_num0;
endcase
end
reg isEn;
always@(posedge clk or negedge rst_n)
" z/ p+ o# ~1 v5 `' Fif(!rst_n)
begin
2 s) v3 m5 m! h" E9 Y: FisEn<=1'b0;
7 ^1 ], h6 Q6 c) mend
3 r& Q3 N1 Y+ N" R) r% ^else
begin
0 q( t. `) g7 o0 J; D2 E0 X! RisEn<=1'b1;
5 g# U( H1 `) w: L5 ~end
assign led=led_reg;
: u; P3 O/ b* |1 F8 Wassign led_seg=led_seg_reg;
9 L9 ~- M: n5 Q; H" |' O  _/ sassign SOS_En_Sig=isEn;
endmodule
5 Y9 @& |+ n6 ]4 T# y0 Q