数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。

zhangsong123

通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
output [7:0]led;
output [5:0]led_seg;
output SOS_En_Sig;
$ |8 \5 i; B* s4 F- v( F4 Z! Wparameter seg_num0=8'hc0,
          seg_num1=8'hf9,
             seg_num2=8'ha4,
1 F$ t1 \/ x1 v5 h             seg_num3=8'hb0,
             seg_num4=8'h99,
             seg_num5=8'h92,
. E9 d8 b" {3 }+ x/ r+ [             seg_num6=8'h82,
             seg_num7=8'hf8,
             seg_num8=8'h80,
1 }% ?5 [5 \: Y; A: o             seg_num9=8'h90;
# w7 q+ x3 {( uparameter seg_en0=6'b111110,
          seg_en1=6'b111101,
7 U0 U1 @8 P9 B' G" }             seg_en2=6'b111011,
             seg_en3=6'b110111,
; l' |5 d" u5 b& \             seg_en4=6'b101111,
             seg_en5=6'b011111;
' L3 j. G1 I) L5 Y  n  X! t5 ]reg [26:0]count;
6 ?, ]2 Y' \, v: N, [7 E2 k& J0 Dreg [3:0] count1;
* B" S* v7 n. g2 I( Xreg [3:0] count2;
  l" u1 k- i* ]5 Z" f% ^reg [7:0] led_reg;
, k% P0 C2 n* Z1 |7 m# \reg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
/ j3 j; o4 e0 y- ?if(!rst_n) count<=27'd0;
else if(count==27'd49_999_999) count<=27'd0;
, [9 W/ G- p* g; `; O# x6 telse count<=count+1'b1;
$ C( e; T+ @8 S7 Cwire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
if(!rst_n)
begin
count1<=4'd0;
count2<=4'd4;
end
( k7 Q/ L8 i/ H' ~4 b# {else if((count1==4'd0)&&(count2==4'd0))
' h% C* `( W# p6 P9 gbegin
count1<=4'd0;
count2<=4'd4;
$ Q, R) b; E& z8 {% ~end
else if(count1==4'd0)
* c* r  V# K5 X/ pbegin
count2<= count2-1'b1;
0 K* P4 {% y5 L2 l; rcount1<=4'd9;
/ n% b- }: z( k0 Dend
; Q3 W! h* w, U7 Zelse count1<=count1-1'b1;
- A" I3 X. O7 Y1 a  \1 Breg [26:0]count_1ms;//
: n7 h: R2 a5 A* I8 oalways@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;  
, |8 ~3 W- u' h$ H) Zelse if(count_1ms==27'd49_999) count_1ms<=27'd0;
  |8 T7 l: d$ selse count_1ms<=count_1ms+1'b1;
& n" c# N6 z9 Q, F6 E0 ~! {wire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
always@(posedge clk_dis or negedge rst_n)
/ s  j+ P( [, x* a& I! a( j5 cif(!rst_n)
' v' T1 Z7 E! d8 }, [% W  p2 s  gbegin
led_reg<=8'hff;
; Y4 r; s) Q7 e, N, @4 oled_seg_reg<=6'b111111;
; F" u, j" e' k' estate<=2'b00;
( h+ q" l6 i, I$ Y3 _end
else if(state==2'b00)
5 B2 f" K- i! R- A4 f5 e3 vbegin
: `- g) V4 d, L) {8 w6 ]# N. t0 [state<=2'b01;
led_seg_reg<=6'b111101;
case(count2)
4'd0: led_reg<=seg_num0;  
4'd1: led_reg<=seg_num1;  
4'd2:led_reg<=seg_num2;
: A6 u. p+ f3 u* r" y  N4'd3: led_reg<=seg_num3;  
4'd4: led_reg<=seg_num4;  
; F1 j9 Z* Y) I! d+ Y$ C4'd5: led_reg<=seg_num5;  
4'd6: led_reg<=seg_num6;  
4'd7: led_reg<=seg_num7;  
4'd8: led_reg<=seg_num8;   
; D0 F3 R, j% }9 g) A/ x+ z3 n4'd9: led_reg<=seg_num9;  
7 a$ x; w4 [7 `! {) [4 O3 H1 Adefault: led_reg<=seg_num0;  
9 @0 F9 a' d% Q- c# k" Eendcase
3 ^0 M! b9 u" Uend
else if(state==2'b01)
begin
state<=2'b00;
/ U* t9 g) h) K9 Z, E4 Mled_seg_reg<=6'b111110;
case(count1)
3 c5 n8 h  [# T  k6 X8 q4'd0:led_reg<=seg_num0;
6 |8 U6 J) `6 y4'd1:led_reg<=seg_num1;
4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
9 {' d2 F1 h  w4'd4:led_reg<=seg_num4;
4'd5:led_reg<=seg_num5;
. w' N% F3 M" P1 B0 R" N4'd6:led_reg<=seg_num6;
8 x1 }3 y+ e) Q8 G) x4'd7:led_reg<=seg_num7;
4'd8:led_reg<=seg_num8;
4'd9:led_reg<=seg_num9;
+ G8 y- i  J9 J$ d* p! v8 l* H5 ndefault:led_reg<=seg_num0;
& Y$ z9 {0 X" j& P3 Y5 Lendcase
end
reg isEn;
% T/ d2 A/ L& m2 M* E0 b# i6 Lalways@(posedge clk or negedge rst_n)
4 W3 G+ f1 C7 v6 Sif(!rst_n)
begin
! p# `& V9 S( }$ [, g4 GisEn<=1'b0;
end
else
begin
0 d6 X( h6 K) V2 C; WisEn<=1'b1;
end
assign led=led_reg;
assign led_seg=led_seg_reg;
assign SOS_En_Sig=isEn;
endmodule

. W2 S; d( Z' ?$ [+ A' v2 T, g