各位大神，请进来看看，急急急~~~

zhangsong123

              各位大神此设计有什么毛病吗，能麻烦你们帮我指出来吗？
4 X- i8 K7 ~9 R/ P  设计要求，40秒倒计时，9秒之后3秒一次的SOS警示，我调试之后蜂鸣器不响，怎么回事，跪求大神指教！！！！
) m' v# x. X8 A8 W" umodule led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
input clk,rst_n;
output [7:0]led;
output [5:0]led_seg;
output SOS_En_Sig;
% R0 s( N; {: l( A+ bparameter seg_num0=8'hc0,
          seg_num1=8'hf9,
% ]! L- e$ `4 W, ?4 M7 k# _    seg_num2=8'ha4,
    seg_num3=8'hb0,
    seg_num4=8'h99,
    seg_num5=8'h92,
% }$ h9 I1 I# J/ w0 d    seg_num6=8'h82,
( G- O; e( T; ]' p/ a, t: F    seg_num7=8'hf8,
1 ^# w0 z: m. V6 J9 l& ~    seg_num8=8'h80,
    seg_num9=8'h90;
parameter seg_en0=6'b111110,
          seg_en1=6'b111101,
4 D9 S. L4 G1 Q    seg_en2=6'b111011,
, m+ e" y! h3 @    seg_en3=6'b110111,
( C; P: y9 d0 [7 G    seg_en4=6'b101111,
    seg_en5=6'b011111;
reg [26:0]count;
reg [3:0] count1;
  R- G$ _. i7 Jreg [3:0] count2;
reg [7:0] led_reg;
  W( u1 X4 F# U6 {reg [5:0] led_seg_reg;
always@(posedge clk or negedge rst_n)
if(!rst_n) count<=27'd0;
else if(count==27'd49_999_999) count<=27'd0;
else count<=count+1'b1;
1 p  [$ m  q, `. |, ]wire clk_div=(count==27'd49_999_999);
always@(posedge clk_div or negedge rst_n)
" l8 r, ^* L2 V( l5 K& h* Tif(!rst_n)
* Z& `& m( I3 j* D& U1 cbegin
, `% M( j! g4 m9 |9 G# T. ecount1<=4'd0;
count2<=4'd4;
end
else if((count1==4'd0)&&(count2==4'd0))
! \' d; l+ f1 ?* t+ j' Sbegin
count1<=4'd0;
. @; ?! k1 X; ~& h% z  U: vcount2<=4'd4;
% a" K- B, B8 o- B4 lend
else if(count1==4'd0)
begin
! A  L, d& o, G3 Icount2<= count2-1'b1;
count1<=4'd9;
  g' |) E6 \5 B" o' d. W/ n& r8 g$ ?- cend
2 X, p9 s! Z, [else count1<=count1-1'b1;
- Z! h, T8 u" l: k4 f' mreg [26:0]count_1ms;//
5 n( |: I7 l( ?$ |0 j3 Ealways@(posedge clk or negedge rst_n)
if(!rst_n) count_1ms<=27'd0;  
else if(count_1ms==27'd49_999) count_1ms<=27'd0;
else count_1ms<=count_1ms+1'b1;
wire clk_dis=(count_1ms==27'd49_999);//
//
reg [1:0]state;
always@(posedge clk_dis or negedge rst_n)
$ R7 C) k& U  zif(!rst_n)
, T, v# V# q! b& Kbegin
. e3 Q) @$ `( R7 c% \* q! D: Uled_reg<=8'hff;
led_seg_reg<=6'b111111;
2 A. {$ s) e) H: m) j: cstate<=2'b00;
end
else if(state==2'b00)
/ ?2 N' ~1 C  ?& t! H0 Kbegin
$ [; y+ j1 b4 {5 R) v1 t$ gstate<=2'b01;
7 X! M) f7 k' b5 rled_seg_reg<=6'b111101;
, K- E2 B: v) d8 G* j; Lcase(count2)
/ c9 U) g- w. N4'd0: led_reg<=seg_num0;  
% P% F! j" _  Y' t, B7 b2 x4'd1: led_reg<=seg_num1;  
4'd2:led_reg<=seg_num2;
4'd3: led_reg<=seg_num3;  
4'd4: led_reg<=seg_num4;  
4'd5: led_reg<=seg_num5;  
4'd6: led_reg<=seg_num6;  
4'd7: led_reg<=seg_num7;  
4'd8: led_reg<=seg_num8;   
4'd9: led_reg<=seg_num9;  
default: led_reg<=seg_num0;  
& V3 L) l% a: P% a) D7 Mendcase
end
else if(state==2'b01)
begin
state<=2'b00;
# @( ?+ t  c. G' Eled_seg_reg<=6'b111110;
case(count1)
/ O4 |- ^2 ~8 c  [4 G* y% @4'd0:led_reg<=seg_num0;
% Z( Z; x0 }( U/ e0 x& R+ y4'd1:led_reg<=seg_num1;
! z3 w9 O6 k" y, g4'd2:led_reg<=seg_num2;
4'd3:led_reg<=seg_num3;
4'd4:led_reg<=seg_num4;
4 K: }3 n6 [: C. q( `4'd5:led_reg<=seg_num5;
4'd6:led_reg<=seg_num6;
4'd7:led_reg<=seg_num7;
4'd8:led_reg<=seg_num8;
6 j) o1 S0 q7 W: u4'd9:led_reg<=seg_num9;
: R1 K, U  R4 sdefault:led_reg<=seg_num0;
2 w4 V, `; Z6 U, P7 m, Oendcase
end
1 B3 ]) R5 S' areg isEn;
8 `7 u$ Z& ~/ G3 z  G* T- rreg [27:0]count3;
1 M. T" L9 K* V0 T' T- l% ~always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
& G: ?  ]$ c- \7 D( h1 misEn<=1'b0;
count3<=28'd0;
end
8 g7 w! T( m9 _2 G6 ~else if((count2)&&(count3==28'd149_999_999))
begin
isEn<=1'b1;
2 w1 P8 ^5 I3 }% c$ Z! R* N: R2 u3 kcount3<=1'b0;
% Y8 Z+ c& ]3 g1 Oend
else
' e" k3 l& Z2 @" kbegin
3 U7 F4 @7 S& I+ }8 |; L* uisEn<=1'b0;
count3<=count3+1'b1;
end
3 X1 v) s  w: w8 aassign led=led_reg;
assign led_seg=led_seg_reg;
/ r6 z7 t  R3 g# bassign SOS_En_Sig=isEn;
endmodule