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本帖最后由 紫菁 于 2017-9-14 11:21 编辑
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$ V9 V+ k0 ]; V! ?" }0 B1 {) a下面链接是Cadence SPB16.3及最新Hotfix下载地址,需要的可以下载!
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Hotfix057更新的内容如下所示:
: A2 v3 Y2 }( }" n5 N+ r0 H2 hDATE: 12-19-2012 HOTFIX VERSION: 0575 h8 D+ X5 l$ p- R
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$ ~; ?+ W# A4 x+ [, m7 iCCRID PRODUCT PRODUCTLEVEL2 TITLE7 D E1 r H( `
===================================================================================================================================
9 y; a. P+ T* a; g1080193 SIG_INTEGRITY ASSIGN_TOPOLOGY View Topology freeze during the extraction of the net connected to resistor network.2 X. G- x ]' g; I \ q' j
1082509 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S056 roatate some pins.( L2 c' i# `# S+ R& b; J Z5 b
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DATE: 12-7-2012 HOTFIX VERSION: 056
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CCRID PRODUCT PRODUCTLEVEL2 TITLE; b5 Y; P1 V( o# o1 i, {
===================================================================================================================================& r/ n0 Q( D: {
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other5 d, ?" i: I. L. Y1 `3 x- E
871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash4 D+ u# q1 r" z& a& ^$ ~9 r+ B- h
871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide
' _8 n5 m, U. n7 e# s# E1 j873917 CONCEPT_HDL CORE Markers dialog is not refreshed
4 \7 {/ p5 S! ^8 P2 ?! D+ K887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License8 Q3 c# E7 L" G# Q. e3 e
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator
0 {( Z6 B& Z5 r; a) F& b2 T1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic
3 y$ ^; F( _0 W: b0 f- j6 o: r+ ^1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide |
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