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DATE: 04-25-2014 HOTFIX VERSION: 027 ( H9 ?9 ~9 q4 m* b===================================================================================================================================+ f {& a6 K w A8 }. X
CCRID PRODUCT PRODUCTLEVEL2 TITLE 6 P* q8 ?5 d7 Z5 Q# h' ^=================================================================================================================================== 8 U X) ?. e3 b+ i308701 CONSTRAINT_MGR OTHER Needs to delete user defined schedule in CM p x2 L" a3 T481674 ALLEGRO_EDITOR PADS_IN No board file saved from PADS_in 9 H D Y6 g+ m* e/ w* @982929 ALLEGRO_EDITOR EDIT_ETCH can't route on NC pin and other that are not pin. ( o) v* m! L, r! }* h: A1012783 FSP OTHER Need Undo Command in FSP/ i2 c8 u( G$ q, Q7 e# A/ ^, {
1017381 ALLEGRO_EDITOR DRC_CONSTR Need Dynamic Phase to be able to measure back to the Drive Pins. + i1 }: h( f( Q( l1072673 PCB_LIBRARIAN GRAPHICAL_EDITOR Copy paste goes offgrid if mouse is moved ( X' `* y9 b: W3 B/ _# l/ q1073231 CONCEPT_HDL CORE Copy-paste of signal names goes off-grid in Windows mode.$ d" ?- j8 o% K% U% O
1105371 CONCEPT_HDL INTERFACE_DESIGN Strange behavior when shorting two Net groups. y( ^: x& `2 U" h
1116498 CIS LINK_DATABASE_PA link database with modified part results in Capture crash 0 F6 Y+ [. y( t1118632 ALLEGRO_EDITOR GRAPHICS Text display refresh issue while in Edit > text command9 t i, N3 ]* S" D) X
1155821 SIG_INTEGRITY LIBRARY Xnet are not recalculated correctly when model is changed on the Series switch part defined as discrete with Espice mode ! u/ r6 A; B' ]7 ?1157372 ALLEGRO_EDITOR DRC_CONSTR Dynamic phase for Diff Pairs not reporting back to Driver pin if pin escapes present+ A; I! T9 y# E' c1 Z
1171951 ALLEGRO_EDITOR CREATE_SYM Jumper has a limited of count when it add to list. 5 _/ L2 H3 ^- p$ E$ \7 ~1180871 CAPTURE LIBRARY_EDITOR Copied parts don't retain pin name and pin number settings& m/ i' e0 F, x* m# b* t) H
1185575 SIP_LAYOUT DIE_STACK_EDITOR Updating symbols causes the graphics for the Assy layer to change from Bottom to Top.* N8 q' i) l( m& ]6 E
1185772 PCB_LIBRARIAN CORE VALID_PACK_TYPE warning when cell was opened in PDV$ A0 m6 g6 Y6 c- y0 B! L
1192377 CAPTURE SCHEMATIC_EDITOR Pin name/number position is incorrect on schematic if it is changed for a rotated part.' L% k. M# v) u+ ~9 ~2 z
1202654 ALLEGRO_EDITOR GRAPHICS Zoom using mouse wheel shall maintain the center co-ordinates & m2 S# i3 q) \3 N1208031 ALLEGRO_EDITOR INTERACTIV Snap to Pin for via during Copy command do not snap to connect point everytime - N T3 m8 P2 G1 ]1208478 PSPICE PROBE Attached project gives overflow error with marching ON.7 p/ Z8 ]# D. m( V( u$ p7 l
1210015 CONCEPT_HDL CORE The value of $PN should be not turned on spin or rotate symbol . u, f4 ]! q" {1210425 CONCEPT_HDL CORE When moving a circuit tool reports that connectivity has changed 1 r+ b& ]7 c q5 b1215858 ALLEGRO_EDITOR SHAPE Force update does not void cline with the shape 5 T$ W* l5 Q7 O! U$ Z# r$ _1215906 ALLEGRO_EDITOR SHAPE Dynamic shape fill smooth failed when copying to other layers+ M" z$ K' _# q1 F& E: @
1216358 CONCEPT_HDL CORE Can we improve our export BOM function to check if user did export physical function before exporting BOM? 5 }3 U' S* J$ |6 X9 j0 o1217364 CONCEPT_HDL OTHER Netlist reports fail because error: GScald failed." N3 K8 u: e: F% k; Z6 }
1217529 CONCEPT_HDL CORE ADW checks do not catch single quotes in PTF values8 S1 U$ W, J) q6 |2 K! e' D
1217556 F2B PACKAGERXL signal name change not sent to Allegro after packaging1 G, }) {$ Z) j7 I- Y
1219283 ALLEGRO_EDITOR DRC_CONSTR Show constraint is inconsistent when displaying region information . g" U1 X: x8 f3 p# j5 U& X/ e1220078 F2B PACKAGERXL Export Physical crashes when ALL the part pins are added7 F# L- ~0 [0 H( N: n+ T" x
1220393 CONSTRAINT_MGR CONCEPT_HDL HDL import physical from board file will annotate CM data back to HDL which includes cross-section thickness.4 \1 t2 j' t5 N& m9 R2 F" G8 c
1220540 ALLEGRO_EDITOR GRAPHICS Need an option to see the pads inside the internal plane shapes8 T% s+ {, s* Q
1220936 CONCEPT_HDL CORE About crash by vpadd/vpdelete command on Linux9 y2 i! f. K- E4 B4 h
1221059 ALLEGRO_EDITOR DRC_CONSTR Get a "Shape to Thru Via Spacing" DRC error only the first time when the shape is manually voided. : P: N0 P& m5 Q. Y1 K* a1221182 ADW TDA Team Design with SAMBA# o& p5 [# `+ h- f% e
1222442 CONSTRAINT_MGR UI_FORMS Duplicate pin pairs appear in DiffPair6 Q% n0 s/ i, j; S
1223175 CONCEPT_HDL CONSTRAINT_MGR Schematic crashes when opened3 G4 s- R! x5 y2 t" W q" X+ y! b
1223533 ALLEGRO_EDITOR GRAPHICS Why the through pins for STEP models are shown at an offset when viewed in 3D inside Package Symbol? % a4 @+ W8 B: R1223680 CONSTRAINT_MGR ECS_APPLY Improve ECSet mapping by allowing user to address ambiguity of Parts 4 ]; n1 H! o& i% l1224156 SIG_INTEGRITY SIGWAVE Exporting spreadsheet with filter Subitems in SigWave exports all waveforms2 s( ~2 I* m+ b% @0 X U8 h" _
1224417 ALLEGRO_EDITOR PLOTTING Hidden font pattern is not showing correct in 16.5 version also 16.6 version. 8 L: P1 S& X7 Q! W8 e6 B, ?, T/ B) F6 i1 \1224704 F2B DESIGNVARI There is no lock for the variant.dat file - multiple users can open the editor # q! {4 T4 f& a. O+ |8 b1224968 ALLEGRO_EDITOR INTERACTIV Delete >(RMB click) Cut> Snap Pick to>off grid loction does not work for lines. ^0 S1 ]& `0 c
1224982 CONCEPT_HDL PDF commandline publishpdf does not work when there are spaces in the path" E' j/ J! X8 ]7 U9 `& l. y
1225114 CAPTURE GENERAL H-pins added after netgroup pin get color as of netgroup pin1 N' B. ~3 C1 T$ O
1225494 CAPTURE DRC Different DRC results for Entire design and selection$ m# j' l5 K0 L3 B4 k% J9 H3 |, _0 J
1226153 ALLEGRO_EDITOR INTERFACES Export STEP should include PART_NUMBER property $ {: Z1 N' T0 K9 |+ @* L1226235 ALLEGRO_EDITOR EDIT_ETCH Enhancement to include Pin_delay of descrete forming Xnet , ^1 i: T9 Z9 V& L( h+ s# \1226372 CAPTURE GENERATE_PART ENH: Functionality to add pin spacing in New Part From Spreadsheet 8 x3 i. t7 N+ I1226477 CONCEPT_HDL CORE DE HDL縮 `Allowed Global Shorts? function is inconvenient for Global Signal2 | E: T3 W8 r- m
1226813 SIP_LAYOUT LEFDEF_IF ERROR SPMHLD-120 when importing a DEF file. Request to increase the number of characters/line in a .cml file 3 e+ [3 a& O$ e3 j1227453 ALLEGRO_EDITOR SHAPE Addition of Fillet generate Pin to Shape Spacing DRC errors and DBDOCTOR errors . m7 F, A+ l& B$ f; [1227461 ALLEGRO_EDITOR SHAPE Sliding a cline for certain net changes the thermal relief connects for pins connected to another net from 4 to 5,6,7,8- Y# u J6 f/ L
1227469 CIS DBC_CFG_WIZARD Oracle Views not visible on Step2 of CIS Configuration; q7 m& q6 T; g. w$ v
1227780 CAPTURE ANNOTATE Inconsistent behaviour when annotating heterogeneous part3 W8 f7 W$ `" z j V! X. o; g: c# @
1227831 CONCEPT_HDL CORE Pin text and H-block name in upper case & j7 Q; s& u8 ]* o, l0 i/ S1227954 CONCEPT_HDL OTHER supress check for global signals when wires are unconnected to pins/ ?7 r* b9 S b, R/ M6 K
1228190 ALLEGRO_EDITOR OTHER Unable to close the 'usage' window during license selection: F# N4 h1 B; y
1228899 CONSTRAINT_MGR INTERACTIV Export/Import constraints in "overwrite" mode from same design shows different results when imported second time. 6 \: p# |2 c ]1228934 ALLEGRO_EDITOR EDIT_ETCH The "View Active Layer" option like the Board Station should be provided for dynamic layer visibility. , k& t! M6 T4 ~! S% `* S9 k* [1229316 ALLEGRO_EDITOR EDIT_ETCH When routing with Hug only enabled we were able to route through other routes(sometimes Hug).$ D2 C. O; `- E$ G2 d$ q7 j0 p
1229545 CONSTRAINT_MGR OTHER Allegro indicate bundle scheduled nets in CM% ^. _! N2 E4 a' E" I+ }0 _* q
1230056 ALLEGRO_EDITOR GRAPHICS Bug: 3D View of Mechanical Symbol with the drill hole defined/ ~5 v d! q2 a7 y- X
1230432 CONCEPT_HDL CORE No Description information in BOM % k# a- t" a, }2 J) [1231148 F2B DESIGNVARI The variant.dat file is not updated with library PTF changes & O4 @. V, O! x# `/ H# ?1231625 F2B DESIGNSYNC VDD at command line needs to support sch2sch and test variable to write out report files + q( a. E6 b2 J1 L. L' ~1231697 CONCEPT_HDL CORE If any locked files exist force a pop-up dialog restricting certain commands 8 M5 E. b1 p; L7 e1231767 CONCEPT_HDL OTHER Unable to find under the search options single bit vector nets 7 {% u1 G0 {6 O) S1231961 ALLEGRO_EDITOR SHAPE Shapes not updating to smooth unless we use force update and as a result false DRC's appear in board. / H# w, B1 p( v! ^7 R& K' E1232100 CONCEPT_HDL SKILL Unable to execute the SKILL commands in viewer mode j' c" o& e% C! `& j1232336 CONSTRAINT_MGR CONCEPT_HDL cmFeedback takes 5hrs to complete during Import Physical 6 [* Z) i0 ~0 d1232710 F2B DESIGNVARI Dehdl crash while moving component in variant viewer mode . Y7 l% _2 f2 L' z1233894 F2B PACKAGERXL The page data is missing in the pst* and PCB files 0 R- o5 ~5 a, P( W; K: v3 z! X! B1235785 CONCEPT_HDL CREFER cref_from_list custom text is not subsitituted in complex hierarchy+ }: }$ p9 h: g- y6 x
1235928 CAPTURE SCHEMATIC_EDITOR OleObject modifications not saved7 ?1 {+ R1 y2 c
1236065 CAPTURE PART_EDITOR Mirrored part after being edited get pin name locations incorrect6 M( j3 c5 F7 T: v2 j5 T
1236071 ALLEGRO_EDITOR SHAPE Airgap for Octagonal Pads ignores DRC Value when Thermal set 9 |( D c/ D5 K w1236072 CONCEPT_HDL CORE Page 122 cannot be saved as logical page 119 has different page mapping in connectivity data and schematic : v+ B% |0 x; P0 {( X1236161 CONCEPT_HDL CORE Import Design shows the current project pages& m7 M& d# l+ k3 @( q5 x& m( W+ ^
1236432 ALLEGRO_EDITOR PADS_IN pads_in doesnot translate via and shape in some instances." Y! \! ?& F9 l
1236557 CONCEPT_HDL PDF Running Publish PDF on command line in linux doesn't output progress until completion' ?! `! o) X: W. R2 }
1236589 CONCEPT_HDL PDF Enhancement license failure error should appear in pdfpuplisher log file! Q) q* d, z5 c( H8 v
1236644 ALLEGRO_EDITOR EDIT_ETCH create fanout deletes shape$ A, _- a }2 {8 S; Z5 Z, A; W+ G
1236689 ALLEGRO_EDITOR GRAPHICS Graphics displays extraneous lines when panning or zooming" Z4 ]( d+ B i a, ~( p
1236781 F2B PACKAGERXL Export Physical produces empty files2 `- @! C; E4 S |* ~" m/ ~( F6 H
1237331 PSPICE ENVIRONMENT pspice.exe <cir file name> - hangs when run 0 s: ?" J. D {+ p) ]* b1237400 CIS EXPLORER Capture hangs on 2 consecutive runs of `refresh symbol from lib? command9 C$ ?0 n4 P* M; d" c
1237437 CONCEPT_HDL CONSTRAINT_MGR CM Crash when saving after restore from definition1 q2 k7 a* _# \( \% m; Y
1237862 CONSTRAINT_MGR OTHER A way to remove the RAVEL markers from the Constraint Manager. ' \4 q# Z. Q, f# K+ m1238852 CAPTURE GENERAL signal list not updated for buses! r- A2 A$ |3 N' j
1238856 FSP DE-HDL_SCHEMATIC FSP schematic generation crashes0 x& n7 f u2 Y9 ?) ]4 D
1239079 ALLEGRO_EDITOR INTERACTIV The 16.6 Padstack > Replace function leaves old padstack.. Q% K* v0 J$ _+ w& z/ Q9 w* Y1 U
1239706 CONSTRAINT_MGR ANALYSIS The reflection result on a differential signal in the CM when Measurement location is DIE: u& } L# @4 ?2 u, b! `
1239763 PSPICE PROBE Cannot modify text label if right y axis is active( l$ s$ D+ U5 T% s
1240276 ALLEGRO_EDITOR GRAPHICS Printing to PDF from SigXp is giving unreadable images * \+ }& J. v4 `$ z! g4 F" A" j1240356 CAPTURE IMPORT/EXPORT Can縯 import SDT schematic to Capture. 1 U8 a% J- L8 I$ T1240502 F2B PACKAGERXL Corrupt cfg_package does not stop PackagerXL from completing 3 R3 ^/ H7 i4 _8 K7 s1 X3 D1240607 ALLEGRO_EDITOR OTHER Footprint of screw hole got shift in DXF file " m0 i) D" x+ g: f1240670 ALLEGRO_EDITOR PLACEMENT Select multiple parts and Rotate makes them immovable # o+ d, u2 x! E, f3 m- ~7 x1240773 CAPTURE DRC DRC check reports error for duplicate NetGroup Reference in complex hierarchy* Q: n. f7 ?( |
1240845 SIG_EXPLORER EXTRACTTOP Narrowband via models for Mirrored BB Vias not extracted in in the interconn.iml and this gives bad ringing in waveforms7 r& J M1 x) G$ o9 u) m
1241634 ALLEGRO_EDITOR OTHER Netshort for pad-pad connect not working/ s z* d; K8 E4 P. t& q+ z
1241776 CONCEPT_HDL CORE In hierarchal design not all pages are getting printed.1 A2 w* j" R) E( P: S% S/ [
1241788 CONSTRAINT_MGR CONCEPT_HDL Issues with changing focus in Constraint manager using keys on keyboard, n" F/ e% O f& y# }" n# e
1242683 ALLEGRO_EDITOR INTERACTIV Color View Save replaces file without warning + R" e" k L% U9 D4 G' j1242818 ALLEGRO_EDITOR PLACEMENT Placement edit mirror option places component on wrong side 2 i( w! H; Q, t/ @. q1242847 ALLEGRO_EDITOR GRAPHICS Need an option to suppress Via Holes in 3D Viewer & P- F, P# E& X2 Y/ H- ~$ u1242923 ADW COMPONENT_BROWSE UCB reports Missing From DB only after selecting the Row in the search results0 r g' L: J9 A7 N" }7 p
1243609 CONCEPT_HDL CORE autoprop for occurrence properties: k" i' j! x( R( g: Z U* i% W% G
1243682 F2B DESIGNVARI after undocking variant icon cannot be redocked back to GUI : z) N6 j; c3 v! W: Q9 z7 ^5 Y' y1243686 ALLEGRO_EDITOR GRAPHICS Invoking Edit->Text, the infinite cursor disappears until edit mode is changed. $ d) C4 P- X8 K0 n5 I. W+ I1243715 CAPTURE PART_EDITOR Pin name positioning get changed after rotating or mirroring& S9 r. r- z% L# @' D7 d
1244945 CONCEPT_HDL PDF PDF Publisher does not include image when file is not located in the root folder / p2 W( u( C# ]& H1245568 CONCEPT_HDL CORE Dual unselect needed for wires attached to other net/source and property is not deselected when component is 4 c9 Z& ^) m) w1245819 F2B PACKAGERXL wrong injected properties information passed during packaging of the design * s' A+ Q/ @1 E9 w( p% H1245916 SCM CONCEPT_IMPORT Where does the folder location reside for DEHDL imported blocks?1 _* T' g. N$ e1 O" G
1246347 CONSTRAINT_MGR CONCEPT_HDL DEHDL crash if environment variable path has trailing backslash character # U, ]% [% N# @$ o" n. ~2 K: g1246896 ALLEGRO_EDITOR DFA DFA_UPDATE on Linux reports err message if the path has Upper case characters 0 D2 r2 P1 v& B2 l* d6 O0 z1247019 SIP_LAYOUT DIE_STACK_EDITOR SiP Layout - refresh/update symbols is mirroring the assembly drawing data on DIE that is placed ChipDown / i! s' }+ A$ X3 C7 ]1247037 CAPTURE LIBRARY_EDITOR Copy & Paste of library parts resets pin name and number # S7 ^9 t5 u2 N2 K1247089 CONCEPT_HDL CORE Group Align or Distribute > Left/Center/Right crashes DEHDL0 M! ~4 M D/ I+ _3 }" x
1247163 CONCEPT_HDL PDF Physical Net Names in PDF not maintained 5 I. U3 L8 I2 o! n, X# f: I, w1247462 CONCEPT_HDL CORE Text issue while moving with bounding box % Y5 n' u8 K' q2 D7 n0 H1247464 ALLEGRO_EDITOR UI_FORMS When using the define B/B via UI the end layer dropdown arrow is partially covered! _2 \, U f/ ~
1249063 CONCEPT_HDL CONSTRAINT_MGR CM and SigXP doesn縯 respect PACK_IGNORE at components ! r9 w4 Y5 T r/ ^1250270 CONCEPT_HDL CORE Part Manager Update places wrong parts # Q0 |% {1 ?! [ G, I& a1251206 ALLEGRO_EDITOR ARTWORK Aperture command cannot create appropriate aperture automatically from design. # W9 f, R- f! M$ N1251356 ALLEGRO_EDITOR INTERFACES Some STEP models are missing in 3D view of footprint, although all components have STEP model mapped in footprint * q0 g/ W% h: P/ m7 V o: p1251845 ALLEGRO_EDITOR EXTRACT Crosshatch arcs do not extract correctly: p2 E; @* b$ X
1252143 APD OTHER When using the beta "shape to cline" command the tool is removing the shape instead of converting it.1 K7 z2 x/ C- N3 `! T7 K
1252737 SIP_LAYOUT OTHER SiP Layout - Option to create shapes from Pins for WLP wafer level packaging technologies' `; s8 v y6 y) q
1253424 SCM SCHGEN Export Schematics Crashes System Architect 4 X+ F! Q' g6 @8 D& C1253508 ALLEGRO_EDITOR INTERFACES Bug - Export IPC2581 exports Crosshatch shapes as filled+ b, V" _2 o6 J n/ E* y. r3 U/ [, c" S1 ?
1253554 SIP_LAYOUT OTHER SiP Layout - Add Netlist Spreadsheet export to SiP layout to help with connectivity auditing I% J; W$ o6 z2 g
1254578 SPIF OTHER Specctra crash with Error -1073741819 for Auto router9 H% P3 v- m/ L( ~# \, \
1254637 ALLEGRO_EDITOR DRC_TIMING_CHK adding nets to a net group causes constraint assignment error, o' F4 h+ L0 b7 V3 [6 E
1254676 GRE IFP_INTERACTIVE Rake Lines disappear when Auto-Interactive Breakout is enabled. , D, a3 ]6 p8 i5 @$ v e1255067 SIG_INTEGRITY REPORTS Allegro hangs on Net Parasitc Report generation $ ~) y e5 L7 P2 m9 j1255267 ALLEGRO_EDITOR SKILL axlDBGetPropDictEntry does not return a list of all objects! `7 U5 u7 B9 ^! b% x& ?
1255383 SIP_LAYOUT IC_IO_EDITING cant move bumps or driver in app mode3 L5 j' k; h6 n; p% x
1255703 ALLEGRO_EDITOR SKILL axlCNSSetPhysical and axlCNSGetPhysical return nil if a constraint set name is provided1 J9 x0 l/ a5 H
1255759 ALLEGRO_EDITOR INTERFACES Change the silkscreen OUTLINE from layerFunction DOCUMENT to layerFunction BOARD_OUTLINE ; A$ M$ g+ A( r$ T5 B" S7 k M4 r1256457 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet from CM crashes the tool 1 ^ E& H- F! a/ A2 R0 p4 N1 R1256597 GRE CORE Allegro GRE crashes while running Plan Spatial, on a particular design( D/ W) C' i# e
1256650 ASI_PI GUI PFE - Cannot generate model file error when using company decap library 6 j: Z' [% i4 w& U& h4 J1256837 SIP_LAYOUT DIE_EDITOR Open and close of die editor takes too long# p+ ^" T; ^$ V& U8 C
1257732 CONSTRAINT_MGR OTHER Bug - Export Analysis Results in CM makes Allegro crash ) g* o' {. j4 B Y6 O1257755 ALLEGRO_EDITOR OTHER Editing time in Display > Status seems to be logging wrong time E# p& \ m; K3 V4 ]7 M+ X1258029 APD WIREBOND The bondwire lost after import the wire information , Z8 G* i$ O( }/ W, b0 M6 w1258979 APD NC NC Drill: There is difference of number of drills.; a- ~1 a- t! N4 F; f
1259484 SIP_LAYOUT OTHER SiP - calc min airgap calculate minimum airgap beta feature improvement' t* i6 f% ^/ G4 d1 D: q# y9 e2 c
1259677 CONCEPT_HDL CORE hier_write -forcereset cause component prop change.5 W8 h& [" a$ `5 L
1259913 ALLEGRO_EDITOR UI_FORMS Unable to save setting of "use secondary step models in 3D viewer" 8 `% L( \1 g' i+ {, N4 @1261758 ALLEGRO_EDITOR EDIT_ETCH Auto Interactive Delay tune (AiDT) is deleting clines% V! O! F' u& t# K- [
1262543 ALLEGRO_EDITOR MANUFACT merge shape results in moved void; q+ n4 {% h4 c! x6 \8 M, H
1264767 ALLEGRO_EDITOR DRC_TIMING_CHK XNET is choosing to resolve to a different name from 16.5 to 16.6 and is causing constraint loss) L* R" X, C# h' X
: I' c! s' f7 Y/ B 作者: pzt648485640 时间: 2014-4-26 16:28
谢谢楼主分享作者: qq371833846 时间: 2014-4-26 23:23
刚刚弄了26的.郁闷作者: 小明网我的天堂 时间: 2014-4-26 23:36
这么快！坑爹！作者: sunyooh 时间: 2014-4-26 23:49
不能下载。。作者: wanily 时间: 2014-4-27 00:06
谢谢分享作者: tubegong 时间: 2014-4-28 09:50
下不了作者: tubegong 时间: 2014-4-28 10:43
下不了，请楼主将其放到网盘好吗，谢谢作者: szhot 时间: 2014-4-28 11:56
能放在在百度盘吗？作者: dsws 时间: 2014-4-28 12:57
