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标题: 关于JTAG参考电压VREF [打印本页]
作者: ych634227759    时间: 2014-4-15 18:32
标题: 关于JTAG参考电压VREF
诸位好，想问下，JTAG的参考电压可以接1.8V吗？我的设计是这样的，FPGA的BANK 0的VCCO是1.8V！
作者: lvsy    时间: 2014-4-16 09:27
本帖最后由 lvsy 于 2014-4-16 10:05 编辑
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可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。$ ^- w, M! e' l' n& e/ g

) r1 {# Y+ ^) U. U2 G如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。- G1 O4 s% Z% N

( x! v; J# ^! K! k' R, {' q3 P* m$ Y2 ~The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The
5 g4 s2 W: @( i. b8 z0 }1 f5 Iconfiguration interfaces include the JTAG pins in bank 0, the dedicated configuration pins
# o* B4 v- }0 T3 yin bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To5 \& S( t1 D! y. c+ \; _
support the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,& Y" J+ K3 l% t# _' ^$ q
the following is required:
" t2 ^+ y- M( h& U1 n7 T; \5 m• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)
/ |9 X+ _. m9 ?6 c: Z# U% [9 i2 bor Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 150 J; ]( N8 X# ?7 f
for 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for
% h0 G6 Y* h1 b% @) n( S1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V- e. u) k/ R' H0 W# O
(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for) G- `% r. D; \$ d1 y
configuration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V., Y$ F2 c  f  _8 T# l
作者: ych634227759    时间: 2014-4-16 11:11
lvsy 发表于 2014-4-16 09:27! I2 L+ L+ D; R, j! `) J) B4 g
可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。1 N' n4 m4 D% M3 J6 G% J" w

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5 O. Y& X" k: x- t7 ~7 X/ ?0 e三克油啦！
作者: ych634227759    时间: 2014-4-16 11:12
lvsy 发表于 2014-4-16 09:274 _: F) L9 H% f1 p8 U2 w+ T: J
可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。2 c* A: B. ^/ e; j" N: u6 W' L
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...
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你也在搞7系列FPGA吗？有空交流下啊，我QQ:634227759！感激不尽！



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