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标题: 关于JTAG参考电压VREF [打印本页]
作者: ych634227759    时间: 2014-4-15 18:32
标题: 关于JTAG参考电压VREF
诸位好，想问下，JTAG的参考电压可以接1.8V吗？我的设计是这样的，FPGA的BANK 0的VCCO是1.8V！
作者: lvsy    时间: 2014-4-16 09:27
本帖最后由 lvsy 于 2014-4-16 10:05 编辑
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. L& `9 p8 y0 }) _可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。* C& c, G* [3 d$ C# i; [

; K8 R1 G! X  m: y1 f4 u0 F$ E2 N如果是xilinx的FPGA，7系列也是可以的。设置CFGBVS管脚，接GND。- E: z  l5 S( T/ j8 h5 z4 x3 D

7 h4 `( x# M: r* ]- {The 7 series devices support configuration interfaces with 3.3V, 2.5V, 1.8V, or 1.5V I/O. The
, Q  M9 h8 P0 F! Uconfiguration interfaces include the JTAG pins in bank 0, the dedicated configuration pins6 E  E. J: F# x% a  H! @, q
in bank 0, and the pins related to specific configuration modes in bank 14 and bank 15. To
& k1 [, v8 W. ?  ^  W, Nsupport the appropriate configuration interface voltage on bank 0, bank 14, and bank 15,6 n% ~, ]8 [' M, ^
the following is required:
" f9 u0 X- [# N! l/ K$ T. C• The configuration banks voltage select pin (CFGBVS) must be set to a High (VCCO_0)
0 {! [/ \5 Y( o- R1 \* p) `or Low (GND) in order to set the configuration and JTAG I/O in banks 0, 14, and 15
! _- r. c2 i7 l! v4 g: w4 b8 Ufor 3.3V/2.5V or 1.8V/1.5 operation, respectively. When CFGBVS is set to Low for
$ _; ~$ J& U5 t1.8V/1.5V I/O operation, the VCCO_0 supply and I/O signals to bank 0 must be 1.8V0 o# M/ I4 Z! j" d- q9 ^0 s
(or lower) to avoid device damage. If CFGBVS is Low, then any I/O pins used for1 ?. i- c0 ^/ U+ A3 j5 }
configuration in banks 14 and 15 must also be powered and operated at 1.8V or 1.5V.
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作者: ych634227759    时间: 2014-4-16 11:11
lvsy 发表于 2014-4-16 09:27
6 q: j7 V- S' i/ X2 y+ y! ^可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。* y! X4 V, z8 }/ R& U/ S4 X
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...

9 O0 ^/ x$ C9 |三克油啦！
作者: ych634227759    时间: 2014-4-16 11:12
lvsy 发表于 2014-4-16 09:278 f! K6 n; N" ?# k; t0 x
可以！对于Altera的FPGA，JTAG接口不是VCCIO供电的，它有专用的电源VCCPD，VCCPD的电压不能小于VCCIO。
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6 {/ J8 f8 U2 `1 n  g3 u. U1 B你也在搞7系列FPGA吗？有空交流下啊，我QQ:634227759！感激不尽！



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