求助-QUARTUS II版本：13.0编译程序出现的问题

XIAOXIAOYUWU

QUARTUS II版本：13.0
" v  `0 Z9 \! v3 Y1 ~FPGA型号：EP2C8Q208
% j" E* n8 j8 Y6 e* E% F8 `在编译的过程中出现了如下的警告：
( W( A7 s  z: b. ?（1）Critical Warning (332012): Synopsys Design Constraints File file not found: 'exp08_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
& @! M3 J8 o/ }) q: ^3 I% iCritical Warning (332012): Synopsys Design Constraints File file not found: 'exp08_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
% `/ q6 I. T! w% n; VCritical Warning (332148): Timing requirements not met
Critical Warning (332148): Timing requirements not met

# D/ {) d# g7 `" R（2）Warning (306006): Found 4 output pins without output pin load capacitance assignment
. a- O8 g0 S& y/ ~" \# u3 [' G        Info (306007): Pin "Data_Out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info (306007): Pin "Data_Out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
& D. O0 ]4 v* g  [. N+ U4 S        Info (306007): Pin "Data_Out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info (306007): Pin "Data_Out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
程序是黑金开发板提供的程序：PS2解码 ，仔细检查了下，程序没有问题。
8 c) R$ C3 x) F9 t+ R! F5 f8 c
求助大侠，有没有什么好的方法来解决上述两个问题。。。谢谢

eda366_murphy

这个 E 文 说，要用 TimeQuest Timing Analyzer 去产生时序约束文件。没有这个，编译器无法工作

dspdesigner

这时说，你的电路没有时序约束文件。在13.0和之后的版本，软件都默认要求开发者提供时序约束文件，如果没有提供，就会给出 “332012” 警告。再者，如果没有提供，软件会自动按照1GHz的要求来进行编译，时序要求当然就达不到了，就会得到“332148”警告。后面几条警告，是说输出引脚没有分配电容负载

zgq800712

有种东西叫衣来伸手饭来张口