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标题: Hotfix_SPB16.60.022_wint_1of1 [打印本页]
作者: steven.ning    时间: 2014-2-10 15:09
标题: Hotfix_SPB16.60.022_wint_1of1
http://pan.baidu.com/s/1bnpaZfD
作者: sztyzhi    时间: 2014-2-10 18:34
太快了，刚装了021
作者: suiwinder    时间: 2014-2-10 21:38
正在下载
作者: yuxifeng    时间: 2014-2-11 10:38
能告知补丁包的功能及解决的BUG吗？
作者: steven.ning    时间: 2014-2-11 11:39
yuxifeng 发表于 2014-2-11 10:38
( k  B/ v  c! t# H7 f( O4 Q能告知补丁包的功能及解决的BUG吗？

8 s3 ^7 ]4 a& P/ k. f+ S/ M* V我只是从EDA365网上搬运了一下而已，原来那个下载太慢，我把我下的转到云盘上,速度快，方便大家下载.更新了什么我也不清楚.
作者: jsf120    时间: 2014-2-11 11:49
找了半天，感谢分享
作者: wolf343105    时间: 2014-2-11 15:15
非常感谢steven.ning,祝你马年发大财.
作者: nbxiong    时间: 2014-2-11 15:46
等的花都谢了，更新好慢，跟看美剧似的。。。
作者: steven.ning    时间: 2014-2-11 19:39
wolf343105 发表于 2014-2-11 15:15% ^: n! P. a, E5 m" ]# i: O
非常感谢steven.ning,祝你马年发大财.
' d, l& a  d* E$ D* w. H  l& G
谢谢，也祝你马年行大运！
作者: steven.ning    时间: 2014-2-11 19:46
yuxifeng 发表于 2014-2-11 10:38( x5 g% q9 h) Y8 \" ]: {
能告知补丁包的功能及解决的BUG吗？

, O) D0 ~. H1 ^8 xDATE: 02-07-2014   HOTFIX VERSION: 022# {; s" Y% g6 D& ?) L; A" I
===================================================================================================================================
0 ~  d* \! |& I" @# iCCRID  PRODUCT        PRODUCTLEVEL2   TITLE
/ V% O, k1 a2 _/ n* g===================================================================================================================================
0 p  T. d8 l- u* h192358 ALLEGRO_EDITOR PADS_IN         Pad_in does not translate some copper shapes
  i6 {; Y4 `2 m5 F$ O, X222141 ALLEGRO_EDITOR PADS_IN          PADS_IN: Extra shapes are created whenimporting PADS design
6 Z8 V& C9 d1 G, `) F3 d. B274314 ALLEGRO_EDITOR PADS_IN         PAD_in boundary defined for flooded area be translated DYN
, T6 H. x4 I! b0 R' V- q; a413919 ALLEGRO_EDITOR PADS_IN         pads_in cannot import width of refdes.! L2 ?6 W  ^8 ^4 f
609053 ALLEGRO_EDITOR PADS_IN         "Mils to oversize" of "pads in" did not workcorrectly for MM data.
& Z  ?7 ]; c3 x* o666214 CONCEPT_HDL    OTHER            Option to increase Line thicknessin publishpdf utility
. Z3 j$ J% n- M  H5 \" }738482 ALLEGRO_EDITOR GRAPHICS        Export image creates black image with Nvidia GeForce 8400M GS Graphicscard
) G! U" d! \( S982950 CONCEPT_HDL    OTHER            change the mouse button for thestroke to have same function with in pcb editor
+ s! ^! d( g( X1020886 SIP_LAYOUT     LEFDEF_IF        a quicker way to promote die pins (byimporting macro_pin list)
. K: Z, B3 D6 _1032678 CIS            VIEW_DATABASE_PA View Database Partgives incorrect result in complex design with variants.9 C5 _! w  S( [; v$ ]% P, Q+ g
1033864 ALLEGRO_EDITOR PADS_IN          pads_in doesnot translates teardropspresent in design7 ^3 I  r  y5 q/ Z- F
1054862 CONCEPT_HDL    OTHER           Option to increase Linethickness in publishpdf utility  \  y  D/ D; U1 J( k& g0 f0 P
1055252 FSP            PROCESS          Add a synthesis option to target agroup to contiguous or consecutive banks% W- o3 @3 U3 D/ A5 h( B
1100772 CONSTRAINT_MGR OTHER            In Constraint Manager > DRC >Spacing the Show Element DRC totals are wrong.
& }* P' J# W1 C6 O0 r1135020 CIS            DESIGN_VARIANT   Variant list is showing wrong results forhierarchical designs
) e. z) s5 e$ ]$ T1138951 SIP_LAYOUT     DIE_ABSTRACT_IF  Fix die abstract r/w to properly supportpinnumbers on ports: S0 `; e# p( d, F5 N$ |
1140042 CONSTRAINT_MGR OTHER            Diff_Pair lengths and analysis arelost after closing and opening Constraint Manager.
( I3 |3 @$ [, c1 n# p; K$ o+ U: ]1143662 ALLEGRO_EDITOR INTERACTIV       Enhancement Request for RMB - Snap Pickto  options increased to include Pin edge
# D# x8 v9 Q" [6 i" \1147961 PSPICE         SIMULATOR        Simulation produces no output data
* p# e7 R4 u3 R2 Z/ n  ]5 S) z4 g) V7 W1150874 ALLEGRO_EDITOR PADS_IN          Dimensions in PADS are not translatedcorrectly during pads_in translation
+ k% e% s0 h% {* W1154184 CONSTRAINT_MGR CONCEPT_HDL      Difference in the way topology isextracted in 16.3 versus 16.6) l1 c1 R5 q: p
1154770 CAPTURE        PROPERTY_EDITOR  Variant Name property doesn't show value inVariant View mode
; j5 S; \# S4 c+ W% r# M* o" ^1158350 CONCEPT_HDL    CORE             Need a warning Message whileimporting a 16.3 sub-design in a 16.6 Design/ o. _+ w0 b  O% }9 Y( i" t* D+ x
1162347 ALLEGRO_EDITOR EDIT_ETCH        Enh- Allow new option in Move commandsuch that it allows stretching etch using only 45/90 degree segments directly
' n! B9 q* E2 I1 Y3 Z  E+ u$ e1165553 ALLEGRO_EDITOR INTERACTIV       Subclass list invoked from the statuswindow does not represent correct colors.* v" U8 H, V3 ~% s4 o0 f& I
1168079 FSP            MODEL_EDITOR     Clicking OK or Save As in rules editorallows user to overwrite the master with no warning
. \% u3 p1 p+ ~, Q3 s# S; {, ?9 h1172043 SCM            OTHER            : in pin name causes SCM to crash
5 z" B+ c; t7 h9 \2 `3 ^: p1172207 CAPTURE        STABILITY        Capture crash while adding new partfrom Spreadsheet
4 G6 V9 _8 u6 o8 U0 ?- ~1172743 ADW            TDA              Allowed character set for thecheck-in comments is too limited
6 [" [; b  P' g1174099 SIP_LAYOUT     WIREBOND         Option to reconnect wire based on 縫in name� in the Wire Bond Replace
: M" J/ D, R! S# [5 ?1177672 APD            IMPORT_DATA      Netlist-in wizard didn縯 provide detail information about whatcolumns have been ignored by import process' v% v, Q& v, Y  q7 F# u7 G9 J' `' p
1177714 CONCEPT_HDL    RF_LAYOUT_DRIVEN RF component's LOCATIONproperty can not be set to invisible
/ M9 j: c. C, d4 i1177820 CONSTRAINT_MGR INTERACTIV       Done the Allegro command when attemptingto launch CM- k8 O8 ~0 j/ N: W
1178586 ALLEGRO_EDITOR EDIT_SHAPE       Number of digits displayed after thedecimal point of Shape Creation function does not match the Accuracy of BRD
1 O4 p: Q& N4 h+ ^8 q1179688 PSPICE         STABILITY        pspice crash for particular HOMEvariable vlaue  R: G" J' z. Y6 o' U, D1 K
1179827 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to Symbolexport - enable field to add Keywords for data fields to excell cells
2 b4 T8 d  X# c( l1179879 SIP_LAYOUT     STREAM_IF        Data file corrupt when exporting Streamdata from SiP database.& s6 i7 J" A2 h
1180164 F2B            BOM              BOM csv data format converts toexcel formats
! V2 c9 F0 i/ w; ~, V7 u0 W1180477 ALLEGRO_EDITOR INTERFACES       IPC-356 output is listing a duplicatelocation in the comment section6 f+ k7 ~5 I5 q  G3 ~! z1 a
1180932 SIP_LAYOUT     OTHER            SiP Layout - Symbol to Spreadsheetadd option for writing to existing spreadsheet
7 v2 x) n* t7 Q# s! T. o' q+ Q1181377 ALLEGRO_EDITOR INTERACTIV       Pick Releative does not work correctlywith RMB-Move Vertex
; t7 _1 ?! \* M" r1181516 ALLEGRO_EDITOR DRC_CONSTR       Getting a "Thru Pin to RouteKeepout Spacing" when there should not be one., |( k* @8 H) y, j# G6 F/ i1 g. V) X
1181739 GRE            CORE             Running Plan > Spatial crashesGRE* W$ }0 A2 D( P  h! s
1181935 ALLEGRO_EDITOR DATABASE         Enh. Property that allows internal C-CDRC errors& w# m7 U2 P0 U/ ~% `' Y8 j1 N: M: j
1182185 SIP_LAYOUT     OTHER            SiP Layout - Import symbolspreadsheet - suppress Family for the font in the XML spreadsheet
% P% R, C" X/ ?8 _1182566 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet to symbol- Enhance ability of spreadsheet exchange to allow for a portion of a full pinmap
1 u7 \% _. V" h( ~' R1182599 CONSTRAINT_MGR DATABASE         CM Prop Delay Actuals do not updateafter Z Axis option is turned ON or OFF and Analyze is run.' s  H. [3 v* U+ p! j2 V
1182892 CAPTURE        SCHEMATIC_EDITOR Pspice marker rotationbefore placement1 S( Q1 X  g2 o* y5 h/ W
1183682 ALLEGRO_EDITOR DRC_CONSTR       Implement Nodrc_Sym_Pin_Soldermask &Nodrc_Sym_Pin_Pastemask to symbol level
$ W! Y- H# V* t; L; }1185445 SIP_LAYOUT     DIE_ABSTRACT_IF  Die abstract export needs to be able toselect xda file type when browsing
, I( c1 S2 {* N# {1185932 ALLEGRO_EDITOR SHAPE            Soldermask in solder mask void DRC0 H" f. ~4 e5 M# l1 X
1185946 CONCEPT_HDL    CORE             Ericsson perfomance testing report5 sept 2013
7 |2 N3 n) @  j9 G- K1187213 FLOWS          PROJMGR          Unable to lock the directive:backannotate_forward
8 x$ [/ _0 Z+ O2 s1187444 ALLEGRO_EDITOR DRC_CONSTR       With this design Database check promptserror "SPMHGE-47: Error in call to batch DRC": i6 i2 q0 I# D
1187597 ALLEGRO_EDITOR DRC_CONSTR       No Package to Package Spacing DRC error,when symbol overlap sideways at 45 degree.$ V) c2 {! N0 y/ Y
1187723 FSP            PROCESS          Synthesis can fail depending on componentplacement
' L3 z4 e& E& s3 c3 e8 z* x1188164 SIP_LAYOUT     OTHER            SiP Layout - Spreadsheet interfacesImport Export and Add Component - include Keyword for NET_GROUP
& b( M; p/ L- n1188245 CONCEPT_HDL    CORE             INFO(SPCOCN-2055): You cannot runthe CHANGE command in a read only schematic  i! [4 [1 W1 _- i4 ?$ i) ]
1190927 CONCEPT_HDL    CORE             Check sheet does not reportshorted signal/power nets if power symbol is connected to a pin
: y, p8 O9 t6 V1191497 ALLEGRO_EDITOR INTERACTIV       ENH: Adding names to the text blockparameters numbers/ [+ Y) T) v4 Q+ \) B: v  |
1192005 SIP_LAYOUT     IMPORT_DATA      Import SPD2 is missing 1 smart metalshape from file8 g) Z& P* U* t
1192204 ALLEGRO_EDITOR EXTRACT          Need ability to extract vias that arelabeled as microvia/ Y5 H, S0 O8 m  K( G, N9 |
1193063 ALLEGRO_EDITOR MANUFACT         TestPrep log displays "Pin is notaccessible from bottom". The component is through hole.
) F4 C. R* p8 F) n  R6 p6 ^+ t1193418 ALLEGRO_EDITOR GRAPHICS         3D Viewer can`t export image  in both SPB166S015 and SPB165S0473 q$ h4 v0 T# g/ e
1194305 SIP_LAYOUT     EXPORT_DATA      export package overlay creates file withno package info
( V$ x- O; ~4 }  x* z9 f3 J+ k1194418 APD            IMPORT_DATA      issue when doFile->import->netlist-in wizard8 e' g6 O, R( A# q5 m, h
1195279 F2B            PACKAGERXL       Ptf files are not being read whenpackaging with Cache7 T* w6 p. C. g2 w9 q8 A
1195374 ALLEGRO_EDITOR INTERACTIV       Modules are not showing up in Tools >Module reports
; t8 }7 I! v7 w; f4 H5 V1196603 SIP_LAYOUT     EXPORT_DATA      Change form for "Write PackageOverlay..." to better support longer lists of routing layers
, f( T) _7 y, W- y6 j5 L. J( ]5 }3 s1197302 CONSTRAINT_MGR UI_FORMS         Inconsistancy in selection of objectfor Spacing Constraint Worksheet7 s( A, m8 V2 U6 s6 A0 ^1 z
1197399 CAPTURE        OTHER            Draw toolbar disappears when usingPrint Preview4 W; i. M# n6 Z9 a# L
1197543 ADW            TDA              TDO does not correctly showdeleted pages
8 R( s, H% p' b8 }. Z1198033 CONCEPT_HDL    CORE             Signals do not get highlightedwhen Show Physical Net Name is option enabled
( i- Q/ z0 F9 M* U5 Q3 H; p# R# g6 l1198468 ALLEGRO_EDITOR GRAPHICS         3D_step model does not show thecorrect view in 3D_Viewer when symbols have multiple place_bounds.
0 q; B" j) G1 t9 F. Q1198617 CIS            GEN_BOM          Mech parts are showing with Partreference in CIS BOM
4 t( [7 j* K2 c- u) J5 X1199764 ALLEGRO_EDITOR SHAPE            Allegro crashes when trying todelete small island on POWER layer.3 h- c6 u8 Y3 `! D& b/ t1 Q
1200232 ALLEGRO_EDITOR INTERACTIV       Moving all items including board outlinewhich is made of lines does not move the board outline in General Edit Mode.
" T9 {9 P+ a' ]4 S# y% Z* n1200748 ALLEGRO_EDITOR INTERACTIV       Additional pin edge vertex object tosnap pick" e3 M+ u& N6 }. P4 @* f
1201056 ALLEGRO_EDITOR DATABASE         Unsupported functionality strip designcreates a .SAV file0 @9 x. ~0 y/ E6 S
1201638 CIS            PART_MANAGER     Part retains previous linking inside thesubgroup! G2 T+ z4 h# x3 L' D, I, }, q8 X( |
1201834 ALLEGRO_EDITOR PLOTTING         Bug: Import Logo command changesresulting imported object4 c& b0 \2 k: a' I' Z
1202406 SIP_LAYOUT     OTHER            enable the dynamic display of componentpin names for co-design dies in Sip Layout3 s/ E. ^: k5 Y, F
1202431 CONCEPT_HDL    PDF              The publishpdf -variant optionshould have a "no graphics" option; {, U! m' K; P4 H
1202717 ALLEGRO_EDITOR DATABASE         About Warning(SPMHA1-108):Illegal linesegment ... end points.
: ~/ R! C. a- K+ G1203459 CONSTRAINT_MGR INTERACTIV       Object Report has no mechanism to outputinformation for a specific design.
9 m' f; g) {* l$ v9 W  t7 _! V1204544 F2B            DESIGNVARI       Variant Editor does not warn on save ifno write permissions are on the file# V9 n2 c! t$ q# [! {
1205500 FSP            CONSTRAINTS MAPP FSP FPGA port mapping VHDLsyntax9 ?+ A8 P' a7 e
1205952 ALLEGRO_EDITOR GRAPHICS         Step Model for Mechanical Part isvisible in 3D viewer only when Etch Top Subclass is enabled
! f8 J" d# y6 k0 E4 h6 g1206103 SIP_LAYOUT     IC_IO_EDITING    add port name property to pins, and addSkill access I/O driver cell data3 [& v, @/ @+ q8 L7 |) `3 d
1206546 CAPTURE        ANNOTATE         User assigned refdes are resettingwhen 緼nnotation type� is set to 縇eft-Right� or 縏op-Bottom�
7 a1 q/ w0 p& p% ~" m% z# V' q1206561 ALLEGRO_EDITOR GRAPHICS         Not all mechanical symbols made with Stepfiles are displayed in the 3D View$ L: S1 B# q' K$ q0 \; ]8 F" h# ]
1207125 SIG_INTEGRITY  ASSIGN_TOPOLOGY  ECSet mapping wrong for 2 bit in a 4bit bus
+ A" A7 [! E+ s; v0 e6 d& |1207386 CAPTURE        GENERATE_PART    Altera pin file not generating the partproperly
& z; k9 ]# P. J* x  c' M1 V1207629 CAPTURE        TCL_INTERFACE    Bug: GetMACAddresses tcl command notworking
6 \' i- g/ W! Q' ~1207994 CAPTURE        TCL_INTERFACE    TCL pdf export in 16.6 fills DOT type pinswith black color
8 x4 D# u# f4 w* r+ W4 W1208017 F2B            DESIGNVARI       sch name is not same when updatingSchematic View while backannotating Variant6 m" r& V; s) M6 o) i
1209363 ALLEGRO_EDITOR INTERFACES       When placing pins using the polarcommand the tool returns 4500.00 for 45 degrees./ ?1 o9 D7 o3 a! B& [2 C% g
1209769 CONCEPT_HDL    CORE             Top DCF gate information missing
2 F: a# E5 i$ [) Q# n1210194 CONCEPT_HDL    CONSTRAINT_MGR   HDL crashes with Edit Via List dialog box
3 i8 d7 {  q2 J2 P; s  h2 a3 N1210442 CONCEPT_HDL    INFRA            Save design givesERROR(SPCOCN-1995): Non synchronized constraint property found in schematicpage
0 q! J2 ]* J/ ?3 _1210685 ASI_PI         GUI              User can't edit padstack inPowerDC-lite3 W. x! Z8 o4 X* Q* v  ~" o2 |
1210744 SIG_INTEGRITY  SIGWAVE          SigWave: FFT Mode Display unit seemsnot to be correct) d  ^9 {4 B8 \+ B, ~1 {
1210829 CAPTURE        NETLIST_VERILOG  Shorted port is missing from verilog file, W2 ^- P) e  ~' ^
1210850 CONCEPT_HDL    CORE             DE-HDL backannotation crashingafter instantiating specific cell from Ericsson BPc Library$ E1 z+ r* O4 \2 d( ?
1211620 ADW            COMPONENT_BROWSE Component BrowserPerformance) x" n+ E$ R+ ^6 o8 u
1212102 ALLEGRO_EDITOR INTERACTIV       Shape edit boundary adds arc mirrored tothe highlighted preview.) Z8 t7 B# ?: i) R; \: S3 ?& E
1213294 CONCEPT_HDL    SECTION          DE-HDL windows mode multiple section fails tosection first contactor pin from column of individual pins
1 k6 _3 t% S  M$ Y2 C1213402 APD            DATABASE         The old "ix 0 0" fix  is now causing the features to lose netsentirely.
9 X/ I5 i$ h: }0 A' @+ b; G0 |' q8 S1213694 ALLEGRO_EDITOR PARTITION        Via connected to Dummy Net pin in Partitiongets connected to shape on the board after importing partition" l8 R: f! L2 \3 i7 S
1214247 CONSTRAINT_MGR UI_FORMS         Selecting the "All" folderin Spacing Constraints in CM does not automatically select the first column forediting
2 x" `! s6 a/ o1214320 SIG_INTEGRITY  SIGNOISE         signoise command with -L and -k option
( l! ~  @% f2 r5 o4 E8 U1214433 CONCEPT_HDL    CORE             Genview does not update sym_1 withports added to the schematic
* T; ~  ^3 L* O7 _' f1214909 ALLEGRO_EDITOR NC               NC Drill Legend show extra rowsfor drills
- B  I! J' N+ l1214916 SIP_LAYOUT     OTHER            package design integrity check forvia-pin alignment with fix enabled hangs
9 {, V) \# v0 p* b1215954 SIG_INTEGRITY  SIMULATION       Cycle.msm does not exist error whensimulating extracted net$ W1 n2 C7 q/ ^
1216328 CAPTURE        STABILITY        Capture crash: m! _* F7 w& T  p2 n! g! |
1216993 ALLEGRO_EDITOR DRC_TIMING_CHK   Allegro crash on SPB16.50.0494 l' w' g2 a0 l2 v" h
1217450 F2B            BOM              ERROR 233: Output file path doesnot exist
/ b7 U( L$ Q2 \0 |* l1217612 ALLEGRO_EDITOR INTERACTIV       Replace padstack will not replacepadstacks that have multiple alphabetic characters in the pin name - AB21-AB374 B/ g8 z: u; `/ B9 T' L
1217823 ALLEGRO_EDITOR INTERACTIV       Compose shape fails with SPMHIS-473% n, c' n6 V7 l/ w) O
1217887 ALLEGRO_EDITOR INTERFACES       An undo option to be made available inthe STEP Package Mapping window
, Z. O; W, x3 b# D" o3 `6 H1218665 ALLEGRO_EDITOR INTERFACES       In step viewer, the bottom side partsare placed above the pcb board surface$ T: Y; q& K8 r3 Z
1219053 PSPICE         PROBE            PSpice crash with the attachedDesign7 v, Z5 ~5 }7 ^1 J3 B
1219067 ALLEGRO_EDITOR EDIT_ETCH        dynamic fillets behavior is unstable  ?+ I1 O% O* e; Q! P2 s2 L" s
1219095 ALLEGRO_EDITOR MANUFACT         Design Cross section chart is taperedfor two layer board6 Z+ y8 b, ^1 h: U
1219126 ALLEGRO_EDITOR SKILL            Skill issue with axlRefreshSymbol()
0 K! ], P# n9 q, d0 @  |1220701 ALLEGRO_EDITOR INTERACTIV       View > Windows > Worldview(showhide view command) fails with command not found
7 L' L2 j- W7 q1 L2 z1221057 ALLEGRO_EDITOR REPORTS          Units in Cross section report forspacing is not synced with the design2 V$ l* D1 p5 e; J1 M
1221139 ALLEGRO_EDITOR EDIT_ETCH        Delay tune is not tuning differentialpair
$ Y! Y0 i, ^; u: `2 ~  o1221157 SIP_LAYOUT     IMPORT_DATA      import spd2/na2 file is not importingdata correctly into sip
5 G$ {! V2 x: @( i2 a1221163 SIG_INTEGRITY  GEOMETRY_EXTRACT Simulation aborts withsevere convergence issue when coupled vias is enabled.5 G% k  f8 E  |/ W" _
1221416 ALLEGRO_EDITOR DATABASE         strip design for function type$ j8 b6 z6 |: L% g
1221931 ALLEGRO_EDITOR DATABASE         Fatal software error when embeddingcomponent
- h: j* W$ a  y$ t1222105 CONCEPT_HDL    CORE             Moving Pins around the edge of aBlock causes the text of the pin to change its text size./ f& L# C  q3 C- R* D0 H
1222124 APD            DATABASE         Same Net DRC's exhibiting inconsistentbehavior.
0 C) M! n, Y# B8 T! {; D1222272 SIG_EXPLORER   EXTRACTTOP       Cannot extract net or open SigXplorerafter selecting a netgroup
' m- n8 h. {' I1222329 ALLEGRO_EDITOR SHAPE            STEP-Model  Symbol which has place bound bottom is on Top, V# @% r$ M! M/ \/ e6 T* c/ }  t- ?
1223183 SIP_LAYOUT     BGA_GENERATOR    Getting an incorrect error message whenusing the BGA generator with a long BGA name.( S9 a5 E' I; Y3 {! ]2 Q
1223662 ALLEGRO_EDITOR REFRESH          Allegro crashes when trying torefresh symbol
! n7 f" m+ M0 B. B+ U: ~% M5 b1 M1223932 CONCEPT_HDL    CORE             DEHDL block desend does not find1st page if its not page1% i7 T* i9 c2 q  f# I
1223940 CONSTRAINT_MGR UI_FORMS         Unable to change CLOCK name inSetup/Hold Worksheet under Timing in CM.$ I8 v3 [6 c4 T% G) X' w
1224127 SIG_INTEGRITY  IRDROP           Is the old static IRDrop in 16.6officially supported?
1 \( a) D; g% n1225492 PCB_LIBRARIAN  CORE             PDV expand vector pins resizessymbol outline to maximum height again6 J/ ~1 t; Q  B/ i  L/ Y
1225546 CONSTRAINT_MGR ECS_APPLY        nets where the referenced ECS mapscorrectly in constraints manager for front end but not in back end
5 t9 e7 {" a, e7 v9 Y/ L1226405 ALLEGRO_EDITOR INTERFACES       File > Export > IDF ask for filterconfig file eventhough it is created in same session and stored in parent folder
& y5 N  ]- M! M5 v1226448 PDN_ANALYSIS   PCB_STATICIRDROP License failure about PDNAnalysis with XL and GXL
# b! U% P6 j- L  E( R2 [) Q1228721 SIP_LAYOUT     OTHER            File Export Netlist Spreadsheetenhance sort to be a natural method per Jedec according to customer



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