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标题: 创建Netlist出现错误,请帮忙看一下 [打印本页]
作者: lxwuming    时间: 2008-8-19 15:52
标题: 创建Netlist出现错误,请帮忙看一下
我从orCAD to Allegro时,出现错误.
2 A; }/ {9 d2 T" I6 j9 g0 XNettev 如下,请帮忙看看哪地方出了问题..
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Cadence Design Systems, Inc. netrev 15.7 Tue Aug 19 15:49:19 20081 w4 t9 B9 ?5 _
(C) Copyright 2002 Cadence Design Systems, Inc.
4 D- o2 n7 b( ~------ Directives ------# ]0 O! J( a2 P- }! W5 j9 r6 P
RIPUP_ETCH FALSE;
% k- G! r/ d# A3 |; MRIPUP_SYMBOLS ALWAYS;
  G, e8 D& U/ s4 ?5 E* `( c+ ]MISSING SYMBOL AS ERROR FALSE;2 O- I' K8 p. N  \. E$ q
SCHEMATIC_DIRECTORY 'd:\project\project\orcad\allegro';$ L: c6 ^- E4 Z; d
BOARD_DIRECTORY '';0 M& {1 Q1 u* t; x$ }
OLD_BOARD_NAME 'halfadd.brd';" b" P3 W% m1 M4 J9 v" w
NEW_BOARD_NAME 'halfadd.brd';" H% j4 Q2 c3 r# x0 y5 P# Y
CmdLine: netrev.exe -5 -y 1 -n -i d:\project\project\orcad\allegro d:\project\project\orcad\allegro\halfadd.brd d:\project\project\orcad\allegro\halfadd.brd
6 j7 u- Y$ P$ y4 u& v6 D, D------ Preparing to read pst files ------
" o- ~/ n* L0 ]6 G: kStarting to read d:/project/project/orcad/allegro/pstchip.dat
; ~% _  m9 f7 ]( A0 r* A  T   Finished reading d:/project/project/orcad/allegro/pstchip.dat (00:00:00.00)  ~, X& `& r* d; G; s
Starting to read d:/project/project/orcad/allegro/pstxprt.dat
: K. v, R# Q; q8 |9 A' M0 V7 A) r   Finished reading d:/project/project/orcad/allegro/pstxprt.dat (00:00:00.01)
" N6 F( p4 c" m4 {0 ^% H  cStarting to read d:/project/project/orcad/allegro/pstxnet.dat . p" I; @$ a* ?
   Finished reading d:/project/project/orcad/allegro/pstxnet.dat (00:00:00.00); C$ h0 w# Q0 @8 {0 x
------ Oversights/Warnings/Errors ------+ a  j7 r9 e0 c) f! y: H( B1 q

" Q1 A  i& x& M0 p3 y  ?9 d#1   WARNING(304) Device/Symbol check warning detected.+ j& m/ F/ k$ S" p
Symbol 'DIP14' for device '74LS04_DIP14_74LS04' not found in PSMPATH or must be "dbdoctor"ed.: Z0 s# @2 R# R
    Alternatively, the JEDEC_TYPE is not defined for the device in the pstchip.dat.+ e! E. n& J5 D' {
#2   WARNING(304) Device/Symbol check warning detected.' a" @! [% k: C
Symbol 'DIP14' for device '74LS08_DIP14_74LS08' not found in PSMPATH or must be "dbdoctor"ed.
- }& m6 [3 G* U    Alternatively, the JEDEC_TYPE is not defined for the device in the pstchip.dat.0 B3 ^3 ]) j; j. b  d3 T
#3   WARNING(304) Device/Symbol check warning detected., s  b' r% q+ e5 q
Symbol 'DIP14' for device '74LS32_DIP14_74LS32' not found in PSMPATH or must be "dbdoctor"ed.
" [! E9 P5 M5 T+ k5 r  K7 v    Alternatively, the JEDEC_TYPE is not defined for the device in the pstchip.dat.( X7 T8 C5 B" r! ~
------ Library Paths ------& A9 ^7 s: t$ i/ V
MODULEPATH =  .
0 y' `; _. o' G  T           F:/Cadence/SPB_15.7/share/local/pcb/modules % Y9 D8 }6 y: f) p3 i$ Y. \8 S
PSMPATH =  .
( V& m* T  R5 w9 v9 U6 I           symbols
- E6 \4 {9 F7 H6 v" x           ..
8 h1 r# N  p: C; n# [           ../symbols
8 t; a3 `9 Q. B4 X. m% n           F:/Cadence/SPB_15.7/share/local/pcb/symbols 6 ]+ \! T: j4 ^% I3 a  w, z+ A
           F:/Cadence/SPB_15.7/share/pcb/pcb_lib/symbols
0 _. M$ g& u/ |, j/ d. `% a: l           F:/Cadence/SPB_15.7/share/pcb/allegrolib/symbols ( [. R# p- i- R7 y, Z# `
PADPATH =  .
0 l1 L& K3 {# H3 N  k           symbols " j: ^  P8 Q- e1 T) ^" O7 [
           .. * E* s/ x' f; k# w* a1 n
           ../symbols
) j! {. Q" K% G: O) K# H$ e  [           F:/Cadence/SPB_15.7/share/local/pcb/padstacks
( B" `9 B4 S- Y  Q; E  G/ I           F:/Cadence/SPB_15.7/share/pcb/pcb_lib/symbols 6 \( D4 d: v9 q1 o& x. Q6 R% G
           F:/Cadence/SPB_15.7/share/pcb/allegrolib/symbols + h7 X% p  \9 u
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------ Summary Statistics ------
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# \; u2 ^& M  I0 Fnetrev run on Aug 19 15:49:19 2008
  y+ l; x0 K9 ^& t9 u   DESIGN NAME : 'HALFADD'0 G; m3 j4 ?/ q+ \4 H
   PACKAGING ON May 28 2006 22:05:31; w: X. |8 ?" \  p- b4 ?) i
   COMPILE 'logic'
+ i) S( w1 M3 x# x' u   CHECK_PIN_NAMES OFF3 L! M, y' }- s  Y2 y; [
   CROSS_REFERENCE OFF) n6 {( ?; ^6 m
   FEEDBACK OFF: Q7 h& y1 B! ~# a8 E5 c. Q
   INCREMENTAL OFF1 \( b  N* v. h; @+ H3 X/ q, {
   INTERFACE_TYPE PHYSICAL
: ]& Z8 s3 H( g* U  L: d4 }( V5 E) t   MAX_ERRORS 500
: e& [: P9 X/ @8 c3 x+ y" a8 [   MERGE_MINIMUM 5
$ h4 ^+ |& T& O- a8 v   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'6 l& m% x- s% j% Q4 ~4 Y$ o# Y, m
   NET_NAME_LENGTH 24  T4 Z1 K8 l7 v, c; {# @
   OVERSIGHTS ON+ G7 X* ~; [* U1 b) l$ Z* D! i
   REPLACE_CHECK OFF1 z( v+ ?! D- x) B$ `3 U) }
   SINGLE_NODE_NETS ON8 s# b9 x' O/ h4 t& I& N& q
   SPLIT_MINIMUM 0
5 s  Q6 w: D7 J( A8 r   SUPPRESS   20
2 X& \' t$ s0 S, t   WARNINGS ON
5 S/ M' L; h: b8 B/ \, l% y No error detected
; q7 ~/ d6 g- C* Y No oversight detected+ K, P+ N$ F( Y9 `2 p; M. {
  3 warnings detected
& e; n' d+ P; R5 ?' o& Ucpu time      0:00:14
8 K5 U0 J# `8 D+ J) X3 L8 }elapsed time  0:00:00
作者: sutee7907    时间: 2008-8-19 16:18
封装没有找到吧，应该有个封装对应的PSM文件。
作者: lxwuming    时间: 2008-8-19 17:22
你的意思是,我在创建Netlist前,要在Allegro中做好原理图中各零件的封装?
作者: lihuizju    时间: 2008-8-20 10:55
最好是这样，不过如果不直接从CIS里将Netlist导入到Allegro中的话，即只生成Netlist是不会要求有相应封装的。但是一旦需要导入到Allegro中的话，那就必须要有相应的封装。
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1 t( ^$ Y2 }" q% ~: A) W+ i5 u8 J[ 本帖最后由 lihuizju 于 2008-8-20 10:57 编辑 ]
作者: genys    时间: 2009-1-5 15:08
楼主,您的这个问题怎么解决的啊?我也遇到同样的问题
作者: sunhui_scut    时间: 2009-1-5 15:35
我今天也遇到这样的问题了，已经解决了。你把DIP14.dra、DIP14.psm和相应的焊盘文件放到封装目录下就ok了。要是没有这样的文件你就必须自己做封装了。
作者: wzwang2000    时间: 2012-6-18 15:15
恩，楼上正解，



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