: }& n s0 i' x( n' t4 sCCRID PRODUCT PRODUCTLEVEL2 TITLE 1 E B$ E& \( f5 f, i2 M7 F9 H" H, h$ t5 v+ T% r# y+ e" l- b
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. p$ T/ w5 c. Z* D" i$ |735992 ADW LIB_FLOW Create Test Schematic does not use the correct package type + @# m1 t' j" v, {6 ^1 B6 l m0 L$ ]7 I: ~# |) V
1121403 FSP PROCESS "Assign to Pin" not getting obeyed by Synthesis.2 p8 [4 T8 U9 M
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1141844 RF_PCB DISCRETE_LIBX_2A ADS Lib Translation Pin Soldermask/Pastemask missing6 N% r9 m' u, q- E' ~6 R
" Q! Q9 u8 R% S s1169269 ALLEGRO_EDITOR DRAFTING Dimension placed on package symbol moves to different place when it is placed on brd file./ ?& c f+ e% N) W2 d7 l
5 w' ]2 L* `8 B+ p1170488 ALLEGRO_EDITOR MANUFACT Dimension text(on .psm) move to different position, when it is placed on .brd.0 H3 V" K! y) G: o& W: K o8 R
$ T* c' J% j: C/ A) |1173345 CIS CRYSTAL_REPORTS Crystal Report - Display Parameter dialog for export option) f+ t/ J8 {2 B7 y
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1181759 SCM LVS SCM Crash when doing update all that executing import physical command.7 x) u4 I- t5 \( `" V$ }3 R
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1182499 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks (all pins and via) drill.: L d9 h* B: _* A& T
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1184682 CONCEPT_HDL CONSTRAINT_MGR Net Constraint not transferring to layout from schematic / e u% p" {+ I9 W! \" i % c' s' e$ F. v0 i! q7 M1185524 F2B PACKAGERXL Enhancement User would like notification of pack_short in pxl.log 3 W9 q! F" v: N* I! S 6 ~! E- j* Z! q& T6 m9 U1185902 ALLEGRO_EDITOR SHAPE Update shapes dont clear some diffpairs in HF15 . \' ?; z) e* h! M$ P5 a1 M( G% |5 w( p& W
1186152 ADW LRM Part Status for Deleted Part in LRM is distinguished with other part status% o7 P9 x" Q$ h1 s
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1186387 ALLEGRO_EDITOR OTHER DXF cannot catch offset value in s047 hotfix. & v r4 J- N4 T, N0 q+ n 8 {6 B: Z& I. n0 w* ~1186805 ALLEGRO_EDITOR OTHER Exported STEP file missing multiple components placed on board% A% F# X i4 d5 v% Z" n/ `6 Q0 x2 _, k
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1186818 ALLEGRO_EDITOR COLOR Custom color not retained during dehilight 5 E$ @8 q* P3 c6 i' Z) z2 g9 u. C2 f; q; K
1187196 CONCEPT_HDL CORE TOC not populating (page 1)4 W2 H9 g2 j* L' D% }. T
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1187667 F2B PACKAGERXL Existing hard LOCATION property in drawing was left unchanged % w, w: n3 w5 i5 V' F, N+ s . z+ c+ {& j' w1188264 ALLEGRO_EDITOR MODULES Some fillets not regenerated in module created from a board file. ! W9 O& @/ R$ F7 ] N , ]) i2 |! L, u }) n6 {1 M1190144 ALLEGRO_EDITOR OTHER Fillet shape is not genrated around cline , E/ ?1 @, E8 A; \" T* t! X2 w% V0 z0 j* D$ I* L6 }
1190210 F2B BOM The bomhdl.exe fails - MFC Application has Stopped Working 9 n- B9 s% [0 g# P2 \9 I: c# C + A/ O- L7 B# ?6 ?5 t1190618 ALLEGRO_EDITOR GRAPHICS Enhancement for Visible grid ) L& U( N+ V3 |4 C/ Y' B8 m# p, h8 h9 z: W3 }
1190813 ALLEGRO_EDITOR INTERFACES 3rd party netlist file in TEL format fails syntax check but imports successfully 7 |! W" s# ]( ?& a( X* B( w9 G9 }# B% y+ S, {& ?- ?0 A) n! J
1190895 ALLEGRO_EDITOR EDIT_ETCH Route delay meter displays violation when sliding diff pair N" R# \5 o4 J* ]
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1190908 F2B OTHER DE-HDL aborts if dummy net is being cross-probed from PCB Editor # `( ~& ]7 ?. \0 B1 J( h& P 2 d' o9 K! Q( c1190990 CONCEPT_HDL CORE Mismatch in .csa and .csb files+ b& j4 G) l: c( ~& m; d! X
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1191008 CONCEPT_HDL CORE Remove Binary File feature doesn't work # m) ]' e2 M" w, I$ I( G8 w( V4 F5 g
1191514 SCM PACKAGER Packaging error PKG-100- ]( f- b9 K: ~9 p) K* B5 d
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1191517 ALLEGRO_EDITOR DRAFTING Metric +tolerance when using dual dimensions is not displayed correctly4 _; f: A# P- \& a* T: w' Q- J
9 [: B M- C' D1192561 ALLEGRO_EDITOR GRAPHICS Padstack with offset is not showing correctly in the 3D Viewer.% p0 h9 `" i( ~
- Q3 v) d' B9 z3 n( ?* o1192916 ALLEGRO_EDITOR EDIT_ETCH Wrong static phase values are shown in the dynamic timing meter for certain Diff pairs compared to CM. 3 [+ G1 g9 d: }; c; |6 ?% V ^3 x; N% i5 E2 ]& n) H3 i
1194197 ALLEGRO_EDITOR OTHER Step export to include through hole padstacks.( n5 f/ j4 N( n, ]* J9 U$ K
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1194239 PSPICE DEHDL Associate Model does not launch from DE-HDL X3 q7 \1 {6 q9 y+ l, Y- i' Z
