9 O9 B" {/ S* ]& _7 H. yDATE: 07-26-2013 HOTFIX VERSION: 013, q" H6 Q3 e: e) ^
=================================================================================================================================== % I" P7 Q6 x& Z" K8 t. q$ a8 gCCRID PRODUCT PRODUCTLEVEL2 TITLE, r; { T0 [4 J. m# u& F5 B
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111368 CAPTURE CORRUPT_DESIGN Capture - will not produce allegro netlistwith 10.02 f3 Q" s# V2 n1 w
134439 PD-COMPILE USERDATA caCell terminals should be top-levelterminals) @$ ]% ^; g( _' u( X% r
186074 CIS EXPLORER refresh symbols from lib requires youto close CIS; N U+ [8 j- v) F( D7 H! C7 r
583221 CAPTURE SCHEMATIC_EDITOROption to have the Schematic Page Name as a Property in the Titleblock) S/ M4 z/ {7 S; Y
591140 CONCEPT_HDL OTHER Scale overall output size inPublishPDF from command line 6 K# ]0 ?6 R8 d801901 CONCEPT_HDL CORE Concept Menus use the same key"R" for the Wire and RF-PCB menus* T" b, A) v* ]
813614 APD DRC_CONSTRAINTS With Fillets present the "cline toshape" spacing is wrong. 1 j" g- E; ]8 V& k6 Q881796 ALLEGRO_EDITOR GRAPHICS Enhancement request for Panning with Middle Mouse Button 2 N5 J; D9 \7 k$ x8 J$ g* W- W887191 CONCEPT_HDL CORE Cannot add/edit the locked property% F0 X1 ]. y' K( S3 S6 {
911292 CONCEPT_HDL CORE Property command on editing symbolattaches property to ORIGIN immediately 0 N! o3 q8 \8 E+ i: y+ K& L$ p* m987766 APD SHAPE Void all command gets result as novoids being generated on specific env. 5 X: M& a1 ]" }1001395 SIP_LAYOUT ASSY_RULE_CHECK Shape Minimumvoid check reports lots of DRCs which are not necessary to check out. # E4 C- R5 w( v9 ~1030696 ALLEGRO_EDITOR INTERACTIV Enh - Allow another behavior of PANmovement using middle mouse in Allegro4 q* N) g- g3 S0 m" N. V) Y2 T+ a
1043856 ADW TDA Diff between TDOand DE-HDL Hierarchy Viewer is confusing to the user3 V) o7 H# U$ |: ^. Q* j; c* Z
1046440 ADW PCBCACHE ADW: ImportSheetis not caching libraries under flatlib/model_sym when the source design is notan ADW project 7 ]6 h5 x1 Q! _7 C3 n/ H* x% l1077552 F2B PACKAGERXL Diff Pairs get removed when packing withbackannotation turned on" E* M- k" }. t3 g6 \7 Y7 `
1079538 F2B PACKAGERXL Ability to blockall 縮ingle noded nets� to the board while packaging.' K5 J/ h9 `6 Y }+ W6 m
1086362 ALLEGRO_EDITOR SHAPE Enhancement request to autovoid a viaif shape cannot cover the center of the via. - t4 L: h% w" h3 E5 ]: r1087958 PSPICE MODELEDITOR Is there anylimitation for pin name definition? 9 T X' d7 `* _" y- J1087967 CIS UPDATE_PART_STAT Update part status window shows incorrect differences ( T' B9 a5 N/ c- k) g1090693 ADW LRM LRMauto_load_instances does not gray out Load instances Button2 G: M2 Q4 h0 Z% x
1097246 CONCEPT_HDL CORE ConceptHDL -assign hotkeys to alpha-numerical keys % z; M5 [: O5 T5 J$ M' _1099773 CONCEPT_HDL CORE DE HDL goes intorecursive loop if a custom text locked at site level is deleted from Tools >Option3 z5 A" p- v t9 W5 D: X
1100945 SCM SCHGEN SCM generatedDE-HDL has $PN placement issue- r! X/ `' g1 v3 v$ m
1100951 PSPICE SIMULATOR Increasing theresolution of fourier transform results in out file e- Z* u: X1 b$ R; w
1103117 RF_PCB FE_IFF_IMPORT Enh- Allow theAllegro_Discrete_Library_to_ADS_Library_Translator to output in its originalunit, S% _3 ~0 V' @" H; t2 |
1105473 PSPICE PROBE Getting errormessages while running bias point analysis.$ P* u V8 O3 g1 t1 Q' a4 n
1106116 FLOWS PROJMGR view_pcb settingchange was cleared by switching Flows in projmgr.' x- ]1 n( N! ^3 c
1106298 ALLEGRO_EDITOR INTERACTIV Copy Shape uses last menu pick locationas origin and not the Symbol Origin as specified in Options. ]9 ~" S& b, i9 d
1106626 CONCEPT_HDL CORE Concept HDL crashes when saving pages / Y( D1 d; J# H" A7 _+ c1107086 ALLEGRO_EDITOR INTERACTIV manual void with arc's goes in wrongdirection during arc creation , T: ~( W6 B8 P) N0 g: y) A1107172 CONCEPT_HDL OTHER Project ManagerPackager does not report errors on missing symbol 1 B X( E8 A) Q. t* v1108193 CONCEPT_HDL CORE Using theleft/right keys do not move the cursor within the text you're editing + _+ j! P3 d# T' [6 _1 {! t1108603 PCB_LIBRARIAN VERIFICATION PDV ToolsVerification > View Verification (CheckPlus) leaves<project>.cpm_tmp.cpm* S: j5 L7 J, l8 ?9 s
1109024 CIS OTHER OrCad performance issue from Asus. 1 j' J, q+ @ s& c1109109 CAPTURE NETLIST_ALLEGRO B1: Netlistmissing pins when Pack_short property pins connected # C, i) Q6 \3 a2 F& t1109466 ALLEGRO_EDITOR ARTWORK Artwork create some strange gerberlines for fillet.9 j$ N7 R: s, O
1109647 SIP_LAYOUT DEGASSING Shape degassingcommand enhancement - control over what layers are counted in even/odd layersets.( ^4 I0 d! g _3 h* b. o
1109926 CONCEPT_HDL CORE viewing a designdisables console window : c b1 N) t8 V" r8 I' Z1110194 SIP_LAYOUT WIREBOND If OpenGL settings for display ofdynamic net names is enabled, should be visible while push/shove wirebonds., ~7 R' z! X/ H3 w3 @
1112357 SIP_LAYOUT WIREBOND wirebond commandcrashes the application : S7 Q8 Z4 C8 D% q3 T( Q" v1112395 CONCEPT_HDL CORE 縗BASE\G� for global signal is not obeyedafter upreving the design to 1650. c/ Q, k* I7 J0 X3 ^; u1112658 CAPTURE PROPERTY_EDITOR Changing Part 縂raphic� value from property EditorChanges Occ refdes values to instance ( }) n e2 C- y( r$ M1112662 CAPTURE PROJECT_MANAGER Capture crashesafter moving the library file and then doing Edit> Cut$ G. H% [2 Q0 S9 @7 D
1113177 PCB_LIBRARIAN CORE Pin Shapes arenot getting imported properly2 h2 U0 ?$ A( l( X; L7 Q
1113380 ALLEGRO_EDITOR INTERACTIV Change layer to - option for packagetype .dra is not available in 16.6 release) G% o0 `( k7 r2 t2 n
1113656 SIP_LAYOUT WIREBOND Enable Changecharacteristic to work without unfixing its Tack point. ) @% [! C" n) p+ h9 @6 S; U( ^1113838 SIP_LAYOUT DIE_ABSTRACT_IF probe pinsdefined in XDA die abstract file are added with wrong location , E* q8 Z+ s9 }7 D3 h: W# N, ^1113991 CAPTURE GENERAL Save Project Asis not working if destination is a linux machine c& k+ L. u; o1114073 APD DRC_CONSTRAINTS Shape voidingdifferently if there are Fillets present in the design. . a' B" E! U/ ~6 V% k1114241 CAPTURE SCHEMATIC_EDITOR Port not retaining assigned color, when moved on theschematic' t8 d% T; Q0 D8 [" v) @. V9 E* |
1114442 PSPICE PROBE Getting Internalerror - Overflow Convert with marching waveform on 0 y& i8 N% B2 a. }1114630 CONCEPT_HDL ARCHIVER Archcore failsbecause the project directory on Linux has a space in the name 1 }' m1 Z7 U. x" x7 N1 h& ~1114689 CONCEPT_HDL CORE Unknown projectdirective : text_editor x; S @0 f' m9 x- C/ A
1114928 F2B PACKAGERXL 縀rror (SPCODD - 5) while Export Physical even afterchange pin from A<0> to A 1 e5 T# {$ C* _ [5 z( F1116886 CONCEPT_HDL CORE Crefer hyperlinksdo not work fine when user use double digits partitions for page Border. 6 Z& g' A' i+ U4 L# ~8 `1118088 ALLEGRO_EDITOR EDIT_ETCH Should Plan accurate and Optimize beremoved in 16.6?5 G0 A' a9 P% c5 I- W, \, m
1118734 APD EDIT_ETCH Multiline routingwith Clines on Null Net cannot route in downward direction2 c2 o1 V( ]2 m: T _: B+ ]. Y
1118756 ALLEGRO_EDITOR SHAPE Shape clearance parameter oversizevalues getting applied to Keepouts : _. n& H |3 d6 L- W1119606 CONCEPT_HDL MARKERS Filtering two ormore words in Filter dialog box, l5 S3 }( M( ]. X1 X; ?7 U
1119707 CONCEPT_HDL CORE Genview does not use site colors when gen schfrom block symbol- g) N8 b% `- t: O% Z) e/ R
1119711 F2B DESIGNSYNC DesignDifferences show Net Differences wrongly9 b' Y. O" s: l
1120659 CAPTURE PROJECT_MANAGER "Saveproject as" does not support some of Nordic characters. 7 z( o/ {8 s7 p8 k1120660 CONCEPT_HDL CORE Save hierarchysaves pages for deleted blocks./ H- }+ D2 r [
1120817 SIP_LAYOUT SYMB_EDIT_APPMOD Rotate Pads commands not working while in the SymbolEdit App. mode/ f* w0 N$ z6 g6 h& q( s
1120985 PSPICE MODELEDITOR Unable to importattached IBIS model 2 g3 U: _- v, D; W5 N! \1 a6 n1121171 CONCEPT_HDL CREFER PNN and correctproperty values not annotated on the Cref flat schematic1 l9 {# G* @- M) H, a/ {; u
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change aftersaving and reopening.5 l+ J |8 L' @' {9 z; i. d u
1121382 ALLEGRO_EDITOR INTERACTIV Undo command is limited to two for thisdesign5 h. Y* n$ i& T6 y8 c
1121540 F2B PACKAGERXL pxl.chg keepsdeleting and adding changes on subsequent packager runs* H9 b4 \0 k6 U& G+ @" Q
1121558 ALLEGRO_EDITOR MODULES Unrouted net and unrouted connectionwhen module is placed of completely routed board file. " \( m8 h: ]; }% ?' D5 h1121585 ALLEGRO_EDITOR OTHER Drill Hole to Shape Same NetSpacing with Dynamic Shapes shows wrong result. % P" R+ E* v3 m( e, P! E1121651 CAPTURE SCHEMATIC_EDITOR "PCB editor select" menu option is missing # o+ ^- P N( }: v) ]$ U1122136 SIP_LAYOUT PLACEMENT Moving acomponent results in the components outline going to bottom side of the design. ; L/ f! N4 h7 m1122340 CAPTURE NETLIST_ALLEGRO Cross probe ofnet within a bus makes Capture to hang. / J! {+ U: @) i( ~$ M1122489 CONCEPT_HDL OTHER Save _Hierarchycausing baseline to brd files * Z; m% s, d* l+ g7 {: l, m1122781 CONCEPT_HDL CORE cfg_package isgenerated for component cell automatically 3 T- }1 e1 r) a# L1122909 CONCEPT_HDL CORE changing versionreplicates data of first TOC on 2nd one2 B T7 h3 K* L( o! T7 K& s
1123150 CONCEPT_HDL CORE property on yaxis in symbol view was moved by visibility change to None. 1 N0 a! @% P/ I8 y1 K: R1123176 ALLEGRO_EDITOR UI_FORMS Negative values for pop-up location isnot retained with multiple monitors (more than 2) $ e# ^: L4 N# h/ [4 d0 t1123815 ALLEGRO_EDITOR GRAPHICS Embedded netname changes to a differentnetname( Q: ?3 a$ v, M" b6 w+ K
1124369 ALLEGRO_EDITOR INTERACTIV Sliding a shape using iy coordinate doesnot work indepedent of grid. 0 u- {) o2 r5 \5 a1124544 CONCEPT_HDL CORE About SearchHistory of find with SPB16.58 y( c; P+ X5 U; p& J) a$ p
1124570 APD IMPORT_DATA When importingStream adding the option to change the point # Y4 F+ X5 n) K! p7 @* W8 U1125201 CONCEPT_HDL CORE Connectivityedits in NEW block not saved( lost) if block is created using block add3 E/ x6 R/ f) c- C) ^. r
1125314 ALLEGRO_EDITOR INTERACTIV Enved crash during setting of library paths inuser preference 0 k7 A# c$ g) Z T1125366 CONCEPT_HDL CORE DE-HDL crachesduring Import Physical if CM is open on Linux ) m/ G8 g2 J( k. r/ `1125628 CONCEPT_HDL CORE Crash on doingsave hierarchy, z( Z3 [) c7 l
1130555 APD WIREBOND Wirebond Import should connect to pinsof the die specified on the UI.+ c% t0 S8 @; ^! J) |( g
1131030 PSPICE ENVIRONMENT Unregistered iconof Simulation setting in taskbar * B* |1 X7 l5 }3 W2 P1131083 ALLEGRO_EDITOR INTERACTIV Bug: 16.6 crash in changing the mode inFind filter window: \6 Y; T; d' h
1131226 ALLEGRO_EDITOR PLACEMENT When Angle is set in design parameterswhile placement component is rotated but outline is not.; p0 E1 t0 V+ T2 {3 Q6 M2 |
1131567 CONCEPT_HDL OTHER Lower case valuesfor VHDL_MODE make genview use pin location to determen direction. " N* f# Y, T7 E% Y Q' H1131699 PSPICE PROBE Probe windowcrash on trying to view simulation message 2 \9 \) n- Z- r' M' [7 y1132457 CONCEPT_HDL CORE The schematicnever fully invokes and has connectivity errors. ; D1 z6 R5 A- Q+ j; E6 N1132575 CONCEPT_HDL CORE 2 pin_name weredisplayed and overlapped by spin command. 1 e3 Y: w' q$ O: }. ]( m1132698 ALLEGRO_EDITOR EDIT_ETCH Slide Via with Segment option with newSlide command1 O3 {2 U& p7 @
1132964 ALLEGRO_EDITOR SHAPE Same net "B&B via toshape" errors created when adding shape7 \! [ G5 g$ n$ B
1133677 CONCEPT_HDL CORE Cant delete norreset LOCATION prop in context of top9 S5 E# T3 ^. x; a: D
1133791 CONCEPT_HDL CORE Cant do textjustification on a single selected NOTE in Windows mode.) Q3 S7 d* J9 h3 q; ]- S
1134761 CONCEPT_HDL CORE Why does MousePointer/Tooltip display LOCATION instead of $LOCATION property , z$ @: Y5 V7 U8 f+ T- o% ]1135118 ALLEGRO_EDITOR INTERACTIV Mirror and other editing commands aremissing for testpoint label text in general edit mode.( O! @6 L/ d$ q: k# ]+ F
1136420 CAPTURE GENERAL Registrationissue when CDSROOT has a space in its path " W; `4 J, C! X; R1136808 PSPICE STABILITY Pspice crashmarker server has quite unexpectedly) d; t4 [6 g# @ q ~! ?+ c
1136840 CAPTURE SCHEMATICS Enh: Alignment oftext placed on schematic page) ^+ k. j6 S5 g( R5 t8 Y$ H4 c8 a. X7 B
1138586 ADW MIGRATION design migrationdoes not create complete ptf file for hierarchical designs 9 v7 r# F* A; C% ?2 y1139376 CONCEPT_HDL CORE setting wirecolor to default creates new wire with higher thickness% Q& N+ I. ~- W( f! p$ @
1140819 APD GRAPHICS Bbvia does notretain temp highlight color on all layers when selected.7 |3 a0 U9 F' H* N! I; F* j% t( C1 R$ M
1141300 CONCEPT_HDL CORE DE HDL hier_writesave hierarchy log reports summarizes Successfully saved block x while blockwas skipped8 J5 `, d) }- `; a; ?, w
1141723 ADW PURGE purge commandcrashes with an MFC application failure message! B6 p$ i0 ^: T9 l4 E& h
1143448 CAPTURE GENERAL About copy &paste to Powerpoint from CIS) q* Q9 H8 l6 E* \, G
1143670 SIP_LAYOUT OTHER Cross Probingbetween SiP and DEHDL not working in 16.6 release) d* B* [7 D: ~0 J6 D7 x# ?
1143902 ALLEGRO_EDITOR DATABASE when the shape is rotated 45 degreesthe void is moved. / \* D9 ?5 ~1 Y. m+ C4 P" o/ C1144990 PCB_LIBRARIAN CORE PDV expand &collapse vector pins resizes symbol outline to maximum height! e1 w: f. e* z9 A- I2 j" _ s
1145112 CONCEPT_HDL CORE Warning message:Connectivity MIGHT have changed 8 L6 {7 I9 S- e, L: l9 L1145253 CONCEPT_HDL CORE Component Browseradds properties in upper case7 g8 N. n+ j7 q& g( t/ E
1146386 ALLEGRO_EDITOR INTERACTIV Place Replicate Create add Static shapewith Fillet shape1 D& ]& j4 C7 S3 Y
1146728 F2B PACKAGERXL DCF with upperand lower case values on parts causes pxl to fail1 b5 `9 Z- X3 Q* z6 I7 z* ^
1146783 ALLEGRO_EDITOR INTERFACES Highlighted component is missing fromexported IPF file. 3 v D% L* a9 ~5 y% d1 x3 c1147326 CONCEPT_HDL CORE HDL crashes whentrying to reimport a block3 |! S4 |. ~5 O8 M
1148337 CAPTURE ANNOTATE Checking "refdes control" isnot giving the proper annotation result 2 u5 @0 N4 y) |6 E3 [% h1148633 SIP_LAYOUT INTERACTIVE Add "%"to the optical shrink option in the co-design die and compose symbol placementforms' m! \, q' `% _ e
1149778 CAPTURE SCHEMATICS Rotation of pspice marker before placementis not appropriate ' n8 l& @6 K4 Y9 e, S% u- V1149987 PCB_LIBRARIAN PTF_EDITOR Save As pushingthe part name suffix into vendor_part_number value 8 V" s* A5 q+ x! ?& g0 N1151748 ALLEGRO_EDITOR OTHER If the pad and cline are the samewidth don't report a missing Dynamic Fillet. 1 I9 ~$ \5 Q! s- B1 k1152206 CONCEPT_HDL CORE ROOM Propertyvalue changes when saving another Page9 O2 o6 B% Q# M' r; |
1152755 CONCEPT_HDL COPY_PROJECT Copy projecthangs if library or design name has an underscore' L# p9 i4 }, s& T6 V
1152769 PSPICE ENCRYPTION Unable to simulate Encrypted Models in16.60 c% v' K8 H# | ~: g
1153308 ALLEGRO_EDITOR DRC_CONSTR Creating Artwork Getting Warning"DRC is out of Date" even when DRC is up to date : C3 A5 i+ g' G# L' c1153893 F2B DESIGNVARI 16.6 VariantEditor not supporting - in name 8 c5 {7 D% J, k8 j i9 X1154185 SIG_INTEGRITY SIGNOISE Signoise didn'tdo the Rise edge time adjustment. 7 \: H0 |0 I" r+ k1154860 ALLEGRO_EDITOR MANUFACT Double digit drill character overlapswith figures triangle, hexagon and octagon in NC drill legend- d7 V; G+ C5 v
1155167 ALLEGRO_EDITOR EDIT_ETCH Via structure placed in Create Fanouthas incorrect rotation. , ~# V, ?; X% Q. |( u( v1155728 CONCEPT_HDL CORE Unable to uprevpackaged 16.3 design in 16.5 due to memory7 y0 F4 d# y# i5 n7 S3 p+ g
1155855 SCM SCHGEN A newlyuser-defined net property is not transferred from SCM to DEHDL in PreservedMode " W5 @! M9 s2 v& E* @: c1156274 ALLEGRO_EDITOR INTERFACES Exported Step file from Allegro is wrong! _3 T2 s9 R; e. [. D R
1156316 CONSTRAINT_MGR OTHER Break in functionality whilecreation of pin-pairs under Xnet in Constraint Manager " I. e5 s& j$ [, i1156351 CONCEPT_HDL CONSTRAINT_MGR Loose members inPhysical Net Class between DEHDL and Allegro8 r: S s+ K3 [/ f
1156547 ALLEGRO_EDITOR DRC_CONSTR Etch Turn under SMD pin rule checkthrough pin Etch makes confused./ J& ]! ~% ~* I. A1 S3 V" y
1156779 CONSTRAINT_MGR OTHER Electrical Cset References in CM notworking correctly 1 p; H' J$ \- l' v9 U6 M# G1157167 ALLEGRO_EDITOR SKILL axlPolyFromDB with ?line2poly isbroken- b/ `: }) H; m) C6 c3 ` p' j- W
1158042 ALLEGRO_EDITOR DFA DFA_DLG writes the dra file namein uppercase.# }* C$ m# y8 m
1158718 CONCEPT_HDL CHECKPLUS Customer couldnot get $PN property values on logical rule of CheckPlus16.6. 5 J. ^" `% P9 p- t9 b. p1158970 ALLEGRO_EDITOR SCHEM_FTB Changing LOCATION to $LOCATION in DEHDLdoes not update the .brd file( s) N! T5 D* ?1 c. z
1158989 ALLEGRO_EDITOR INTERFACES pdf_out -l creates a PDF# F. T0 T" P" g* t( C( \
1159285 APD DXF_IF DXF_OUT fails;some figures are not exported& {9 o8 n" p3 ]4 x. J8 {$ s! F) [
1159432 ALLEGRO_EDITOR SHOW_ELEM http:// in the Show Element in 166 donot have HTML link to open the Website 8 Q, d0 W0 o. v7 W: J1159483 PCB_LIBRARIAN SETUP part developercrashing with, ^4 v. l, O% E' r$ w" V
1159516 ALLEGRO_EDITOR EDIT_ETCH Unable to slide cline segment with newslide.9 g ~- X3 Y- a3 l. c! r
1159959 ALLEGRO_EDITOR GRAPHICS 3D viewer displays clines arcsincorrectly- |4 G) i5 S2 v+ r- W1 k; g) s
1160004 SCM UI The RMB->Pastedoes not insert signal names. + j0 U& v& z2 }5 H$ R7 l' g$ W2 |1160410 ALLEGRO_EDITOR DATABASE Lock databse with View Lock option ismisleading: ] Q0 s" j* s' f" M1 [& Q% J* T' Y
1160529 SCM SCHGEN Schematicgeneration stopped because the tool was unable to create an appropriateinternal symbol structure- Q1 ~7 x) j) |/ [. t9 b
1160537 SPIF OTHER Cannot start PCBRouter + P3 Y2 N4 R' ]- C. ?9 k& `1161363 ALLEGRO_EDITOR SYMBOL Getting error SPMHGE-73 when tryingto mirror symbol + W; K7 a2 J+ p% r5 t3 k& V/ o1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset indesign 6 v& E; x2 n7 q/ l3 O1161896 ALLEGRO_EDITOR DRAFTING Tolerance value added for Dimensionsis not working correctly (HF11-12) : _' L+ z" V, i- D1162193 SIP_LAYOUT DIE_ABSTRACT_IF shapes in diafile not linked to the die after edit co-design die * G, D: D8 z. y- r9 @1162754 APD VIA_STRUCTURE Replace Via Structurecommand selecting dummy nets.