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标题:
cadence导入网络表出错
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作者:
wanghairui168
时间:
2013-7-3 11:02
标题:
cadence导入网络表出错
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( Allegro Netrev Import Logic )
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( Drawing : s301pcb_dianchi.brd )
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( Software Version : 16.5P002 )
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( Date/Time : Wed Jul 03 11:06:07 2013 )
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( )
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(---------------------------------------------------------------------)
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------ Directives ------
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RIPUP_ETCH FALSE;
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RIPUP_DELETE_FIRST_SEGMENT FALSE;
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RIPUP_RETAIN_BONDWIRE FALSE;
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RIPUP_SYMBOLS ALWAYS;
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Missing symbol has error FALSE;
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SCHEMATIC_DIRECTORY 'C:/SPB_Data/BRDword';
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BOARD_DIRECTORY '';
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OLD_BOARD_NAME 'C:/SPB_Data/BRDword/s301pcb_dianchi.brd';
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NEW_BOARD_NAME 'C:/SPB_Data/BRDword/s301pcb_dianchi.brd';
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CmdLine: netrev -$ -i C:/SPB_Data/BRDword -y 1 C:/SPB_Data/BRDword/#Taaaaaa04396.tmp
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------ Preparing to read pst files ------
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#1 ERROR(24) File not found
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Packager files not found
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#2 ERROR(102) Run stopped because errors were detected
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netrev run on Jul 3 11:06:07 2013
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF
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CROSS_REFERENCE OFF
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FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL
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MAX_ERRORS 500
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MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
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NET_NAME_LENGTH 24
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OVERSIGHTS ON
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REPLACE_CHECK OFF
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SINGLE_NODE_NETS ON
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SPLIT_MINIMUM 0
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SUPPRESS 20
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WARNINGS ON
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2 errors detected
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No oversight detected
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No warning detected
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cpu time 0:00:25
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elapsed time 0:00:00
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作者:
amaryllis
时间:
2013-7-3 12:07
#1 ERROR(24) File not found
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Packager files not found
作者:
eeicciee
时间:
2013-7-3 13:40
本帖最后由 eeicciee 于 2013-7-3 14:36 编辑
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封装库的路径没有设置吧?
作者:
wanghairui168
时间:
2013-7-3 14:16
eeicciee 发表于 2013-7-3 13:40
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封闭库的路径没有设置吧?
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哦,谢谢,我试试
作者:
wanghairui168
时间:
2013-7-3 19:55
已经调整过了,是PCB library与元理图命名不一样
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