标题: Hotfix_SPB16.60.012_wint_1of1(12号补丁) [打印本页] 作者: dsws 时间: 2013-7-1 12:00 标题: Hotfix_SPB16.60.012_wint_1of1(12号补丁) 本帖最后由 dsws 于 2013-7-1 20:32 编辑 + C; ~7 |& \1 u# ? d8 ^! n 0 Y7 n2 O) y5 T4 Y" J5 oDATE: HOTFIX VERSION: 012( d8 n1 p( D* [! I. I, d8 W% g: V
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CCRID PRODUCT PRODUCTLEVEL2 TITLE . O* e( g" l4 v+ o' G6 \===================================================================================================================================' k! X) h# Q6 \
914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD1 s, f2 T; b: D8 Q
1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files $ _& v5 r! o+ Q6 m1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display$ Q# Z, a) n% Q# J4 {
1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.: z( t* ]3 m. p" i, @! E' k
1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line . v% d- O( n, H$ N, W! C1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command. ) L; g! Z m- Z; Q K( E- ^1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group. % R0 X: \5 C6 s5 f) t1151458 GRE CORE GRE crashes on Plan Spatial Q( L7 S$ S' c6 v
1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy " m. A6 k) U. x& D. X* K1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]* W& ^( m- B' i+ o
1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design; ?! e; M. e' ` e' |
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger/ z; {9 N! t/ ^9 j! d8 u
1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.) q; K0 @/ P4 I) I1 R4 j; d
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places4 G' W# w& o* s7 h3 L
1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail% F7 J+ [1 V7 p v g
1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off. # A0 w) ?8 r+ C: L% n1 J p1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer4 H. o) k; G" p2 H6 V+ p! ~: O
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