标题: Hotfix_SPB16.60.012_wint_1of1(12号补丁) [打印本页] 作者: dsws 时间: 2013-7-1 12:00 标题: Hotfix_SPB16.60.012_wint_1of1(12号补丁) 本帖最后由 dsws 于 2013-7-1 20:32 编辑 9 M; d# {) Y8 C 3 X9 a' u5 d" pDATE: HOTFIX VERSION: 012! { r2 N0 f! g
=================================================================================================================================== # {, k' b$ t8 ?CCRID PRODUCT PRODUCTLEVEL2 TITLE ( y2 g9 k# A! T( m# J8 b& n=================================================================================================================================== ! m: G, k5 Z6 ?0 t9 {9 ]914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD % P2 k# D8 p8 }1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files : [; v9 y7 u; X4 p9 N0 x1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display 0 Q! E5 r2 E1 \8 @/ S# {1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter. ' a* r/ g/ U) Z6 |4 c5 H1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line 7 G. v6 L+ x' c* J1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command. , D# [" O( {, [9 E) G1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group. 6 @( j! y* R% h) l8 Z& S; G' i1151458 GRE CORE GRE crashes on Plan Spatial 1 V/ ]3 Q- K5 D+ {1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy K9 F5 P- R- N9 _9 S. f( G8 E
1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268] : N3 H" L! A2 @1 B& U% n1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design( M' e, _, V' c* b. i5 T
1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger 2 U. u& m. |. L1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.* F6 u1 d) i: B* x! v' \: ^
1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places 7 U9 H. @+ W9 a% H- [3 V( l9 V1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail % \- _+ h, g, H# H1 t1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.9 f) ]5 D1 t* u, h
1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer) s$ K2 x( z2 j% D
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