标题: Cadence Hotfix_SPB16.5.044-2013-6-7 [打印本页] 作者: hzqydq 时间: 2013-6-17 08:20 标题: Cadence Hotfix_SPB16.5.044-2013-6-7 Cadence SPB 16.5下载地址（Hotfix更新至044）1 O# d# w8 [ p' L! ]! Q: f
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Cadence最新版软件SPB 16.5及其Hotfix下载链接如下： " [% Q% L( W; A- v+ nhttp://dl.vmall.com/c0sfvdb4yy - S. U) x+ I$ n/ b8 u " s, \7 r. ?$ v6 X5 o* i7 Z, RHotfix中只需要安装最新的版本即可。 " z0 B; j* j: q3 w ' ]2 ]' Q1 _$ i# _2 C' q' eDATE: 06-7-2013 HOTFIX VERSION: 044& w/ W9 H: H' j* }6 o' Y
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1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers 1 @% H6 [' b, K" R9 u* c2 I" @1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer 3 ]' \. F# A: |/ x2 `3 }1 T1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB6 L# @, V2 J1 e; c! e( X- w+ s
1106116 FLOWS PROJMGR view_pcb setting change was cleared by switching Flows in projmgr. 6 I2 {# t# Q! f) N1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT6 }& V- @" M9 w$ o+ }
1110323 APD DXF_IF DXF out is offsetting square discrete pads.3 h7 i' h/ u G0 q
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files/ p' \( I" D6 W& B
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor) P) e8 b/ h! b
1121353 ALLEGRO_EDITOR INTERACTIV Local env setting will change after saving and reopening. n& R3 b$ _; v( C1122781 CONCEPT_HDL CORE cfg_package is generated for component cell automatically ' g& T* D/ l- c9 M1122909 CONCEPT_HDL CORE changing version replicates data of first TOC on 2nd one! S4 R6 P: M7 m' t2 j
1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board ) }: _, F6 z4 @& N$ [1124544 CONCEPT_HDL CORE About Search History of find with SPB16.5* ]. [4 T W- Q/ R
1125366 CONCEPT_HDL CORE DE-HDL craches during Import Physical if CM is open on Linux# {: v5 C, S( z Y; S1 N/ A) ]
1125628 CONCEPT_HDL CORE Crash on doing save hierarchy' o& h# ^: o- W: y- l
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC. , _1 K/ l7 w& I. o/ z1 j. F1130945 SCM SCHGEN SCM Export Schematic does not copy all cells in the library/ ~7 u% {9 ~- J
1131567 CONCEPT_HDL OTHER Lower case values for VHDL_MODE make genview use pin location to determen direction.5 {# J$ C7 Q* I, w& |$ w! w1 f( w
1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters . k5 G3 C8 J: z, v1 C1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4 1 y: E, o, h9 T- I& t( J1132457 CONCEPT_HDL CORE The schematic never fully invokes and has connectivity errors.! o5 S$ _2 R! q% {+ Q& P
1132575 CONCEPT_HDL CORE 2 pin_name were displayed and overlapped by spin command. 1 l* M" D; U% p8 R# N( Y1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder. m" C y9 h3 f8 ]' D7 C1133677 CONCEPT_HDL CORE Cant delete nor reset LOCATION prop in context of top 0 u& |% \; a. {) I# w) }1133791 CONCEPT_HDL CORE Cant do text justification on a single selected NOTE in Windows mode.: W8 X6 ^0 _; o* d) {
1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border. + }+ x1 J& x% i+ P$ V1134761 CONCEPT_HDL CORE Why does Mouse Pointer/Tooltip display LOCATION instead of $LOCATION property % S5 M6 P% r7 x5 j, n1138586 ADW MIGRATION design migration does not create complete ptf file for hierarchical designs # N) C* {! F7 ?; J1139376 CONCEPT_HDL CORE setting wire color to default creates new wire with higher thickness+ Z+ p. H: h# l2 b
1141300 CONCEPT_HDL CORE DE HDL hier_write save hierarchy log reports summarizes Successfully saved block x while block was skipped( S# j4 l5 {- I8 h! ~
1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero 0 s' g) P( z5 m. h# S" P% }& d1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF& y( X! M a8 l0 o0 C6 N
1145112 CONCEPT_HDL CORE Warning message: Connectivity MIGHT have changed7 \" ]$ ]9 M$ _6 y4 {( b4 C
1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP* A' p) O+ Y$ D0 }( k( Z7 V m" b
1145253 CONCEPT_HDL CORE Component Browser adds properties in upper case. L) B& @. v7 h
1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL( }) `/ c+ h( G4 u: ?
1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.+ c9 y# n, J; M7 x T; c
1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added % s4 E/ a0 }# B0 f( ]6 T1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps7 H5 U8 x7 i6 s7 z. V% @
1146728 F2B PACKAGERXL DCF with upper and lower case values on parts causes pxl to fail 0 G& @, ?2 S9 V9 R5 P1147326 CONCEPT_HDL CORE HDL crashes when trying to reimport a block作者: linsky2000 时间: 2013-7-23 11:51
谢谢楼主分享！作者: iepdcay 时间: 2013-7-23 13:48
可以下载 ，谢谢分享作者: ckcpyongfu 时间: 2013-7-31 17:30
这种更新的补丁，是怎么安装呢？作者: linsky2000 时间: 2013-9-4 13:56