9 o4 N+ \0 E7 B3 R, S8 ]' X * g+ k' p1 d+ c; G9 v" l8 `. bWARNING: [DRC0004] $ W/ R7 w0 W& ?+ DPossible pin type conflict E2,1 Bidirectional Connected to Output: BENCH, C (0.40, 10.10) ( ?2 Z# @+ m. k6 W: Z% o& ]. }* E( L8 x8 X+ D
解决方法:8 D5 b, _9 K2 A1 v+ p
These errors are produced based on the settings in the ERC matrix. If you've finished your design and you think that the connections are correct after you've checked all these errors, you can change the settings in the ERC matrix to remove them from the Design Rules Check. # t6 v. X. U- E' V s* J 6 |2 u: o, i7 HTo change the ERC matrix:& p V( p1 F4 `1 r
1. Select the schematic page in the Project Manager.) S4 G2 L; w4 ?2 ?$ V# R2 @
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2. Choose Design Rules Check from the Tools menu, then select the ERC matrix tab./ C1 \' U+ Z1 b
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3. Make changes to the matrix, then click OK. When you click OK, Design Rules Check will run with the new settings.7 \9 j* h& ?1 k; m! D
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简单来说就是修改ERC matrix,来控制ERC检查,这样就提高了容错能力,更容易通过, 但前提是对自己的设计要有把握,确保正确。 - v: y! S7 L) G% x) x - D( |1 I0 U0 W8 a7 |! Y+ P6 y8 R7 U4 B3 p! B
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WARNING: [DRC0006] + c4 }4 b+ F6 x! J# m1 G0 M1 m
' _% [1 h3 a8 X" Y" J$ f, SNet has fewer than two connections A01( K9 }3 [- o1 ^: f$ s. {$ U
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解决方法:网络标号只有一处,没有配对的,或者网络标号命名有差别,注意必须命名相同才表示连接。0 W Y& b* h0 Z5 n9 q# }
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WARNING: [DRC0006] 1 B; b0 ] v0 q3 `5 ~7 p0 r" X, ~Net has fewer than two connections5 R0 P N3 s8 U4 {
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解决方法:这个warning的产生在于一页原理图上电源bar只有一次连接点,这样就会报; m% W# |7 e. r
! O6 b! D8 U. y. g/ k+ c ; x* u% I. A' X4 l2 o6 F错,通常可以忽略,或者在芯片的电源引脚旁边加一个0.1uF的 bypass 电容 接地就 J$ o4 m0 g5 p0 j9 [8 T
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OK,这种设计习惯也是比较好的,只要名称相同,不同页的电源bar就是相连的。) b4 e* H6 N1 L7 R& F/ d2 l e( O
1 U- ~" W2 }3 ?0 I% OERROR: [DRC0007] ! ?1 r7 w8 N1 f% J- n' @3 l6 P
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Net has no driving source A01-PC / ^6 w; C! e4 |- u" P2 i4 c$ o# w9 u, W8 m# O( ] N% p; K# K9 _' r/ F
解决方法: 总线网络标号有问题,即总线的标号必须与总线名中的一致,例如总线名为:A[0..5],那么总线的分支网络标号就只能取A0、A1、……A5中间的一部分或者全部,而不能超出或者改成其他的。 1 @9 U8 G) C a/ Y8 m+ O" V " ]0 p+ M& T, I" r# `1 G WARNING: [DRC0008] 9 |( [3 b$ v' F* e6 OTwo nets in the same schematic have the same name, but there is no off-page connector--〉 + V' d+ ~2 `2 l ) J5 e. ~: T9 d5 {. v解决方法:you label a port or off-page connector with a name that is used by a power symbol or power pin on the schematic. It would be best to replace the port with a power symbol to transfer power through the design. If you have verified that there are no connectivity problems when running the netlist, you can ignore this warning. - L0 y1 t9 i4 k7 A % G$ V$ K6 o! ~& E9 K P2 p j' O" G$ X
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ERROR: [DRC0026] 0 O3 N# w h4 v5 V. ^ 6 A* X9 \( w( Z! j* eThis reference has already been assigned to a different package type. U1 ( ~" T, j# X6 n3 V3 L& z 9 X8 O- n+ L+ q0 J解决方法:检查U1各个部分part reference还有 封装有没有不同的* I& C/ M8 J) J: A" t' ~+ ?! H7 F; a
# E" B/ b! C- X1 H* K2 n0 f 4 u2 H( t# U, S, @4 \ERROR: [DRC0027] 4 ]9 u# m: h9 `7 R pOther parts in this package have different values or PCB footprints. U1--〉- ~+ Z, r) ^- m m# N3 V" e+ b
解决方法:检查U1各个部分part reference还有 封装有没有不同的# x3 k3 c. n( L" x9 U7 y
6 z8 M2 E7 L) x! Q$ e/ u, y 8 ^! }* ~5 o9 g7 F2 m' u* p6 a( p ' w/ v, c! c: \9 r- f* LERROR: [DRC0029] $ \, }7 ]7 p+ \2 FBus has no name and therefore defines no signals.9 r d2 k, j; g( l5 O
N9792615: e6 h7 P, u# ?- w* o* a1 ^( J
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解决方法:再总线上加上总线名称即可消除两端的DRC错误,总线命名必须和总线两端的的分支网络名相一致,即必须是分支网络名称的集合。 r8 Z# ?5 }, K% _2 I/ U% Z+ V ; O3 V; z5 n0 U: ~- N _1 [
如果在原理图中Ctrl+F找不到出现DRC错误的Net,或出现DRC错误的Net的坐标超出图纸范围,则应把原理图的Page Size放大,有可能是因为当初画图时某些器件忘记删掉就直接调整图纸大小了。。。确实很低级的错误 + ]# y! @3 C! |5 A l5 p& l0 d0 c* @0 }, n7 T# n$ a8 t
这篇东西也参考了网上很多文章和论坛里面的一些问题和解答,由于自己做得辛苦,所以就综合一下子,结合自己的理解和过程,希望初学的朋友不再对DRC检查迷茫,当然这些内容也不全,后续碰到了其他warning和error再补上来 。 # J y0 l( Q4 W) m1 {) U * z- \: B1 w0 ?4 j { t( g' a: [' Q! O 2 X, M' t5 C& E2 x! `6 U 4 H$ e+ k R+ `7 k$ E* s+ n: R/ Y) [
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