标题: 关于16.6 [打印本页] 作者: terry302 时间: 2013-5-25 16:00 标题: 关于16.6 求大侠指点， 现在Cadence16.6出第几个补丁了？ 各个补丁的修正内容是什么？作者: kingsr 时间: 2013-5-25 16:21
目前刚看到发到10了，修补功能未知。作者: mengshang 时间: 2013-5-25 16:53
刚才看到了，第10个作者: penny190 时间: 2013-5-27 10:39
DATE: 05-24-2013 HOTFIX VERSION: 010# K( b# C t( _. y
=================================================================================================================================== ) V. |- P, S7 y( X2 F9 e+ L+ fCCRID PRODUCT PRODUCTLEVEL2 TITLE i& q/ n8 n6 g* |1 l4 j
=================================================================================================================================== , G9 \, o7 J$ @, D& }1 Z1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer * D b8 R( j5 O) z% Q1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border* o% _2 o) i3 X* G
1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files # ? p) D$ J; ~% Q1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor- k; k, n( u0 ~2 Z! g7 M& P
1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6$ {8 U7 g1 u. t& n1 ]( M+ Y2 w
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border - ?( d$ ]4 _/ f1 \8 s$ X' E/ W! |1131775 ADW LRM LRM error with local libs & TDA R* r0 D1 {0 w: k, p: y j1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP4 3 g. t# L! L' u/ f5 ^2 l1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo; d5 ^/ _; E8 w& R; f
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM. # n, I& ~* U6 {; O1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur # v3 E/ N. _' a' X1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?& K1 Y, i- {6 q$ x/ q% w3 ~
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.9 [/ _8 r- Y p9 @
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor! \; {* ]/ ~) m! \- J) ^
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro & `, X3 x r- q$ a) P% `" a% D1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode. 5 U5 K5 [# W- ?& v$ _, R+ d5 v1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.4 H4 Q5 I6 B" I3 E: u; ]& \6 W
1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash( I7 W5 K F; M- a$ \
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF( T5 z; x5 w7 l. D, t
1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering" i7 a7 E! h1 u \, c4 p
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor, c2 B9 {3 _# p8 P1 i9 d
2 t2 P! f3 S" j7 c& I$ QDATE: 05-9-2013 HOTFIX VERSION: 009; y- M" t+ n* ?+ u6 ^+ F. U
===================================================================================================================================2 U1 E7 K+ `; T% h( ]) S% F, w! D
CCRID PRODUCT PRODUCTLEVEL2 TITLE ' \" H2 {. q& ^! x8 F3 R=================================================================================================================================== l' n/ W3 w( J- N: h+ P' j- T D$ L961420 ALLEGRO_EDITOR PLACEMENT Regardless of the aspect ratio for room of side The QuickPlace by room command could be placed comp0 A! \% q* w' |4 e3 w! C! b
1079862 ALLEGRO_EDITOR SKILL Ability to create IPC2581 layer mapping file by Allegro Skill function/ ~( |" [) d) z. J' V# `
1080734 CONCEPT_HDL CORE Repainting of grid lines during pan or by moving window show as solid white lines instead of gray da 1 z& L1 ?$ `, U+ j( ~1104145 ALLEGRO_EDITOR SCHEM_FTB User defined properties do not appear in PCB ) j _! W$ B* N3 y, [3 K1107547 SCM OTHER v15.5.1 tcl/tk code not recognised in 16.6$ e3 h$ y' E3 L( h# N$ o6 I; r
1110209 CONCEPT_HDL OTHER We can move symbols and wires off grid despite the site.cpm grid lock f9 @% r; m* h4 }
1117825 CONCEPT_HDL OTHER SHOW_CONSOLE_ON_LAUNCH throws an unrecognized directive warning in the schematic editor& C1 `' s% e. A8 H
1118874 ALLEGRO_EDITOR INTERFACES Oblong pad shapes are not shown with correct orientation after DXF export from Allegro - S! o5 j) B" X' ~1121873 ALLEGRO_EDITOR INTERFACE_DESIGN Importing Bundles from Net Groups does not allow any further editing.7 [2 ?+ l. t; K: m! j* p
1122933 CONCEPT_HDL CORE Newly added Toolbars are getting invisible after re-staring Concepthdl# _8 L; ~8 S' J# ` h: r
1124587 ALLEGRO_EDITOR INTERACTIV The Shape Expansion/Contraction command should also be available in EE mode. 6 A2 v4 _5 }9 @$ m* z- w3 q+ s3 }1125895 SIP_LAYOUT LEFDEF_IF Tool crash while moving the slider in the Filter options Macro tab form of the co-design die library manager# ~1 t9 ?8 }/ B
1125962 F2B DESIGNVARI Custom Text in Variant Details dialog box is inconsistent1 ^0 d" R8 k; j: y. `: ?7 Z# ]6 o+ g u
1126096 SCM REPORTS Two nets missing in report 6 C9 P, F! B9 u# k3 V1126134 SIG_INTEGRITY GEOMETRY_EXTRACT Attempting to extract topology hangs APD' u* K$ N K% a; J8 H& g: ^
1126182 ALLEGRO_EDITOR DRC_CONSTR Shape fillet DRC in same net thru via to thru via was removed after update DRC.1 \5 _* n7 K9 a# y3 F7 q
1130280 ALLEGRO_EDITOR MANUFACT stream_out command in 16.6 seems hard coded to look for a design called stream_out.brd! N1 q3 K j' ]7 g) I4 m* z" t
1130737 F2B PACKAGERXL Error - pxl.exe has stopped working x8 V: u: \' M" M7 ?7 I1131650 ALLEGRO_EDITOR PLOTTING PDF Publisher doesnot display few component defination properties in Property parameters W' r4 V5 |" ^7 q: C; O* [9 g8 H
1131764 ALLEGRO_EDITOR EDIT_ETCH Line segment will not slide using the New Slide.6 [1 M5 Z& ^- \+ b1 Q
1132638 ALLEGRO_EDITOR DFA 'dfa_update' crashes when running the utility on the attached foder. # w* b* V/ r8 C/ P/ X+ R. X1133311 ALLEGRO_EDITOR SKILL ?origin switch is not working correctly with axlTransformObject while rotating shapes ; u2 A: ~# n0 Q1133893 SIP_LAYOUT IMPORT_DATA netlist-In Wizard crashes / r0 C3 O, s' m 5 g( ]/ J* {% \; U; LDATE: 04-26-2013 HOTFIX VERSION: 008& C+ q+ [& n9 D; v- f
=================================================================================================================================== $ S3 t* H4 u$ b# `CCRID PRODUCT PRODUCTLEVEL2 TITLE! c% d! M: m' S6 ^3 {! G+ Z
===================================================================================================================================. ~0 q( P3 E% c
876711 ALLEGRO_EDITOR GRAPHICS Mouse wheel will only zoom out using Win7 64 bit9 P$ v0 K6 O; @8 P. P* C
1080386 CONCEPT_HDL CORE Unable to highlight netclass on every schematic page using Global Navigation8 I. N) }! V* B: N0 y
1082587 FSP FPGA_SUPPORT Support of Xilinx's Zync device5 Y- m; M4 G1 x( z8 B2 _
1105286 FSP DE-HDL_SCHEMATIC FSP crashes while creating board in Schgen if it does not find any available license. 7 x+ _: D; T5 q1105461 ALLEGRO_EDITOR DRAFTING Dimension Enviroment deletes Diameter symbol whenever we add anything to Text section7 ~" v6 i- ] w8 G& N: F
1105504 PCB_LIBRARIAN CORE PDV on Linux Move pins by arrows does not stop when release arrow key but keeps on running4 s: {% ]1 p4 T5 f4 ~" f" C5 s
1110126 ALLEGRO_EDITOR GRAPHICS Display Hole displays strange color. 6 k/ Z2 y% i5 |0 Y. E; ?' S, t1113518 CIS DESIGN_VARIANT Incorrect Variant information in Variant View Mode for multi-section parts with occurrence * r/ ~+ f% Y; u# b1117580 SCM OTHER DSMAIN-335: Dia file(s) error has occurred. 5 {2 k- ~. T6 y0 E1117845 FSP DE-HDL_SCHEMATIC Schematic Generation fails without a reason) V& D9 s4 e% w9 z, z2 w0 j
1119864 FSP TERMINATIONS Auto-increment the pin number while mapping terminations.4 A+ a4 p9 C! m) b% C7 P. J
1120250 ALLEGRO_EDITOR MANUFACT Why is the parameter File altered? ; P9 T+ r8 q- s; t Z) }3 m1120414 ADW LRM TDO Cache design issue , _4 F) _% b1 ?: N1121044 SIP_LAYOUT SKILL axlDBAssignNet returns t even when no net name is assigned to via . S# y7 p" Q/ g2 \( X6 I1 ^1121148 ALLEGRO_EDITOR PLACEMENT Ratsnests turns off when moving symbols with Net Groups5 n w4 ^% D1 h$ f0 ^
1122440 ALLEGRO_EDITOR DATABASE Cannot unlock database using the password used to lock it |- p, \* [+ M7 I& s1 Q1122449 ALLEGRO_EDITOR DRC_CONSTR Uncoupled length DRC for diff pair shows different actual length value between show element and CM.+ F j, z2 }% |- q0 i( l8 }% W/ X: d
1122990 ALLEGRO_EDITOR INTERACTIV RF PCB Symbol which is part of Reuse Module cannot be replaced5 P, C1 W: ]8 U# n' G
1123083 ALLEGRO_EDITOR PLACEMENT Saving after mirroring a Place replicate mdd create a .SAV board file.5 b* [. _0 s/ h- n
1123257 SIG_INTEGRITY SIMULATION some of the data signals at the receiver are not simulatable 9 k9 Z3 p; X/ B# L* h/ }% W1123764 CONSTRAINT_MGR OTHER Allegro crash while importing DCF file 2 |5 @9 C0 k$ @# _1123816 CAPTURE PART_EDITOR Movement of pin in part editor; `1 L6 T' N8 Z, U" \7 s
1124183 ALLEGRO_EDITOR EXTRACT Output from EXTRACTA gets corrupted with refdes 50. c, k" v" ~: b6 ?9 s7 Q
9 t2 O- N; ]" ^" t' k: Y
DATE: 04-13-2013 HOTFIX VERSION: 007' A" C8 Y" C/ O7 m! v
===================================================================================================================================' c3 g& m3 {+ h9 V) _
CCRID PRODUCT PRODUCTLEVEL2 TITLE2 B9 |7 V8 ~ I. p6 C
===================================================================================================================================! H6 t. c5 ?8 b* a4 W
1107397 SIP_LAYOUT PLACEMENT Place Manual-H rotates die o' ^+ T% m& @4 I G1 V8 b
1111184 ALLEGRO_EDITOR PLACEMENT NO_SWAP_PIN property does not work in 16.6 4 _5 t9 `$ P' O+ _: ~( c1112295 APD DXF_IF Padstacks� offset Y cannot be caught by DXF.6 p1 I6 |* V2 X; P3 U# k4 K+ ^- e8 ^8 P
1113284 ALLEGRO_EDITOR INTERFACE_DESIGN Rats disappear after moving components + d" e5 y/ l3 r3 Q7 W6 {1113317 CONCEPT_HDL SKILL skill code to traverse design not working properly # n4 A, h1 d4 |3 o1115491 ALLEGRO_EDITOR SKILL telskill freezes command window8 H" V. ?8 Z4 R( ^
1115625 ALLEGRO_EDITOR SKILL Design extents corrupted when axlTrigger is used. % c1 P' w0 h: m2 w1 V1115708 ALLEGRO_EDITOR INTERFACES Export DXF is outputting corrupt data on one layer. ! u# E2 D0 W% T1115850 ALLEGRO_EDITOR GRAPHICS Text edit makes infinite cursor disappear 9 c, a& f$ @' h1 R7 ?/ t1116530 ALLEGRO_EDITOR MANUFACT Import artwork show missing padstacks 4 s9 j9 r5 O; O( t1117498 ALLEGRO_EDITOR DATABASE Why does dbstat flag LOCKED?+ y( N# |; L# c9 q; o
1118407 SIP_LAYOUT DIE_EDITOR net connectivity is getting lost when running die abstract refresh6 I2 D7 c9 |/ p
1118413 SIP_LAYOUT DIE_EDITOR pin number is getting changed when running die abstract refresh9 u2 D3 h5 A8 m2 `# J) h
1118526 CONCEPT_HDL CONSTRAINT_MGR Upreved design now has Constraint packaging errors) G" y8 t3 k, w- w
1118830 ALLEGRO_EDITOR SHAPE Performance issue when moving/refreshing shapes in 16.6. {- K- ~2 H, a
1119784 ALLEGRO_EDITOR INTERACTIV ipickx command gives drawing extent error inconsistently& i4 k& x( w. x" c1 L
1120469 SIP_LAYOUT DIE_ABSTRACT_IF use different padstack for different, but look-alike bumps w; H: \ p+ V0 J5 b1120669 CONCEPT_HDL CORE DEHDL crash on multiple replace of hier blocks & }9 a0 E7 m# |. P. U9 t, A L2 V1120810 ALLEGRO_EDITOR EDIT_ETCH Cannot slide cline segment. * ?* o& }1 l" \ , ^2 P4 h" a8 ]% UDATE: 03-29-2013 HOTFIX VERSION: 006 / x% O' L# a# I* K, d: T3 N===================================================================================================================================! K& [: p- f6 K" J3 S% i
CCRID PRODUCT PRODUCTLEVEL2 TITLE# ~+ I0 q ?' i
=================================================================================================================================== , D" V" P$ J5 k# E F# N2 Q% f625821 CONCEPT_HDL CORE publishpdf from command line doen not work if temp directory does not exist.* S# ~* O }: Q* e! \
642837 PSPICE SIMULATOR Option to disable Bias Points when Primary Analysis in Active Simulation Profile is DC Sweep ; L7 m6 H. {6 J6 P: [; X! w650578 ALLEGRO_EDITOR SHAPE Allegro should do void only selected Shape without "Update Shape".- c, \1 A0 ~/ J ^: X4 u0 d& f
653835 ALLEGRO_EDITOR MANUFACT Double character drill code overlaps with "cross" in NC drill legend7 \# c# ^8 T! @0 F
687170 SIP_LAYOUT DRC_CONSTRAINTS Shape to Route Keepout spacing DRC display incorrect 8 M; S3 N5 f0 {: o( D$ N- E/ z: e787041 FSP DE-HDL_SCHEMATIC FSP Refdes inconsistency when gen schematics1 a" K/ I1 m& K- l2 d
825813 CONCEPT_HDL CORE HDL crashes when copying a property from one H block to other. a; p3 u, n5 e* i$ p2 o
834211 ALLEGRO_EDITOR SHAPE Constant tweaking of shape oversize values is time consuming7 f+ m* f5 r7 E7 G: S& A2 L7 x. b
835944 ALLEGRO_EDITOR OTHER Customer want to change for Jumper symbol by other Alt symbol. G8 d, b2 y0 B# U$ T2 H5 J/ c& G
868981 SCM SETUP SCM responds slow when trying to browse signal integrity 2 t% n* q/ U8 C) v6 t2 \7 i) I871899 CONCEPT_HDL CORE 'Multiple:' column of Grid window in DE-HDL option is too wide ' R% ?3 Z2 Y& v3 g3 s+ ~/ a! ^873917 CONCEPT_HDL CORE Markers dialog is not refreshed) }; }# l7 C% I
887887 CONCEPT_HDL CORE Option to find unconnected Pins/Nets with DEHDL L License/ }! F. U* |; j, i5 ~
888290 APD DIE_GENERATOR Die Generation Improvement, {* Z8 [; T; q6 s" ~+ i$ w) j7 ]% Y+ U
892857 CONCEPT_HDL CORE packager treats R? as a unique reference designator . J& j7 q6 f* M) ^! g8 @902908 PSPICE SIMULATOR Support of CSHUNT Option in Pspice 8 K; t/ ^) P" ]908254 ALLEGRO_EDITOR INTERACTIV Enhancement request for DRC marker to have a link to CM7 W( ?# @0 \0 l1 s( \" U% U% O0 z: s
922422 CAPTURE NETLIST_ALLEGRO Netlist errors when using mix of convert and normal symbols 6 |% s3 W7 x" q$ t" A0 h. K* C$ z923361 ALLEGRO_EDITOR INTERACTIV Stop writting PATH variables in env file if no modifications are done using User Preferences 5 g/ E9 e, v+ E+ J935155 CAPTURE DRC No any warning messages listed in the On line DRC window even executed "Check & Save" to on line DRC & c2 K# X) u7 Q) E! y. O945393 FSP OTHER group contigous pin support enhancement * j+ Q0 g& \6 F$ ]0 z! Y969342 ALLEGRO_EDITOR DATABASE Enhanced password security for Allegro database8 f5 B6 t9 ]1 {. J s5 ^) J6 f
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes G$ w+ \+ R: M1005812 F2B BOM bomhdl fails on bigger SCM Projects6 \1 N1 ?5 k. D; N2 _, Z; a
1010988 CAPTURE OPTIONS ENH: ADD ISO 8601 Date Time format to Capture : s) F* T% G# _; h1011325 ALLEGRO_EDITOR PLACEMENT Placement replication creates modules with duplicate names$ \" W; {. }4 w" q
1016640 ALLEGRO_EDITOR PLACEMENT Error/Warning Message for not finding or unmatched mechanical symbol or fiducials or which are not on a net 7 S$ A+ p" @ R1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical" v6 ?0 t0 {5 U" c: h
1032387 FSP OTHER Pointer to set Mapping file for project based library. 6 ]. s' w5 a$ p; R+ F# F8 P4 E9 Y3 ]1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with 燕LL PLL_3 does not exist in device instance�7 W, Q+ Q/ [* G7 t
1040678 ALLEGRO_EDITOR MANUFACT Text spacing is inconsistant for top and bottom SM layer in xsection chart$ ]0 w8 J9 I- v& V1 Q
1042025 APD WIREBOND Order placement of power rings for power/ground rings generation with using Perform Auto Bonding 9 }9 Y b0 {' t+ P9 A# H! G: I1045500 CONCEPT_HDL CORE Why Search results does not display the correct Physical Pages.# M- `7 W; K; p" a( B1 n5 W- b. p3 n
1047259 CIS EXPLORER Sorting in CIS Explorer is not Numeric even for columns which are of Numeric data type P; y. M6 _- d1047756 CAPTURE NETLISTS Not adding user defined properties in netlist generated by orDump.dll% @. X0 C9 l ~0 c& q5 z3 B) A+ m
1052455 RF_PCB DISCRETE_LIBX_2A RFPCB IFF Export to fix port direction for ADS for footprint having the same pin rotation& C4 S& {$ _7 q2 M7 \
1054314 CONCEPT_HDL CORE Zoom of custom text is different from other schematic objects- C$ H, |: Z7 S9 m2 C9 q! E0 y5 x5 t& _
1061529 CONCEPT_HDL CORE Space can be included in LOCATION value and cannot be checked by checkplus ; ~. }& u& e3 E7 @! \- K1064035 CONCEPT_HDL COMP_BROWSER Component Browser crashes on part number search using a library containing >23K parts' S# ~9 S; ]3 K' c
1064604 ALLEGRO_EDITOR MANUFACT Enh - Include ability to add slot notes to designs% ^& u7 Q# u* d U- ~; b9 ^2 P
1065636 CONCEPT_HDL OTHER Text not visible in published pdf 3 F6 V4 N1 K4 x; t. E0 ?; m5 o: b: ^1065843 CIS PART_MANAGER time stamp on library from different time zones triggers part manager lib out of date warnings ! z% r( Z8 J( Y. \: t' o1066701 ALLEGRO_EDITOR OTHER Missing padstack warnings not in Symbol refresh log summary {) A7 z4 h) H5 q
1067283 SCM PACKAGER ALLOW_CONN_SWAP does not work for lower level schematic parts9 k3 y4 j( V# T/ y* `. F6 ]/ T
1067400 CONCEPT_HDL CORE ERROR(SPCOCD-171): Port exists in symbol but not in the schematic9 `! I" e& H& ~" ^4 [# \
1068878 CONCEPT_HDL CORE Rotating symbol causes the pin name to be upside down 8 ~3 z( p" M( f: `2 V% w w1069896 ALLEGRO_EDITOR EDIT_ETCH Cline changes to arc when routing even when Line lock is set to Line 45 ) {$ L* L& c% I3 C. ?" f; t1070465 CONCEPT_HDL CORE Why does ConceptHDL crash on renaming a Port Signal$ @( W( P/ P4 J
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check; @$ g+ W; G! P" _
1072311 CONCEPT_HDL OTHER Schematics are incorrect after importing design.# v6 \4 h) D; A- z; \
1072691 CONCEPT_HDL CORE Customer has the crash from Run Script of DE-HDL 16.51 again(#3) . `) p* r/ x0 ~% e* _/ C1072859 SIP_LAYOUT DIE_EDITOR padstack selection window crash from Die Editing: Component editing of Co-Design Die + t; V2 |1 W3 \+ I; J9 i1073354 CONCEPT_HDL CORE Bubble defined on symbol pin is not visible on the schematic. k! V8 V2 {8 @" [& B6 d" e/ R
1073837 ALLEGRO_EDITOR GRAPHICS Some objects disappear on ZoomIn ZoomOut 1 `* G: E( w: G! H1074243 ALLEGRO_EDITOR GRAPHICS Allegro WorldView window does not always refresh after dehighlight of objects + Y) n7 P/ i/ t9 [; F1074606 ALLEGRO_EDITOR INTERACTIV Enh - Cosmetic change in Filter Option UI of Replace padstack to indicate multiple pin entry format # F" e$ x/ c* l0 n6 N: F4 a+ X1074794 ALLEGRO_EDITOR REPORTS add commonly reguested via reports to Allegro and ICP reports. Via per net, via per layer per net. Z' C2 w+ P9 D0 ~; n! C' @
1075587 CONCEPT_HDL PAGE_MGMT Unable to insert page in schematic- R" [# j. D, }+ d
1076117 PSPICE PROBE Copy & Paste text/label in probe window changes font size and later gets invisible3 n* ~6 r: D4 B, e3 W2 G
1076145 SIP_LAYOUT DIE_ABSTRACT_IF Issue message in Add Codesign and Refresh Die Abstract if Pin Numbers from Die Abstract exceed 31 chars. , L1 u" b2 ?! n4 ]* N; U X6 _& Z! v1076566 ALLEGRO_EDITOR EDIT_ETCH Sliding diff pair cline that has a min/max prop rule displays the HUD meter inconsistently. : z6 B0 H+ ]3 T5 q1076604 ALLEGRO_EDITOR SHAPE Sliding via in pad corrupts surrounding shape and generates false DRC Errors & s5 X. Y6 O! U. H1076820 SPECCTRA FANOUT Fanout fails to stack vias in bga pads.2 u. B* p5 M- m( a5 X
1076868 ALLEGRO_EDITOR PARTITION Symbols become 'read only' inside a design partition : s, ^# _5 I$ a x! [1076879 GRE IFP_INTERACTIVE Plan Column should not be present in Visibility tab for Symbol Editor * o+ d/ H& N# s1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options8 V, H8 y6 Y# w, R" g
1077026 CIS LINK_DATABASE_PA fonts changes while linking db part in 16.5, A: l0 ?5 k9 _0 x
1077187 ALLEGRO_EDITOR DATABASE DBDoctor appears to fix database but nothing is listed in the log file. / _. C+ c+ q7 T7 y5 K/ v1077527 CONCEPT_HDL CORE ConceptHDL net with name U cannot be found using Global navigate 1 I& m2 f+ ~; T( k0 h0 ?6 M1077621 CONCEPT_HDL CORE DEHDL crashes when saving page 30 f! w) C5 e" [! X
1078270 SCM UI Physical net is not unique or not valid, ?7 s$ N. k7 L3 d, k5 n4 F3 _6 S
1079616 CONSTRAINT_MGR CONCEPT_HDL Packager error in 16.5 which is resolved when system is re-booted& k. ]) w# |3 } n* k# P: W
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle6 E0 I2 q7 I% {2 R/ I
1080142 CIS CONFIGURATION peated entries in Allowed Part Ref Prefs7 N/ R" v9 j- i: f
1080207 ALLEGRO_EDITOR INTERACTIV Separate the 2 types of SOV violations."Segments over voids & Segments with missing plane coverage"0 |; I9 h) }/ ?" x0 s
1080261 PSPICE SIMULATOR Encryption support for lines longer than 125 characters3 B7 J6 P" s+ U
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement 2 I7 I: N$ V }8 z1081001 ALLEGRO_EDITOR PLACEMENT Package boundary is not visible while manually placing a component when using OrCAD license : {% E6 ~. w0 m5 x1081237 ALLEGRO_EDITOR PLACEMENT Place replicate > apply does not apply component pin properties stored in .mdd; `6 ?3 H. U; _( N+ G
1081284 MODEL_INTEGRIT TRANSLATION Space in the file path will create a bogus error h$ k; }8 A8 z1 D5 v& c/ Z6 c
1081346 ALLEGRO_EDITOR INTERACTIV With Place manual, rotation of the symbol is not updated. + B$ ]6 y7 s: t1081760 FSP CONFIG_SETTINGS Content of 澹PGA Input/Output Onchip termination� columns resets after update csv command A4 K* x# W3 G; Z5 ?# ?1082220 FLOWS OTHER Error SPCOCV-3532 K* l0 h7 z: m) D
1082492 ALLEGRO_EDITOR PLACEMENT Place replicate create does not highlight symbols. 7 J) g& G+ n/ }' [, F& x9 R1082676 ALLEGRO_EDITOR EDIT_ETCH HUD meter doesnot display while sliding / add command 6 E' O' ~' A/ d" m. T# f1082737 CAPTURE GENERAL The 澤rea select� icon shows wrong icon in Capture canvas.2 b1 X; a' f+ w& H
1082739 CAPTURE OTHER The product choices dialogue box shows incorrect name- v, g, c" r' P' O2 h/ W- D
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way8 y2 S) g' ]6 |$ \0 a2 u% } U
1083761 CONCEPT_HDL OTHER AGND text missing from PDF Publisher' t* W3 \6 H7 M/ X% }' K+ A
1083964 CONCEPT_HDL OTHER Do not display Value and other attributes on variant parts which are DNI 5 ]- o8 j# [( q0 [4 |3 r1084023 PSPICE MODELEDITOR Model Editor is slow/unresponsive while opening a Model by double-clicking on .lib file 1 B( q# m# t) j: k1084178 ALLEGRO_EDITOR SHAPE Spike create on dynamic void." [$ z7 @. ~ a3 U! I9 P" _: z
1084637 ALLEGRO_EDITOR INTERACTIV Enhancement: Pick dialog should automatically be set to enter coordinates; i6 V" a& K$ N. G; c
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters0 r0 \8 I% x1 t! E
1085347 CAPTURE SCHEMATIC_EDITOR Replace cache results is loss of net graphic changes.9 O( `. Y1 J( @/ z
1085522 ALLEGRO_EDITOR INTERACTIV Allegro add angle to Display->Measure results * {$ G- A4 k5 j+ X1085791 CONCEPT_HDL CORE Publish PDF can not output Constraint Manager properties into PDF file. . i i o# X C' q1085891 ALLEGRO_EDITOR INTERACTIV about DRC update 1 L. V; S; q) ]; q, g! ~1085990 CAPTURE DRC B1: "ERROR(ORCAP-2207) Check Bus Width Mismatch" should be INFO ; _- Z! n# b7 |( _1 T4 f1086514 CONCEPT_HDL COMP_BROWSER Component Browser placement restrictions not working, `5 i' ]" `: a( [% F5 K
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.6 M4 z0 A! o& w4 y
1086671 PSPICE SIMULATOR SPB16.6 pspice crashes with attached design" S0 y" ?3 F* \( ~) o A1 s
1086749 ALLEGRO_EDITOR MENTOR mbs2brd: DEFAULT_NET_TYPE rule is not translated $ K: P8 Z, r$ U$ t# g9 {! m1086886 CAPTURE PROPERTY_EDITOR "Is No Connect" check box in property editor doesn't work for power pins; n; R8 h1 g; \( N( Q% \& d
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity! h B r& c8 F8 L5 i4 E' i; G
1086937 PSPICE ENVIRONMENT PSpice Color map getting doubled leading to crash after colors are modified number of times. ^/ A$ x, i4 Y5 G8 s1087221 CONCEPT_HDL OTHER Part manager could not update any parts.6 Z+ D$ t3 Y& b1 i
1087223 CAPTURE CROSSREF Cross Probing issue when login into system with user name containing white space" X* F+ m( C$ w8 U' y( c# r
1087295 SIP_LAYOUT EXPORT_DATA Enable "Package Overlay File for IC" for concurrent co-design dies too 7 F7 u# ^$ t- F' \5 O6 @3 M1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice% R4 R. o+ D }0 u! R$ D* x; o
1088231 F2B PACKAGERXL Design fails to package in 16.5- k- _/ W6 D! _2 a/ F' W" K A5 @
1088252 CONCEPT_HDL CORE Menu commands grayed out after Save (with 16.5-s035) when launched from ASA.- J& u0 L- g/ U$ T+ R
1088606 ALLEGRO_EDITOR INTERACTIV Pin Number field do not support Pin Range for Symbol Editor5 `# W7 h1 m' G* D* S
1088983 CONSTRAINT_MGR CONCEPT_HDL Units resolution changed in 16.6 Constraint Manager3 r. |" M7 l. D3 b
1089017 ALLEGRO_EDITOR SHAPE What is the cause of the shape not filling?. v2 T$ b( X* U9 c6 Q7 h- B
1089259 SCM IMPORTS Cannot import block into ASA design 6 S* D* C/ w, \$ U, q, G( a; a1089356 SIP_LAYOUT DIE_EDITOR Distributed co-design : launching die editor taking more than an hour to bring up edit form 6 L* r3 b1 d; j8 H# c `6 b1089362 PSPICE STABILITY Pspice crash on pspice > view simulation result on attached project % g# Q6 r% w7 `6 ?6 g- [; p0 l1089368 SCM OTHER Can't do Save - cp: cannot stat ... No such file or directory / F& F. a$ p( Y1089605 CONCEPT_HDL CONSTRAINT_MGR Power net missing from the CM opened from DEHDL Schematic editor. n( k% _% S3 J0 ~1 D
1090068 ALLEGRO_EDITOR SHAPE shape priority issue in SPB165. x4 j7 h4 V( f$ j& }& j$ f
1090125 ALLEGRO_EDITOR DATABASE Q- The rename resequence log file is not giving correct message. ( m" Z2 c ]4 K5 Z1090181 GRE CORE AiDT fails for the nets with errors SPGRE-21 & SPGRE-22 " |5 S) ?3 G7 p+ H5 E! Z' W" f1090930 CONSTRAINT_MGR CONCEPT_HDL DEHDL-CM does not retain customized worksheet. 6 Y; V$ m9 x! h1091335 CONCEPT_HDL OTHER Color change cannot remain in some situation. 2 B2 _% ?/ O: D% |5 ~7 e1091347 CAPTURE TCL_INTERFACE The Project New link on Start Page doesn't work when Journaling is enabled4 Y7 _- z' p: l; S8 Z: J5 d
1091359 CAPTURE GENERAL Toolbar Customization missing description" C+ x9 j1 C) L$ V. f, o4 m
1091662 CONCEPT_HDL CORE Incorrect behavior with the SHOW_PNN_SIGNAME directive% d7 {, C4 y3 t0 ~, ^% z4 O: H, g
1091714 CAPTURE PART_EDITOR More than one icons gets selected in part editor at the same time " j( N8 \! O9 H9 x7 T, z1092411 CONSTRAINT_MGR INTERACTIV In v16.6 CM multiple net name selection under net column is not working as in v16.5. W" J0 v7 {3 i$ m
1092426 CONCEPT_HDL CORE Getting ERROR(SPCOCN-1993) while saving a Hierarchical Design2 {" A$ }5 V) t( H% W" ~8 ^
1092874 CONCEPT_HDL CORE DEHDL wire short during move not detected with check enabled 9 o2 z L F9 G, C; Y( `1092882 ALLEGRO_EDITOR EDIT_ETCH AICC should be removed from orcad PCB Designers design parameters 0 y- K5 d/ G# ]* X# V2 y1092918 CAPTURE GENERATE_PART Generate part functionality gives no/misleading information in sesison log in case of error( A, c+ H8 C3 V/ _4 }) v6 t
1092933 CONCEPT_HDL OTHER PDF Publisher saves the pdf generated in the previous project folder $ L _3 A6 }0 |+ n6 ?* W( Q6 p) O) R1093327 CONCEPT_HDL OTHER Getting error SPCODD � 369 Unable to load physical part in variant editor 0 R9 t! M! P& _1 A1093391 CONSTRAINT_MGR OTHER Setup > Constraints > (domain), doesn't open correct worksheet with OrCAD PCB Editor Professional license. ' x# e9 _$ l9 H3 v1093886 SPECCTRA HIGHSPEED Pin delay does not work in PCB Router when specified in time3 `$ k2 m" ~; w6 Q" p
1094223 CAPTURE PROPERTY_EDITOR CTRL+S does not work in Property Editor but RMB > Save. & Y5 V7 k$ Z, [5 k2 v1 ^5 P1094513 CONCEPT_HDL CORE How to display $PNN for which SIG_NAME is not visible?/ S6 [. P( X' p ~; c
1094611 CAPTURE PROPERTY_EDITOR E1: 'Tools->Update Properties' should list parts which are present in .UPD, but not schematic. B/ v% U' t& @: Y
1094618 CONCEPT_HDL INFRA Unable to uprev the design in 16.56 ?7 k3 B$ A! ]1 R7 H# C& x
1094867 CONCEPT_HDL CORE Page Up / Down Keys are hard-coded assigned to Next /Previous Sheet/ `" P6 M5 h f) r( R; ^9 v
1095449 SIP_LAYOUT LOGIC Allow netlist-in wizard to work on a co-design die 8 F$ R' K# l6 i; }+ T* t1095701 CONCEPT_HDL CORE Replace part in replicated block only preserves the Refdes in 1st instance of the replicated block - y* X. s6 n' U& O! z5 E1 Z: y1095705 CONCEPT_HDL CREFER Cref_to_list not updated on repl icated blocks in 16.5 release worked fine in 16.3 . J7 g4 a5 w3 }; `, \( {" z1095861 F2B BOM Using Upper-case Input produces incorrect BOM results# A" P' j9 g7 \+ M @
1096318 ALLEGRO_EDITOR INTERFACES IDF import not removing MCAD tagged objects during import3 h q( k" o* O, O
1097241 CONCEPT_HDL CORE Concepthdl - zoom in to first object in Find result automatically% _) S' n% T" Y: Z1 J
1097468 ALLEGRO_EDITOR INTERACTIV Need ability to hilight and assign color to vias 8 m% m8 y: O% a1 {3 w7 ?1097675 CAPTURE ANNOTATE Enhancement:Option to have Incremental reference Update to be checked at all times when we click on Tool>Annotate " l9 z+ T/ x- j1099151 SIG_INTEGRITY SIMULATION All Neighbor crosstalk numbers reported when there are no aggressors* L' _1 V- c6 i# s3 U
1099175 CONCEPT_HDL CORE CPM directive that enables the Command Console Window in DE-HDL. o8 _$ a- [9 L" n5 O1 {
1099838 CAPTURE TCL_INTERFACE TCL library correction utility is not working correctly.. u$ z' q. E, y2 t/ g; f" n
1099903 ALLEGRO_EDITOR PLACEMENT Mirror and rotating component places component mirror side 8 N% a) T( E4 r/ b1099941 ALLEGRO_EDITOR PLACEMENT Problem in rotating bottom components when using Place Manual or place manual -h command % {! \/ k" m/ m5 s1099998 CONCEPT_HDL CHECKPLUS CheckPlus marker file not locating signal when signal name includes the # character. , X% w7 g! p( c/ q1100018 CONCEPT_HDL COPY_PROJECT CopyProject gives errors about locked directives1 @; F3 w: C+ B) _
1100449 ALLEGRO_EDITOR ARTWORK Pad with Net_short property and shorted to shape supressed wrongly with Pad Supression in Artwork 9 {) G! }. M/ ]% j1100758 CAPTURE LIBRARY Import properties does not update pin numbers of multi section parts8 N, p+ H& e% L; P8 f* b! w- s
1101009 CONCEPT_HDL CORE Cursor stays as arrow after performing File > Save Hierarchy . I$ N2 v9 P( r* n# }$ D- e$ G* n" C; [' V1101497 ALLEGRO_EDITOR UI_FORMS Allegro PCB Editor crashes using attached script when working with RF PCB Clearances. ! k2 t- c! O% y$ `1101813 SIP_LAYOUT DIE_ABSTRACT_IF Support die abstract properties + x) v' P% r( l: W; I8 z! n1102531 ALLEGRO_EDITOR GRAPHICS Allegro graphics distortion infinite cursor 16.64 G! }; g; ^& u
1102623 ALLEGRO_EDITOR SHAPE Strange void around the pad - g1 Q X; n2 _1 g& y. p! V1103246 FSP FPGA_SUPPORT New FPGA request - Arria V - 5AGXMA1D6F31 - IN2P3 6 y; |- w4 p: @" `1 A3 b1103631 MODEL_INTEGRIT OTHER Model Integrity license when using orcad2 V* w+ o! ^: v& v& F: R1 Z; S8 L
1103703 F2B DESIGNSYNC Toolcrash with Design Differences ' _/ l8 W+ U- V M1103712 CONCEPT_HDL COPY_PROJECT Copy Project crashes on customer design attempting to update symbol view . d5 i$ k. |* `0 V. ^) @1104068 CAPTURE DRC "Check single node connection" DRC gets reset in 16.6 7 R$ E$ t1 k& J& F( ^! R1104121 PSPICE AA_OPT 燕arameter Selection� window not showing all the components : on WinXP % w" y, [0 d( w9 T$ Z2 C1104575 CONCEPT_HDL CORE Allign does not allign offgrid symbols correctly . ]# R2 [8 ~8 E+ R7 J1104727 CONSTRAINT_MGR SCM Net Group created in sip does not transfer to SCM- u8 n$ N F& X1 ~) _- K
1105128 CONSTRAINT_MGR DATABASE Import dcf does not clear out user defined schedule. 8 d, T! s! ?1 m5 d+ m( g1105195 SIP_LAYOUT WIREBOND Request that Tack points default to a "fixed" position after Generate Bond Wires. $ g; ^, A4 g, g0 t' C4 C7 y6 Y1105249 ALLEGRO_EDITOR OTHER PDF out--- component user defined prop doesn't list the prop selection form % C1 ^2 _3 D) @" Q& X) Z1105443 PSPICE AA_OPT Parameter selection window in optimizer does not list param part 6 ~* D3 ~$ Q X/ E0 m: f( r1 n1105818 ALLEGRO_EDITOR INTERACTIV Menu-items seperators are clickable and menu goes away when clicked2 O/ `! n: V# `
1105822 ALLEGRO_EDITOR SCHEM_FTB Netrev failing with compact pin syntax 0 E* F! }1 L2 h1105993 SIP_LAYOUT LOGIC Import netlist no longer works with co-design die in SiP 16.6 + L) S8 p/ J8 i8 [9 i1106332 SIP_LAYOUT OTHER sprintf for axlSpreadsheetDefineCell writes characters in upper case only / ]: p; d1 u) v/ C" q- u1106786 CAPTURE SCHEMATICS Bug: Pointer snap to grid * N. ^2 S6 S+ }4 b& Y1107132 FSP OTHER Altera ArriaV (5AGXMA5GF31C4) support.+ r5 p0 ~& H2 g# o! O% A7 C
1107151 ALLEGRO_EDITOR ARTWORK Shape filling removed when changing artwork format to RS274X in Global Dynamic Param 2 p" F& K6 V8 B7 I. z7 Q1107237 SIP_LAYOUT WIZARDS Updating a Die using the Die Text In Wizard will error out and not finish/ [) o2 H; B2 L* @, \) N0 U4 M
1107371 ADW COMPONENT_BROWSE ADW preset Warning filter is spelt incorrectly. (Wraning).' n4 l3 N; v: [! M, D# Z$ `4 I
1107599 CAPTURE STABILITY Capture 16.6 crash when trying to invoke ( x$ u0 X, K% [( K' O* I$ k1108118 ALLEGRO_EDITOR OTHER PDF Publisher pad rotation messed up with flashed pad.* c3 E% ? W) A! Q. v+ V
1108574 ADW COMPONENT_BROWSE LifecycleStatus functionality does not work when in Metadata mode. Work correctly in PPT Mode 3 D' t$ N/ l# K$ x1109095 SIP_LAYOUT WIREBOND Bondfinger move in hug mode create drcs 0 k. e; {/ x4 g* r0 A e1109113 ALLEGRO_EDITOR DATABASE Allegro Netrev crash with SPB 16.69 o5 E$ c) k, n% _" v) p1 V1 d' Z
1109622 SIP_LAYOUT DATABASE In a wirebond design, the ratsnests with 'Closest Endpoint' should not point to the die pins.. k, I [4 [' I2 O0 d
1110077 ALLEGRO_EDITOR DRC_CONSTR Duplicate Drill Hole DRC's are not shown for Pins overlapped in same symbol unless "Min metal to metal" DRC is turned ON* J' R$ v. N2 j7 v7 K
1110256 ALLEGRO_EDITOR SHAPE Auto void on dynamic shape is not correct in 16.6 9 l7 E* [/ |2 f0 ~) D1110264 RF_PCB FE_IFF_IMPORT IFF Import in DEHDL has component offset# q& V/ z: M- b
1111226 ALLEGRO_EDITOR DATABASE Name too long error with Uprev command when output file name exceeds 31 characters4 d8 X5 d7 K, O% r/ L
1111234 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figures triangle, hexagon and octagon in NC drill legend & t8 v& F) S% w1112431 SIP_LAYOUT COLOR Frequent crash while working with latest version of CDNSIP : W3 Y' g) [2 {, s0 _" f1112493 ALLEGRO_EDITOR DATABASE Customer does not like 16.6 Ratsnest points Closest Endpoint ; {7 t" F1 p. L- Y J2 m. s2 y5 D1112774 GRE CORE Allegro GRE not able to commit plan after topological plan5 R0 d* S. g& \
1113908 ALLEGRO_EDITOR COLOR Dehilight command fails to remove highlight pattern on a cline, without removing net custom color.6 q6 s: V. ]4 M n( [8 a
1114815 ALLEGRO_EDITOR OTHER Q1: Switchversion error when reading -fa file 1 S7 B% X: `- N( t; D! j1 l1114994 ALLEGRO_EDITOR DATABASE Getting an error after upreving components to 16.6 D5 M, K- J$ g+ d% { C. M: K& Y* Y$ P& N% h, u
DATE: 03-7-2013 HOTFIX VERSION: 005; d: a6 X+ [1 w/ g
=================================================================================================================================== 3 u/ b' i) j; \5 G' dCCRID PRODUCT PRODUCTLEVEL2 TITLE 2 j& M9 j5 Z* D- i7 z1 l=================================================================================================================================== - _8 H- \# @% J l; e. F7 g1067770 IXCOM-COMPILE COVERAGE Assertion failed: file ../covToggleCoverageXform.cpp, line 1102 2 T* j1 @- S* Y2 s! F, ~$ b1100442 ALLEGRO_EDITOR PLACEMENT Placement queue shows components whichs are already placed- C! k* a' G7 D4 \+ w5 N, H% H3 t* D
1101555 ALLEGRO_EDITOR DATABASE Allegro Crash frequently/ u$ q- e! F. V+ z
1104011 ALLEGRO_EDITOR DATABASE Place replicate move group of a modules leaves traces behind 5 V2 o( ?: c! Q! N1104065 SCM NETLISTER SCM 16.6 has problem generating Verilog with existing sym_1 view: f2 [3 g. n+ X) d* v0 i: @
1104605 F2B PACKAGERXL Pins of function swapped part in block not displayed 9 V; L5 M5 U& V2 ^; A1104790 SCM IMPORTS Corrupt data once SiP file is imported into SCM 2 l' s1 k( Y+ g7 a" A* b1105066 APD IMPORT_DATA Import NA2 worked in 16.5 "035" but fails in 037 and 16.6 . O: w* e+ y! X4 U1 b I& ]* \# Q1106323 ALLEGRO_EDITOR PLACEMENT Unable to locate specific placed symbol on this board as it becomes invisible after placement.6 }; M9 { B5 I' ?. y1 E* |
1108032 CONCEPT_HDL CORE 'Find' option does not list all Components in the Design- ` D1 t3 F1 ]8 m) R1 Z4 i
1109080 ALLEGRO_EDITOR OTHER Window DRC is not working in OrCAD PCB Editor Professional8 t) L3 n/ g8 D
+ u% d) s2 \ A8 a
DATE: 02-22-2013 HOTFIX VERSION: 004 7 J& `$ U. c9 A2 Y# V2 c=================================================================================================================================== * J5 [$ ]7 f2 }$ Z. k: ZCCRID PRODUCT PRODUCTLEVEL2 TITLE1 Z; ?) f, R8 \# J' ]) q b# ?
=================================================================================================================================== , ?# ~; c0 N4 I# ] l/ z1081026 ALLEGRO_EDITOR GRAPHICS 3D Viewer do not show the height for the embedded component correctly 6 a6 }( g$ O# c% y6 Q( ? Y5 _1095225 ALLEGRO_EDITOR EDIT_ETCH The Constraint option does not work from right mouse click>Options>Line Width > constraint during interactive routing - b+ S, w F# ~. b8 y* S4 C! a1096356 ALLEGRO_EDITOR DATABASE Cannot Analyze a Matched Group in CM 9 `% S, }3 P: B! s. _. [/ t! ~1097481 ALLEGRO_EDITOR INTERACTIV Allow replace padstack command in design partition / N8 a% t4 b+ d/ }0 @1098252 ALLEGRO_EDITOR MANUFACT Double digit drill character overlaps with figure "circle" in NC drill legend ( ~8 s1 A& D% o4 H; i, o3 @1099958 ALLEGRO_EDITOR PAD_EDITOR Library Drill Report producing an empty report . y l: v' C& e k6 o7 g1100401 ALLEGRO_EDITOR OTHER Invalid switch message for "m" for a2dxf command + K! _2 }4 e% ^0 E6 t2 _1101026 ALLEGRO_EDITOR OTHER utl_perftune hanging in fpoly_RemoveVerySmallSegments(), causing shape degassing never to exit. ) l7 |: @2 V% |% W R1101064 SIP_LAYOUT SHAPE 'Shape force update creates a rat( s Q# i! ^1 X; m8 |" C
1102798 SIP_LAYOUT OTHER Stream out puts offset pad in wrong position if pad is mirrored but not rotated. 2 Z1 B7 a( X" M: c3 J( C$ P0 n - ^0 Y) ~; x8 T$ m1 m- MDATE: 02-8-2013 HOTFIX VERSION: 003 b) w( w7 g* ~( O0 }1 ]===================================================================================================================================5 L* a$ A! u+ H8 d% `; |
CCRID PRODUCT PRODUCTLEVEL2 TITLE - a0 u! d @$ ]* v) A: W===================================================================================================================================5 q! b& g( `. B* P
1077728 APD EXTRACT Extracta.exe generate the incorrect result & f% o+ [) [: v( w- ~& H1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF 2 ~, O$ U" \/ @ s( I) D3 f, z% o* s1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer . z/ g1 L# U$ C- W; j1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing. 5 J0 G) J9 U% j9 l5 g' y& }1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on 2 f3 ?# D" D* x1 k3 C( m) V1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent/ M) N" `; x3 ^0 b# X# m
1094788 SIP_LAYOUT WIREBOND Wirebond edit move command, m6 O5 ]) A7 }- q8 U
1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor S o) p1 k2 _, _* Y$ D& r
1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didn篙 show up after 燙uppress unconnected pads� option.+ O6 p A$ M3 M, J |" o
1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff8 J# C8 q- \/ I4 d
1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible9 S) w7 R. Q/ S# O4 n
1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35# i0 u6 p2 c: n" C: m8 b
1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component. ! f* u8 i5 t; j/ ]( B* g1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes.- B" a. u0 { F& q
1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license. 1 F8 e/ P! q5 ?& | W: E , E m6 D( \" d& U5 s4 a3 c$ PDATE: 1-25-2013 HOTFIX VERSION: 002( z+ V' r6 ]$ G* }- Z& ^' i; P
=================================================================================================================================== $ s4 P( K9 I" ^ J3 yCCRID PRODUCT PRODUCTLEVEL2 TITLE * U* `; m% b* H* K* T& x9 R5 ^& X=================================================================================================================================== w) _8 @8 w7 Y* j! i491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute1 A1 c- D* Y: S3 g E! U- `" x
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc" . f0 R+ X; L% b2 d) j. W1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes9 k2 z1 H7 h+ @) j' D
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable 0 a- B N7 K1 x: ^- O9 b0 B+ f& L1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33% x) B7 T a, Y! s. J+ D2 b% n. k6 B
1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence; e4 V! `6 l" E) K4 @2 N
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator ' K2 K, x# G7 P4 p: o$ k; b1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command; G2 E% X v W7 }' j
1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6: b/ S% ^' n' M$ Y
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note. " E& a0 U) n5 F* P! S) v1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.: }, L! |' _1 ~' l' n8 J- |
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL. 4 n3 Z$ L' k; F, r1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0 # Y. k* I$ j6 B2 N% @, O2 B1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white 6 ^3 D& H0 G) ], K# s; @$ K: p' l1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure ( [* {: w: W. _# U+ ~1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer0 \; D: O9 }% |% |
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.- a. Q# N+ _+ ~$ G& n/ C
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.# p5 U7 o7 [/ n& s8 F
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name. k3 _7 R1 B+ I' O) @5 w/ G; ~
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6 2 }% @# D: @. r% A: C y4 Z1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout 6 t* o, z9 ~0 Z; w9 b; C1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file- N7 H1 G( c# p7 Q: u1 d
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.5 X" J* A7 [( W; ~8 `& _9 b
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.* }0 r" G9 n$ C+ `
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties 2 S, ~2 z f0 l1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error 7 A0 h" [- q8 m$ {9 l6 `0 w4 f1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric: {8 T8 Y/ X* A* {* ~3 Q
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol. 3 z7 L5 \$ p; C# _! `1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue ; G! A) a6 `' `" B0 \; ^1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command" \7 k% O2 w/ u8 l4 f7 t
1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled % l6 I2 n) w+ _) W7 C% _ m2 H1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error; [$ p/ P) W( P' l7 J( N* W( {
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled. , e+ }$ X5 m- n4 I& R9 C- b1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function 5 @/ v9 H4 b* ]6 S1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.0 |8 |6 e3 h1 E% O
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?% a1 R3 }1 u, H( g# P
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group 9 W" B0 {3 J* v3 }3 Z3 ~1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle 0 B+ V- z v5 P; f: h- T1090689 ADW LRM LRM: Unable to select any Row regardless of Status # L& ^" ~0 T) a5 ~/ V* q4 a; L1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle. c8 w" k$ y' e; q* E3 {
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna� report seems to be missing vias that are antennas. ' c# `. k3 Y6 ^* h1091218 ADW LRM LRM is not worked for the block design of included project8 `, v C* i. q. w8 \) v. \
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads6 `. ]: C3 G7 E/ {( g: o
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width % ^( V9 c$ W8 Q& J8 q Q+ D L1092916 CAPTURE OTHER Capture crash5 ~* H7 H b( K/ ~& b3 B8 Q4 g
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database4 v% T! N# e0 w" ?
) a% K7 v8 W+ F6 \9 XDATE: 12-18-2012 HOTFIX VERSION: 001' w5 `; U, |8 D; }% B9 F
===================================================================================================================================- q% A* l3 x& C: S$ {' Y
CCRID PRODUCT PRODUCTLEVEL2 TITLE - P8 z% |! y0 k" V7 G===================================================================================================================================( w- u) ^' n. C4 \6 q+ S# l
501079 ALLEGRO_EDITOR MODULES Enhancement for Module swap function similar to component swap $ r: c" j }" K! g b745682 CONCEPT_HDL CORE Attributes window requires resizing each time DEHDL is launched. u+ b9 r) r, V* i' O
825846 CONCEPT_HDL CORE The module_order.dat file gets corrupted + d' b, ^: a4 N4 s8 c0 f; }$ q871886 CONCEPT_HDL CORE Browse button in Signal Integrity window of DE-HDL option causes program crash8 ^4 J+ i$ G# c5 _: K, {3 e) E
891439 ALLEGRO_EDITOR INTERACTIV moving cline segments8 R- v1 c6 @$ B) ?/ J9 N9 a
898029 CAPTURE PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore / r. G( O; m1 D% V8 b' `( k923210 CONCEPT_HDL CORE Search with multiple properties does not show all properties }1 E' G" \6 {% i/ _) @4 k) u938977 CONCEPT_HDL CORE Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic3 i5 [9 |$ L* a: F" q6 C5 S6 X/ w
947451 ALLEGRO_EDITOR INTERACTIV Allow the tool to select multiple shapes when assigning a net to more than one shape. 7 e: f' ]$ s- e' h968646 ALLEGRO_EDITOR EDIT_ETCH The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing- `8 s# r. j. v1 t2 ?
976723 ADW MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor , w- `; G S s981767 SCM UI Add series termination in ASA will crash if both output and input pins are selected. : c1 r& d& B1 S4 s$ M1 R982273 SCM OTHER Package radio button is grayed out 5 p- `# S9 a1 F) l6 P- G# d6 f. N* Y988438 CONCEPT_HDL CORE Visible constraint disrupts MOVE command 7 u7 t- O% c4 G989471 ALLEGRO_EDITOR INTERACTIV Functionality to zoom to the selected object in Pre Select Mode H+ G T! k# ^& z; _; q# f
993562 CONCEPT_HDL INFRA After upreving the design save hierarchy is leading to WARNING(SPCOCD-34). ! ?9 }% Q# R u( p$ }4 D996577 SPECCTRA ROUTE Specctra not routing NET_SHORT connections4 {9 L& p, X) c/ c# W
997992 CONCEPT_HDL CORE Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?: b) K" j5 w- z2 d: N8 ^5 r9 y
1001300 PSPICE MODELEDITOR BUG: Simserver crash with encryptedm model4 l4 l, G9 r' c
1010124 PSPICE SIMULATOR Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs 9 l# z8 k+ C0 H& {# [1013656 SCM OTHER create diff-pair should honour diff-pair setup or ask user for positive negative leg8 O7 r) {0 a% {+ c( i6 ]' S1 s# ^
1013721 ALLEGRO_EDITOR EDIT_ETCH Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.2 a& h+ B* u9 R
1016859 SCM REPORTS dsreportgen exits with %errorlevel%# [6 ?/ T: x* b& j F1 Q
1018506 ALLEGRO_EDITOR INTERACTIV Edit copy with retain net of via will assign net to pin9 t/ b- P/ [) o, R
1020746 CONCEPT_HDL OTHER PDF Publisher tool behavior inconsistent between OSs 2 p7 U; a; i" A- f1020798 SIP_LAYOUT SHAPE Shape not voiding on layer 2 causing shorts) \3 L7 \; |0 Q, e
1023051 SCM UI Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140 ( f+ d: v( x9 V& `1023774 APD WIREBOND After "xml wire profile data" is imported it isn't reflected to actual wire. 8 e$ C, M6 o! _ J1023807 SPECCTRA GUI Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button 5 S( s! W) v! J* y- [ O1024239 ALLEGRO_EDITOR INTERFACES DXF pin location is moved when I execute DXF out 8 r! x8 C' \/ ]$ U1028237 CONCEPT_HDL HDLDIRECT Error binding design when generating simulation netlist 9 N0 @3 d# k0 J' @. s# C" r, @1030591 CAPTURE LIBRARY Library Correction utiltiy locks the library and deosn't frees it even after being closed7 j7 w5 N. R: A3 c, M& I/ w9 U( d: f+ y
1035624 CONCEPT_HDL CORE Options pre-selected when launching base product 1 \ [; C! F( I2 y) I1035896 SIP_LAYOUT ASSY_RULE_CHECK Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly ' w3 c9 J0 a+ o. _5 l1036580 ALLEGRO_EDITOR MODULES Module created from completely routed board file has lot of missing connections in it. c1 z) r9 N- F* H0 j$ f1037345 ALLEGRO_EDITOR INTERACTIV Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file) ( E) X3 O. ^9 e4 [5 K2 ?1038180 ALLEGRO_EDITOR DRC_CONSTR BGA escapes not being calculated in phase tol * u, J8 k" H( N5 D8 O1038285 SCM UI Restore the option to launch DE-HDL after schgen., g2 R' `1 \9 s: X
1038371 ALLEGRO_EDITOR INTERFACES Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."' ~; W/ H. O& h
1038577 ALLEGRO_EDITOR DATABASE Modifying Void crashes Allegro1 b5 I; Y" w$ }. o
1039112 ALLEGRO_EDITOR ARTWORK Antietch and Boundary layers deleted when Match Display selected h: R% q; q- E1039147 ALLEGRO_EDITOR COLOR Need an option to change color of Text marker and Text select in Display listing( N$ }. R; `3 T+ [( ~, X; e
1040653 ALLEGRO_EDITOR DATABASE Cannot update netlist data, ERROR(SPMHDB-121): Attribute definition not found.5 H1 v; F! Z- |* i, j' \- c+ p
1041368 APD DEGASSING The Degas_No_Void properties assigned to Cline does not work. , F$ v* Y) i0 l# D1041864 ALLEGRO_EDITOR MANUFACT Allegro crashes when opening the Backdrill setup menu4 p: l5 I7 x. @+ l: M
1042199 SIG_INTEGRITY SIMULATION Waveform list was not refreshed by switching tab. - Q \' X5 R) V3 i2 F( _1042348 SIP_LAYOUT STREAM_IF GDSII export includes the full refernce path, breaks CATS flow ; @. @: \# z1 a' B1043861 SIG_INTEGRITY REPORTS Derating values are NA in bus simulation report when derating table is not in working directory ' v k& R! E- H, G3 T) M1043903 GRE GLOBAL This design crashes during planning phases in GRE. / A3 B+ [* `3 d( @& Q3 d1044029 PSPICE ENCRYPTION Encrypted lib not working for attached + d" o; C# _: Z+ O1 e/ P6 g1044222 ALLEGRO_EDITOR INTERACTIV Capture Canvas Image changes working directory / G7 w1 t4 q. B* p0 e1044264 PSPICE SIMULATOR Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.1 m! j$ K8 b; R+ w5 Y4 `: O# I
1044577 GRE CORE Plan > Topological either crashes or hangs GRE - [6 n' Z: k# O m9 v" Y1044687 TDA CORE tda does not get launched if java is not installed* W: @" e7 ]) R5 j& s4 H$ L4 x- |
1044754 SIG_INTEGRITY SIMULATION Incorrect waveforms when simulating with stacked die , Z# c6 Q! d6 g( s Q# t. b1045607 ALLEGRO_EDITOR OTHER Component get placed even after Cancel IDF in form.5 U2 ^' p& r" @( E
1045694 CONCEPT_HDL INFRA Why to package the design twice to pass the net_short property to the board? . U( E& c# D( Y) i2 g4 u' S, H1045863 CONCEPT_HDL INFRA Customer had the crash several times when they run script with SPB16.51. 9 t) r: i2 Y8 I! W1046929 CONSTRAINT_MGR OTHER Unable to create physical of spacing cset after rename the default cset in design entry.3 q- h* R' S4 U* f4 c
1047590 ALLEGRO_EDITOR SCHEM_FTB Buses created in Allegro-CM are deleted by netrev in traditional flow$ I5 r% P: Y4 b5 L4 u
1047823 CONSTRAINT_MGR OTHER acPutValue predicate text not being displayed at bottom of Constraint Manager window.5 ^$ {. V; t: H- z+ E
1048403 ALLEGRO_EDITOR SKILL Allegro crashes opening more than 16 files with skill 7 Z( J" ^4 V2 l) r/ |' f1049262 ALLEGRO_EDITOR OTHER APD and extracta crash owing to Wirebond. + t$ T( J: a" d1049303 CONCEPT_HDL CORE Block rename deletes schematic data immediately in 16.5/ P. A: u) T. D1 `
1049317 CONCEPT_HDL OTHER bomhdl with scm mode not working on RHEL in 16.5: w" f5 R2 x: j( E1 @+ t- B1 {! q
1049399 SIG_INTEGRITY OTHER Toggling z-axis delay in CM shows the same value 1 y. b3 H) R, C& x4 w- J% K$ u: H1049956 ALLEGRO_EDITOR DATABASE BUG:dbdoctor deletes fillets as design is migrated from old version1 Y9 c1 l; I$ J' J
1050408 APD DXF_IF Symbol has 45 degrees rotation in mcm but DXF doesn篙.& y6 N7 X6 M( R4 w
1050483 ALLEGRO_EDITOR DRC_CONSTR DRC has been waived but after updated DRC system generated a new DRC. ! @' i! f+ T! x: K+ Z1050918 ALLEGRO_EDITOR MANUFACT Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.# w3 ]0 Q5 o# u8 q
1051588 ALLEGRO_EDITOR PAD_EDITOR Pad_Designer library drill report omits some drill holes6 f) \# V4 g. f) Z9 L
1052005 SIG_INTEGRITY OTHER Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.0 @7 x9 g% u' o2 t
1052045 ALLEGRO_EDITOR OTHER Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3 5 n& v- @" W3 k- k6 ]1052449 CONCEPT_HDL COPY_PROJECT Copy Project does not update all relative paths in the cpm file6 f5 v# }+ `" p8 P" V$ b4 v
1052600 ALLEGRO_EDITOR SHAPE Adding a specific cline causing shape errors ; M" @' h A# [) ] y; w1052753 ALLEGRO_EDITOR DRC_CONSTR Allegro showing soldermask drc only when the symbol is rotated. - S0 W1 P+ k/ f9 N1054235 ALLEGRO_EDITOR PLACEMENT Cannot place alt_symbols for mechanical parts. 4 p! W, W1 y' |) h C: s! ?% `1054269 ALLEGRO_EDITOR MANUFACT Backdrill Setup and Analysis crashes on attached design0 }5 C1 c* i N! W
1054351 ALLEGRO_EDITOR SHAPE Shape voiding fails for board having diffpairs with arcs 3 i, j8 R1 Q5 F, ?! o1054456 ALLEGRO_EDITOR MENTOR mbs2lib incorrectly translates refdes label5 w/ D$ f- Q$ l
1055273 ALLEGRO_EDITOR INTERFACES DXF exported from Allegro has an offset in pad location for Y- direction. - D1 t- t |, z# i: |4 M1055328 CONCEPT_HDL COPY_PROJECT Project Manager - Project Copy; p% X5 {. \& J
1055481 APD SHAPE keepout does not clear shape unless it's picked up and dropped down5 ^# O9 b, L- @5 ~/ Q7 |
1055729 CIS GEN_BOM Standard CIS BOM per page is not working correctly with option Process Selection& N* O& O5 t& V q+ J3 Z: ~
1056418 ALLEGRO_EDITOR OTHER PDF exports the blank text markers whether or not the markers are visible. . I* ?* | ]7 B; I! \+ c1056579 CAPTURE OTHER Ability to define custom variables for titleblocks that update for specific variant views$ A, o: @ N7 B
1057003 ALLEGRO_EDITOR SHAPE Z-copy to create RKI does not follow board outline & k) B" L, L+ |/ D. |7 X% K' k1057976 ALLEGRO_EDITOR DRC_CONSTR No Same net Spacing DRC on attached design. , G0 Q% R/ x8 S7 L1 `1058002 SIG_INTEGRITY SIMULATION Incorrect Xtalk sim netlist was created.) Q+ S. q3 X% F# w& E
1058364 ALLEGRO_EDITOR SKILL axlTransformObject() is moving refdes text when only symbol pin is selected for move + k- T+ T) y: p f# Y+ Q1058940 ALLEGRO_EDITOR INTERFACES IDF(PTC) out command output wrong angle value# t: {2 g% i% O( ^; g
1059037 CIS PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer ( G$ ]3 `: }4 j+ Q% e( |1059389 ALLEGRO_EDITOR MANUFACT about back drill analisys report/ W( Y* G: C$ c/ e/ q
1059901 CONCEPT_HDL CORE Global Property Change and <<OCC_DELETED>> property value. ( N2 U- P' a2 Y# t& N v& z1060428 ADW DESIGN_INIT ADW Flow Manager Copy Project fails to complete5 D( d% b: y t
1060589 F2B PACKAGERXL Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties. ' L6 Q: m5 o/ r8 v7 {. z3 i; ?1060977 F2B DESIGNSYNC back annotate in 16.5 does not bring in already placed nets as global nets) Y! c/ A; C( @: j
1061223 CONCEPT_HDL CHECKPLUS What determines a passthru pin?' i) a# g2 z$ ?3 M$ V% r/ f
1061424 CONCEPT_HDL CORE Customer creates <<OCC_DELETED>> property values.; l% r" F4 J' l! L2 G4 I
1061572 ALLEGRO_EDITOR INTERACTIV Shortcut keys wont work after "Edit Text" command is finished.1 Z6 ~- n7 }' i2 B
1061659 ALLEGRO_EDITOR DATABASE Unable to return drawing origin to 00 & ]% |; }* a7 W, T2 l2 L1062558 APD DXF_IF If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation " R6 e% n* v0 v# |0 r1062982 ALLEGRO_EDITOR MODULES Module containg partitions has been imported to the main design and cant be refreshed.- x1 k& s, e, x8 u, z; E
1063284 PCB_LIBRARIAN OTHER PDV Save As is broken/ ?' B2 g3 u8 p# V. R
1063658 ALLEGRO_EDITOR SCHEM_FTB Allegro Import Logic does not remove library defined diffpairs1 c6 A" {2 W/ B4 M/ O
1063778 CONCEPT_HDL CHECKPLUS The hasSynonyms CheckPlus predicate is not returning true for all global signals.1 f/ }1 e6 r, `0 F$ i
1063924 CONCEPT_HDL CONSTRAINT_MGR Highlight the net between DE-HDL 16.5 and Constraint Manager.' B0 i( W) }/ g) p
1064707 CONCEPT_HDL CHECKPLUS Rules Checker core dumps on design 6 k! B" v9 O( q `1 |1065124 PCB_LIBRARIAN SETUP PTF properties cannot be deleted from the setup in PDV/ e% ]. I) W, f3 ?8 E% P4 c& D: F
1065618 CONSTRAINT_MGR ANALYSIS DRCs on board but Constraint Manager shows the columns as green. ' q! q$ B# d5 _0 {1 E& l! H1065641 PCB_LIBRARIAN CORE PDV symbol editor is crashing when deleting a group using delete or CTRL+X/ G& j0 y/ Q8 a$ C% _ l
1065745 SIP_LAYOUT DATABASE The logic assign net command crashes the application9 x6 ]* `( w: h9 d
1065860 ALLEGRO_EDITOR REPORTS Design crashes when running a padstack usage report , E% e l" U4 u( y6 }/ N: @1066051 ALLEGRO_EDITOR TESTPREP Auto Testprep generation creates TP with Testpoint to Component Locatin DRC 9 E9 K4 Q! W c. e, ? u1066318 CONCEPT_HDL CREFER Issue with LOCATION visibility in flattened schematic& T, {& d7 j1 \' ]0 @8 |# Z
1067339 CONSTRAINT_MGR ANALYSIS Relative Propagation Delay analysis in the Partition file seems very inconsitent.! @$ z( z1 T" S$ k5 @8 l1 b
1067984 SIP_LAYOUT OTHER layer compare batch fails with write protected file 0 K: O' o m2 C% v$ }7 d4 r8 O3 n1068425 F2B DESIGNVARI Out of memory message in Variant Editor while 盧hange properties� command+ O( b; h0 p* J( b+ V% Z4 U
1068547 ALLEGRO_EDITOR EDIT_ETCH Outward Fanout is not fanning out this 4 sided part as intended" H* A4 w& Q' j% J9 E' j
1068966 SIP_LAYOUT DRC_CONSTRAINTS DRC update aborts on this design with ERROR -3000067# F, W/ j5 B8 \
1069215 CAPTURE DATABASE Capture Crash on usnig a TCL utltiy to correct design 8 q5 q( d5 w( N; v6 l. ?1069517 SIP_LAYOUT DIE_EDITOR change die abstract pins tab default action from delete to modify1 x# r" `1 b3 G# ?
1069915 ALLEGRO_EDITOR EDIT_ETCH Allegro hangs with when doing spread between voids9 _3 u Y3 |& U4 y0 v
1070007 ALLEGRO_EDITOR PLOTTING Export IPF omits drill figure characters for backdrill holes & ]% m( J g1 I, g3 ?+ m( ]% }1071722 SIP_RF DIEEXPORT Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow# n! G6 M6 @, o+ y B8 E, `
1072067 APD EXTRACT When expoting using Extracta oblong pads with anyangle are abnormal : T5 ^4 v6 h6 _; _+ |7 ]4 {1072791 ALLEGRO_EDITOR DATABASE Database check cannot fix error and keep report the same issues cause artwork cannot export.- ^. I1 W: A3 J* j! ]/ S9 S0 P
1072806 CIS EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6 ~* o7 C5 u a' j4 |1072843 ALLEGRO_EDITOR PLACEMENT The move command that was present in the right mouse pop up menu during manual placement is missing in 16.5 / A% s% S3 ?: s) O7 a1072904 SIP_FLOW SIP_LAYOUT Probe pins not being mirrored in Die Editor correctly in Chip Down mode. 3 T. Q2 s* Z4 u! C. b8 ~$ H1 o1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation. Z: p5 ?* ?: @7 t3 Y5 [7 R9 b( T
1073445 ALLEGRO_EDITOR GRAPHICS 'infinite cursor graphics fail -ghost copies as you move cursor # P/ p" Y4 o! N2 I& a, |1073464 SCM SCHGEN Schgen never completes.5 l. A3 o8 A% t1 a. _+ R
1073587 SIP_LAYOUT OTHER axlSpreadsheetSetWorksheet command clears the cells in memory . A% `* Q7 i; Q$ a3 ]7 S1073745 CONCEPT_HDL CORE Import design fails ' w( y1 l8 B* W1 }, F' ^1 j$ s/ I1073852 ALLEGRO_EDITOR INTERACTIV While doing a Copy Via use the last 'Copy Origin' 2 B: R' d% i9 ^# {; J( a1074279 ADW DSN_MIGRATION Design Migration fails purge if there are cells with BODY_TYPE3 F6 [/ a" H5 @, h( f) _4 m
1074791 CONCEPT_HDL HDLDIRECT User gets port exists in schematic but not on symbol message even though the port does not exist: B! h0 O3 S' ?7 l8 `9 }/ Y4 T
1075135 ALLEGRO_EDITOR DRAFTING Ability to edit dimension text block in Instance Parameter 7 b' R/ c/ D F2 n$ l+ ]+ |1075151 ALLEGRO_EDITOR SHAPE Cannot change global shape parameter back to thermal width oversize after having used fixed thermal 0 ^9 @4 R9 A2 ]& i1075256 ALLEGRO_EDITOR OTHER Import > IPF in 16.5 is dropping data.! m7 O$ ^; m/ N9 N1 M7 T' v
1075853 ALLEGRO_EDITOR REPORTS please add "PART_NAME" at Extract UI % {' @0 ?& H5 i5 a' Y: w% B1075934 ALLEGRO_EDITOR DRAFTING Able to Changing Dimension Text Block ) f7 A. r( _# O1075955 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 using key "I" on keyboard in not centered on mouse pointer7 G; i- N$ n( g$ @/ `
1075964 ALLEGRO_EDITOR SHAPE Shape voiding is not consistent in conjunction with odd angle and arc traces3 c7 h7 M" M( D) c
1076086 SIP_LAYOUT IMPORT_DATA missing wirebond after import SPD2 ( a0 y; G H: f8 o L6 h# w- s1076202 ALLEGRO_EDITOR EDIT_ETCH Allegro add connect causing crash after Hotfix % e% M! a, n) l. `1076205 CAPTURE PRINT/PLOT/OUTPU : Printing of User Assigned RefDes! I1 s4 N5 i" a( r
1076536 ALLEGRO_EDITOR DRC_CONSTR Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top 0 N6 a/ `( O3 `& t, l3 w1076538 CONCEPT_HDL CORE Property visibility changes in attribute form not updated in schematic canvas. 2 q6 \" v, c6 b ~9 ]" f1076655 APD DXF_IF Dxf does not get offset value if die symbol padstack has offset value " ~% b- m8 @: w1076846 ALLEGRO_EDITOR EDIT_ETCH Grid snapping broken after slide in 16.6 % K1 s% M: z1 A! I2 z2 z1076891 ALLEGRO_EDITOR INTERACTIV Symbol rotation not displayed correctly when defined as a funckey ! U5 |$ p" a. b" O9 M1076909 ALLEGRO_EDITOR DRC_CONSTR Allegro crashes while placing modules from database; Y: t( \) E8 S( E! D1 T
1077084 CAPTURE NETGROUPS Crash on selecting bus when Enable Global ITC is unset & K0 G! s y/ k; V( N z1077169 APD SHAPE Shape > Check is producing bogus results.+ X g9 o+ F9 o( n
1077572 ALLEGRO_EDITOR DATABASE Mechanical symbol created with 16.6 cannot be placed on board. 3 n+ ]1 {9 C1 ]$ v1077879 ALLEGRO_EDITOR SKILL Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim ! a F( F- P, ~! b: ?* f9 `1078380 SCM OTHER Custom template works in Windows but not Linux0 X+ Y9 E" V; |! l+ N& ~, |: S
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly. - j2 l8 Q+ |. O! N. S) |1078682 ALLEGRO_EDITOR DRC_CONSTR Unaccetable slowness with Slide % p+ m( N( _; ~" w3 J9 w; o: Q: ]1079082 ALLEGRO_EDITOR PLACEMENT Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping e5 w8 Z: j( e' ^3 O
1079533 ALLEGRO_EDITOR PLACEMENT Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match" # s9 W! k8 d$ j% L `1079937 CAPTURE SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text2 r# j3 b2 y: A, M* _9 f) L
1082582 ALLEGRO_EDITOR GRAPHICS Allegro hangs on a given testcase using the MMB zoom control 9 Z( T" j$ W" U# I( X' u4 T1082981 ALLEGRO_EDITOR SKILL Allegro crash while change the new symbol type as mechanical.9 z2 O8 D7 A4 V- a+ d! H; r
1083230 SIP_LAYOUT SHAPE Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.. B# U) K8 w/ G, @3 W" V+ k
5 k$ }7 X4 e y" q' A6 K 作者: terry302 时间: 2013-5-27 22:22
多谢作者: wjl882008 时间: 2013-7-25 10:30
怎么出得这么快呀，看来BUG不少作者: inspiron1501 时间: 2013-7-25 12:57
已经到了bugfix 012
