剧透：DesignCon2013的获奖论文

stupid

1. A reusable generic platform for validation and characterization of high speed mixed signal designs

2. A rapid prototyping of FPGA-Based duobinary transmitter/receiver for high speed electrical backplane transmission
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! ~7 W' [- z9 `+ r/ o3. channel to channel crosstalk behavior and design optimization for ddr4 memory buses
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4. signal and power integrity(SPI) co-analysis for high speed communication channels

2 j1 A9 p3 i, }2 E( l9 D  |# w5. innovative PDN design guidelines for practical high-layer-count pcbs

6. Time domain and statistical model development,correlation,and analysis methods for high speed SerDes
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% a/ |/ }1 O6 c% u; X7. applying microwave techiques to digital systems: a simple case study

% c5 E# J0 @7 X/ Y8. high throughput,hign-sensitivity measurement of power supply-induced bounded,uncorrelated jitter in time,frequency,and statistical domains
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* n- \7 |) M$ c% z, @6 \) D5 J9. beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures
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5 V! U6 f1 _' z, g. I10. Memory interface on-chip PDN noise Charachterization,modeling and its impact on timing

+ f5 u* H, t% K' y11. Enabling DFT logic and timing verification in mixed signal designs
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% z, P8 C  Z! P( t9 e12. analytic solutions for periodically loaded transmission line modeling
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13. power-signal co-integrity design for multi-Gbps low-power DDR3 mobile platforms

; v  q; ]2 @! d- \: [- s14. power/Ground bump optimization technique on early design stage
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5 p) O. `; ~2 |- S15. DDR memory channel design from passive stub eqalizer perspective
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% A8 P' s0 ^! [16. using power aware IBIS v5.0 behavioral IO models to simulate simultaneous Switching Noise

17. validating EMC simulation by measurement in  reverberation chamber

: I3 P! ?' }6 Z& f+ @18. 3D interposer design and electrical performance study

19. Dramatic noise reduction using guard traces with optimized shorting vias

6 q% {& j( ?: M3 `1 L" q$ C20. effects of ground via asymmetry on mode conversion for high speed differential signals
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. D1 d3 j' ~8 l9 ?+ t+ X21. design and analysis of a high-speed parallel interface for coded differential signaling

& l6 Z, ?. Y2 c. ~) ^; |  h6 ]7 d22. measurement-based simulation:increasing IBIS-AMI model Accuracy with Data from lab measurements

23. accurate receiver clock positioning in high speed parallel buses
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24. partial response and noise predictive maximum likelihood(PRML/NPML) Equalization and Detection for high speed serial link systems
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25. Which one is better?comparing options to describe frequency dependent losses
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26. a reverse nyquist approach to understanding the importance of low frequency information in scattering matrices
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27. Terabit/s packaging design for testing of high speed IC transceivers

) ^$ r+ [8 R. a4 r% F" ?  X28. Channel operating margin(COM):evolution of channel specification for 25Gbps and beyond

（7楼继续。。。）

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frank2

技术无止境，慢慢看

stupid

chenqianwjkx 发表于 2017-3-21 05:51
5 N' ~/ m7 `! L$ u8 b2 W; p7 X想下载，不知道哪里能下到这些有用的文章

; t7 Y& B+ N4 Z! M本论坛就有下啊

chenqianwjkx

想下载，不知道哪里能下到这些有用的文章

2821462144

路过，了解，

qiye408

学习下，楼主V5

sleeper2008

只能看名字，还是顶一个

lpch8

分析的好，慢慢看吧。

stupid

0 k: V+ C  \2 b5 a3 a4 [& g1. A reusable generic platform for validation and characterization of high speed mixed signal designs
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Rambus 出品。

2. A rapid prototyping of FPGA-Based duobinary transmitter/receiver for high speed electrical backplane transmission

宾大和Agilent联手，Agilent方面是Mike Resso.
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3. channel to channel crosstalk behavior and design optimization for ddr4 memory buses
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  G* G4 [3 e, X# t# ~* yIntel，Xiang Li，DDR4连接器规范的制定者。

# M9 j2 ^7 V/ }: _4. signal and power integrity(SPI) co-analysis for high speed communication channels
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IBM美德研发中心联手。
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5. innovative PDN design guidelines for practical high-layer-count pcbs
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作者主要来自密苏里理工，其中Siming Pan 和Jun Fan都来自清华，后都就读于密苏里，俩人貌似有师生之谊。
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6. Time domain and statistical model development,correlation,and analysis methods for high speed SerDes
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LSI和Agilent联合，Agilent是Fangyi  Rao。
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7. applying microwave techiques to digital systems: a simple case study

( t3 E# u" F  M: a# f4 E8 mCray、SiSoft联合出品。
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3 H* ]; Y7 R! M' X/ z3 \8. high throughput,hign-sensitivity measurement of power supply-induced bounded,uncorrelated jitter in time,frequency,and statistical domains
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% ~& Z1 ?2 _1 u- H2 C) a0 BAltera出品，3个作者都是亚裔，其中大家熟悉的Daniel Chow，以及一位疑似华人Shishuang Sun。

. W" e& r/ A, V+ w4 C7 Y( a/ h  I9. beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures

LSI、TE联合出品
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10. Memory interface on-chip PDN noise Charachterization,modeling and its impact on timing

0 B7 _/ @/ z: n% L) k% {Altera出品，9位作者。

. H* d' |# ]" _" V$ c11. Enabling DFT logic and timing verification in mixed signal designs
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, F0 {2 x: M$ g) l6 z. iRambus和Synopsys联合出品。

2 m9 K5 P$ O6 L6 {12. analytic solutions for periodically loaded transmission line modeling
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Intel 和 Ansys 联合出品。
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13. power-signal co-integrity design for multi-Gbps low-power DDR3 mobile platforms

Samsung出品，目前似乎还没有用LPDDR3的手机，但是毫无疑问，这将会很快成为智能手机的标配。

1 M% ?" ~! R# \, l* }3 o14. power/Ground bump optimization technique on early design stage

Smasung出品。
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" ?% u5 s% G7 x1 H" N( ^9 i& l15. DDR memory channel design from passive stub eqalizer perspective
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, a3 l  W4 U  V; i/ j7 U7 V7 gIntel，貌似1位华人 Qin Li。

2 B- f# l: q; b" B: u" A5 X8 K$ S7 ]16. using power aware IBIS v5.0 behavioral IO models to simulate simultaneous Switching Noise
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Xilinx 和 Cadence出品，非常有用的SSN仿真文章。

17. validating EMC simulation by measurement in  reverberation chamber
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来自Cisco，作者中有4位华人，3位来自思科中国研发中心，分别是Xiaoxia Zhou，Hongmei Fan，Jinghan Yu
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) _% p7 R8 s0 v1 C* t18. 3D interposer design and electrical performance study
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Rambus 联合出品。

19. Dramatic noise reduction using guard traces with optimized shorting vias

# d8 [0 M7 T9 L' |: ?1 w& C4 x1 AEric  Bogatin和Lambert Simonovich联手
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20. effects of ground via asymmetry on mode conversion for high speed differential signals
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2 x: d6 h4 s# u3 |5 kIBM独家出品。

21. design and analysis of a high-speed parallel interface for 16Gbps coded differential signaling

' w7 C3 Q8 b3 uRambus、Samsung联合出品。

! ?$ D$ [/ \6 a. B22. measurement-based simulation:increasing IBIS-AMI model Accuracy with Data from lab measurements
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$ y8 a: s. t0 F5 F9 i1 j! jSiSoft、Ericsson联合出品。

23. accurate receiver clock positioning in high speed parallel buses

7 r6 D8 R7 g" ~2 H2 K, L9 k5 DRambus、Altera、xilinx、Qualcomm 联合出品。

24. partial response and noise predictive maximum likelihood(PRML/NPML) Equalization and Detection for high speed serial link systems

LSI出品，3作者中有一个中国人，Cathy Ye Liu，1995年清华毕业，后去了美国。

25. Which one is better?comparing options to describe frequency dependent losses

Eric Bogatin联合CCN，Simberian出品。
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0 z7 O: c; C# x& Z2 m4 y2 ~1 J; p. n26. a reverse nyquist approach to understanding the importance of low frequency information in scattering matrices

/ F. s; w" y' Z0 n  N5 H3 D% [1 a+ bAnsys出品
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$ I: q" @8 ]: K# Y3 @1 q! H27. Terabit/s packaging design for testing of high speed IC transceivers
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1 b/ D" ]1 p2 c( @+ S% c出自鼎鼎大名的IBM T.J.Watson Research Center，Xiaoxiong Gu是众多作者中的一位。
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28. Channel operating margin(COM):evolution of channel specification for 25Gbps and beyond

Intel、Altera联合出品，Mike Peng Li出手啦。

从今年DesignCon的获奖论文看，Rambus依然是论文大户，共有5片论文获奖，其中4篇是和别人合作。Intel 4篇，2篇与人合作。Altera 4篇。IBM独自贡献了3篇。 Samsung 3篇，一篇和Rambus联合，跟最近整个三爽的势头一样，表现的很猛。LSI 3篇。Agilent、xilinx、Sisoft都是2篇。多产的Bogatin博士，也是2篇。仿真大户Ansys这次只收获了1篇。 整机厂商，如Cisco、Cray、Ericsson则均收获了一篇。
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5 S! S6 ~. Y( g# J& h' z9 g密苏里理工表现优秀，乔治亚理工则没有收获。

* t7 I0 f1 c, [3 y8 X* e. U国内SI的领头羊，华为亦有论文宣讲，但未中奖。另外Qualcomm的有线部门开始发力，他们目前的重心应该在10G 以太网上。
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+ Y" N6 R3 ^- c/ [& B另外，几乎每篇获奖论文的作者都有一个华裔，从侧面反映出来中国人苦逼，到哪儿都是做民工的命，呵呵……

lpch8

非常感谢分享，那里能下载到论文，每年这个时候就期待。

understudy

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共享其中几篇SPI方向的文章：
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3、Channel to Channel Crosstalk Behavior and Design Optimization for DDR4 Signaling
! W5 q# u7 N3 C1 _+ ]$ ]5 z* ^4、signal and power integrity(SPI) co-analysis for high speed communication channels
5、innovative PDN design guidelines for practical high-layer-count pcbs
9、beyond 25Gbps:a study of NRZ and multi-level modulation in alternative backplane architectures

signory

如何下载这些论文？

dzgking

看到这些感到学无止境啊，叹自己懂得太少

wanily

很好的题目  能看个详细的就好了