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标题: 16.6 的 hotfix 出現囉 [打印本页]
作者: penny190    时间: 2012-12-17 12:49
标题: 16.6 的 hotfix 出現囉
{:soso_e100:}
2 y" s  q% V! v. H: v16.6 的 hotfix 出現囉 ~~ 14 Dec 2012 SPB16.60.001, Version: SPB:Hotfix:16.60.001~wint   
作者: longzhiming    时间: 2012-12-17 14:46
是不是16.6BUG多得受不了了?{:soso_e120:}
作者: haveok    时间: 2012-12-17 14:48
还在用16.5
作者: rx_78gp02a    时间: 2012-12-17 16:50
期待这个hotfix
作者: rasytc    时间: 2012-12-17 17:52
更新了神马
作者: sz_cheny    时间: 2012-12-17 18:18
求链接
作者: oostilloo    时间: 2012-12-17 20:05
ASI也可以下载了，Allegro Sigrity SI
作者: yueyuan2003    时间: 2012-12-17 21:13
本帖最后由 yueyuan2003 于 2012-12-17 21:14 编辑
8 y7 b, l3 ?* W; _( C0 B* e" W3 m! [) m3 w" {" o  U  @- A
别的地方找到的更新说明，其实干嘛老是跟着公司更新软件啊，我就觉得16.3挺好的，功能就很好了
8 e9 D8 u- L' }DATE: 12-18-2012   HOTFIX VERSION: 0012 P# H( O8 X8 v5 K* x8 A2 ^
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE% v$ k# Q4 F$ P- n
===================================================================================================================================
9 t3 W2 F3 e) i: `7 T% T; i501079  ALLEGRO_EDITOR MODULES          Enhancement for Module swap function similar to component swap
9 M* Y  c- r' c- |; _+ v. {745682  CONCEPT_HDL    CORE             Attributes window requires resizing each time DEHDL is launched
6 ~( z1 y7 d- B; Z, w6 e# I825846  CONCEPT_HDL    CORE             The module_order.dat file gets corrupted
! m: m5 m& L+ s' e8 q9 h% t! m! M871886  CONCEPT_HDL    CORE             Browse button in Signal Integrity window of DE-HDL option causes program crash% B8 \: k6 ?% x8 f" n" a
891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
3 N  O2 c6 C3 I) A! i7 [6 u898029  CAPTURE        PRINT/PLOT/OUTPU ENH: TCL:To show net alias clearly in print out if alias has underscore
9 g) u0 l) R/ e# |% y923210  CONCEPT_HDL    CORE             Search with multiple properties does not show all properties
, a9 ^1 F/ f: [# W" }938977  CONCEPT_HDL    CORE             Properties attached to standard/DRAWING symbol does not propagate to parts placed in the schematic
# @0 S& P* x  F8 C# o947451  ALLEGRO_EDITOR INTERACTIV       Allow the tool to select multiple shapes when assigning a net to more than one shape.
3 I* ^8 b* }% K+ p" y968646  ALLEGRO_EDITOR EDIT_ETCH        The Cline to Pad spacing not followed for Multidrill pad it is more then minimum spacing
9 l. c; E) @' E& z7 Q976723  ADW            MODEL_MANAGEMENT SI DML Model has to be provided the Auto Generate function for discrete components on DBeditor
6 G$ c0 g3 D3 x2 b5 L1 M; J981767  SCM            UI               Add series termination in ASA will crash if both output and input pins are selected.
3 b- Q& X$ B& c6 S- m- T982273  SCM            OTHER            Package radio button is grayed out9 |7 I% F' I- e. V$ g1 Z9 Y
988438  CONCEPT_HDL    CORE             Visible constraint disrupts MOVE command3 L, ?% P+ p" X  ~8 s% w! v% [
989471  ALLEGRO_EDITOR INTERACTIV       Functionality to zoom to the selected object in Pre Select Mode  l' u3 P" F  W* ]$ Y( _, n! u
993562  CONCEPT_HDL    INFRA            After upreving the design save hierarchy is leading to WARNING(SPCOCD-34)." L1 t. b) k( `9 B
996577  SPECCTRA       ROUTE            Specctra not routing NET_SHORT connections( x; J: ^, ]( s, \
997992  CONCEPT_HDL    CORE             Why are Page Numbers not enumerated correctly when multiple TOC Symbols are used?1 m6 K6 Y8 T5 Q, D" a
1001300 PSPICE         MODELEDITOR      BUG: Simserver crash with encryptedm model0 l$ e& A7 \3 ^. a% }5 k
1010124 PSPICE         SIMULATOR        Monte Carlo summary doesn't list all the runs in case of Convergence error in one of the runs
! c' N7 K- ?+ j# u* ^1013656 SCM            OTHER            create diff-pair should honour diff-pair setup or ask user for positive negative leg" {, z; t' m8 m4 F) m
1013721 ALLEGRO_EDITOR EDIT_ETCH        Routing near a 2x3 multi drill padstack does not maintain the spacing constraints.7 b0 Y8 w4 a1 I  D) C9 f0 q- K
1016859 SCM            REPORTS          dsreportgen exits with %errorlevel%
2 J( ?" M2 E( m4 A; P1018506 ALLEGRO_EDITOR INTERACTIV       Edit copy with retain net of via will assign net to pin
" I* v5 c, r) ~  F1020746 CONCEPT_HDL    OTHER            PDF Publisher tool behavior inconsistent between OSs
: U6 \$ W4 u* t" S/ C/ \1020798 SIP_LAYOUT     SHAPE            Shape not voiding on layer 2 causing shorts2 G& d( B7 z& j
1023051 SCM            UI               Wrong and incorrect message is generated while adding connectivity in SCM matrix view � DSTABLE-140
. j- [- [: _3 w' X4 e9 V* S1023774 APD            WIREBOND         After "xml wire profile data" is imported it isn't reflected to actual wire.
$ E# y! X% ~  B# s" w1023807 SPECCTRA       GUI              Unable to close SPECCTRA using File > Quit or by clicking on standard window red close cross button0 E7 E- R% t. b6 a1 Q
1024239 ALLEGRO_EDITOR INTERFACES       DXF pin location is moved when I execute DXF out
3 i" E0 M4 Y4 q  m7 Y3 C1028237 CONCEPT_HDL    HDLDIRECT        Error binding design when generating simulation netlist
1 L% c: ?9 C- ]$ s+ O$ _1 l" h1030591 CAPTURE        LIBRARY          Library Correction utiltiy locks the library and deosn't frees it even after being closed7 \5 ^) i, b6 M/ U/ U4 K
1035624 CONCEPT_HDL    CORE             Options pre-selected when launching base product; V1 e9 l2 j: g' r% x; m& c* y- @) F
1035896 SIP_LAYOUT     ASSY_RULE_CHECK  Rule Wire Length under Wire on line in Assembly Rule Checker doesn't work correctly
( t3 U) A) W( e, A1036580 ALLEGRO_EDITOR MODULES          Module created from completely routed board file has lot of missing connections in it.; J) b: o8 A/ P7 A6 |
1037345 ALLEGRO_EDITOR INTERACTIV       Enhance Allegro's Snap-To tools to select the origin of a sub-drawing(clip file)
- v- A& M7 X. w7 i+ D8 m1038180 ALLEGRO_EDITOR DRC_CONSTR       BGA escapes not being calculated in phase tol
+ V2 ^8 H% u- M/ J4 O( z1038285 SCM            UI               Restore the option to launch DE-HDL after schgen.
0 c2 ?/ S/ `" \- j1038371 ALLEGRO_EDITOR INTERFACES       Import > IDF fails with error "(SPMHDB-187): SHAPE boundary may not cross itself."
0 m$ B: F; {8 W0 H; M" L- m9 t1038577 ALLEGRO_EDITOR DATABASE         Modifying Void crashes Allegro
; A4 f% n( E0 B1039112 ALLEGRO_EDITOR ARTWORK          Antietch and Boundary layers deleted when Match Display selected
# b9 B( w7 W+ n1039147 ALLEGRO_EDITOR COLOR            Need an option to change color of Text marker and Text select in Display listing
3 S, S1 W+ l  U! e( m- u( i& Z1040653 ALLEGRO_EDITOR DATABASE         Cannot update netlist data,  ERROR(SPMHDB-121): Attribute definition not found.
* x# ]/ h% F9 x- ^+ j1041368 APD            DEGASSING        The Degas_No_Void properties assigned to Cline does not work.) [- L) X1 P# o& ]& l) p4 K
1041864 ALLEGRO_EDITOR MANUFACT         Allegro crashes when opening the Backdrill setup menu
8 A+ p  w, P$ y. m1042199 SIG_INTEGRITY  SIMULATION       Waveform list was not refreshed by switching tab./ s# m$ G4 Q, p
1042348 SIP_LAYOUT     STREAM_IF        GDSII export includes the full refernce path, breaks CATS flow
' C* {- a) G+ {0 [* y: l: ^1043861 SIG_INTEGRITY  REPORTS          Derating values are NA in bus simulation report when derating table is not in working directory
6 G/ U9 N& ]( K5 f# \8 Z1043903 GRE            GLOBAL           This design crashes during planning phases in GRE.  F+ {7 @& ^4 A1 D) c5 b8 w
1044029 PSPICE         ENCRYPTION       Encrypted lib not working for attached
7 x7 Z# m6 y# S5 |0 y1044222 ALLEGRO_EDITOR INTERACTIV       Capture Canvas Image changes working directory2 R5 J' e6 |: _* a) e0 b
1044264 PSPICE         SIMULATOR        Why does the 'ORPSIM-15009:This device scales to 0.0 at this Temperature' Error occur.2 }8 C1 y7 @0 k6 z
1044577 GRE            CORE             Plan > Topological either crashes or hangs GRE
: w0 g& A1 Y( A/ r2 U- l0 a1044687 TDA            CORE             tda does not get launched if java is not installed
6 _: m2 J' t" I1044754 SIG_INTEGRITY  SIMULATION       Incorrect waveforms when simulating with stacked die" ]/ N5 \: g5 ^- E8 z  I
1045607 ALLEGRO_EDITOR OTHER            Component get placed even after Cancel IDF in form.
7 p  Y) K: _  c* L) b; K- k$ K( I1045694 CONCEPT_HDL    INFRA            Why to package the design twice to pass the net_short property to the board?3 Y* o. D8 Y4 V: G
1045863 CONCEPT_HDL    INFRA            Customer had the crash several times when they run script with SPB16.51.! y) ~+ H4 R$ a
1046929 CONSTRAINT_MGR OTHER            Unable to create physical of spacing cset after rename the default cset in design entry.
; l+ y. T% k# ]% S1047590 ALLEGRO_EDITOR SCHEM_FTB        Buses created in Allegro-CM are deleted by netrev in traditional flow
* L9 x+ V! L( O# S4 L1047823 CONSTRAINT_MGR OTHER            acPutValue predicate text not being displayed at bottom of Constraint Manager window./ I; |4 l9 y; m/ H; j: v
1048403 ALLEGRO_EDITOR SKILL            Allegro crashes opening more than 16 files with skill
$ H$ y2 M4 d1 _1 n1049262 ALLEGRO_EDITOR OTHER            APD and extracta crash owing to Wirebond.
0 X' T) F, L/ E9 K5 a7 f1049303 CONCEPT_HDL    CORE             Block rename deletes schematic data immediately in 16.50 g2 D0 p0 W5 E; \* M  m
1049317 CONCEPT_HDL    OTHER            bomhdl with scm mode not working on RHEL in 16.5% S* V* d: e7 P. J6 d
1049399 SIG_INTEGRITY  OTHER            Toggling z-axis delay in CM shows the same value! M% Q4 V9 i$ t( n
1049956 ALLEGRO_EDITOR DATABASE         BUG:dbdoctor deletes fillets as design is migrated from old version
+ Z8 p2 y4 M3 V5 u# i: b/ X1050408 APD            DXF_IF           Symbol has 45 degrees rotation  in mcm but DXF doesn縯.
5 w/ G. _4 a' J0 y; u1 j8 A1050483 ALLEGRO_EDITOR DRC_CONSTR       DRC has been waived but after updated DRC system generated a new DRC.5 C+ V; F' }3 P. P
1050918 ALLEGRO_EDITOR MANUFACT         Testprep Automatic generate testpoints with wrong padstack Itype in SPB165S026.. l! c4 @% }, G) p8 ]9 d
1051588 ALLEGRO_EDITOR PAD_EDITOR       Pad_Designer library drill report omits some drill holes- _% g5 ?- n9 @  }4 g. r
1052005 SIG_INTEGRITY  OTHER            Huge difference in Z-Axis delay with the latest hotfix for 16.5 that did not exist in older ISR's of 16.5.# v+ E* f4 W8 `. p3 J' K- ~: M
1052045 ALLEGRO_EDITOR OTHER            Bug - Thermal relief connects not sustaining 15 degrees component spin in version 16.5 unlike v16.3
- K7 M/ G5 B6 B5 _) ~# ]1052449 CONCEPT_HDL    COPY_PROJECT     Copy Project does not update all relative paths in the cpm file; s3 O  s; M' Z$ A, c5 V9 s
1052600 ALLEGRO_EDITOR SHAPE            Adding a specific cline causing shape errors
: n* S3 s4 t" F+ E( }( r9 s1052753 ALLEGRO_EDITOR DRC_CONSTR       Allegro showing soldermask drc only when the symbol is rotated.
/ v* f6 V; w. r. _  `8 \1054235 ALLEGRO_EDITOR PLACEMENT        Cannot place alt_symbols for mechanical parts.% {, L! q# l% M
1054269 ALLEGRO_EDITOR MANUFACT         Backdrill Setup and Analysis crashes on attached design8 G5 `" p1 t4 m( p' @4 h
1054351 ALLEGRO_EDITOR SHAPE            Shape voiding fails for board having diffpairs with arcs
# h% G5 D) E$ q1054456 ALLEGRO_EDITOR MENTOR           mbs2lib incorrectly translates refdes label1 A* m8 v( N& b/ O0 {9 s7 f# v
1055273 ALLEGRO_EDITOR INTERFACES       DXF exported from Allegro has an offset in pad location for Y- direction.
* T4 z5 c. b# Z1 w# |1055328 CONCEPT_HDL    COPY_PROJECT     Project Manager - Project Copy
9 A) C' K2 W( ~" u- T' P1055481 APD            SHAPE            keepout does not clear shape unless it's picked up and dropped down
2 D  i8 i0 d1 |2 m( ~1055729 CIS            GEN_BOM          Standard CIS BOM per page is not working correctly with option  Process Selection* i; R+ i; v5 X4 l, H4 U
1056418 ALLEGRO_EDITOR OTHER            PDF exports the blank text markers whether or not the markers are visible.
8 V. @) J& N+ D2 ^4 `1056579 CAPTURE        OTHER            Ability to define custom variables for titleblocks that update for specific variant views0 H7 `8 Q- q, p
1057003 ALLEGRO_EDITOR SHAPE            Z-copy to create RKI does not follow board outline" T/ ?% N5 ~* w' H9 v7 I7 f! R1 T) F
1057976 ALLEGRO_EDITOR DRC_CONSTR       No Same net Spacing DRC on attached design.. T7 m3 I3 s/ D5 O( W
1058002 SIG_INTEGRITY  SIMULATION       Incorrect Xtalk sim netlist was created.% i$ ~5 c, K9 L
1058364 ALLEGRO_EDITOR SKILL            axlTransformObject() is moving refdes text when only symbol pin is selected for move
; M. Q& E% _8 \1058940 ALLEGRO_EDITOR INTERFACES       IDF(PTC) out command output wrong angle value
- K  b7 {/ y4 i7 n: R7 g2 ~1059037 CIS            PLACE_DATABASE_P What enables the Refresh symbol libs option under hte update menu in CIS explorer( q. c% ]& ^3 T. p  |  P
1059389 ALLEGRO_EDITOR MANUFACT         about back drill analisys report( U) O' k* _. p2 S
1059901 CONCEPT_HDL    CORE             Global Property Change and <<OCC_DELETED>> property value.
) U. k; m; @1 d: B3 S% d1060428 ADW            DESIGN_INIT      ADW Flow Manager Copy Project fails to complete% R) C' `5 i. s" k8 w( \% t9 n
1060589 F2B            PACKAGERXL       Packager Fails with ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties.
2 k2 G1 ^8 f- ]4 h& O2 s1060977 F2B            DESIGNSYNC       back annotate in 16.5 does not bring in already placed nets as global nets  ]/ Q/ Q: f- g! e/ _
1061223 CONCEPT_HDL    CHECKPLUS        What determines a passthru pin?
) z0 r2 q* A/ v7 E2 E; X( a' D' X1061424 CONCEPT_HDL    CORE             Customer creates <<OCC_DELETED>> property values.2 m6 d  M# Z8 ~9 I
1061572 ALLEGRO_EDITOR INTERACTIV       Shortcut keys wont work after "Edit Text" command is finished.
5 b) z5 b# d: r  Z# e& _2 _8 e1061659 ALLEGRO_EDITOR DATABASE         Unable to return drawing origin to 00
9 i' J' J. `7 |7 d- P1 c1062558 APD            DXF_IF           If set both in X and Y offset DXF only get one and not get absolutely value in 45 degree rotation
! n1 x/ E" _( x+ h; V1062982 ALLEGRO_EDITOR MODULES          Module containg partitions has been imported to the main design and cant be refreshed.0 N4 f+ `$ Q2 W$ E! V
1063284 PCB_LIBRARIAN  OTHER            PDV Save As is broken
+ ~$ b- t' A6 s' d7 Z# d1063658 ALLEGRO_EDITOR SCHEM_FTB        Allegro Import Logic does not remove library defined diffpairs# X0 J# b, I; m' R4 t
1063778 CONCEPT_HDL    CHECKPLUS        The hasSynonyms CheckPlus predicate is not returning true for all global signals.( G, Z2 g# `! V$ Q4 G- j& o/ \" V
1063924 CONCEPT_HDL    CONSTRAINT_MGR   Highlight the net between DE-HDL 16.5 and Constraint Manager.
- \9 y5 i  ~7 w% Z1064707 CONCEPT_HDL    CHECKPLUS        Rules Checker core dumps on design
$ C2 `  U+ s* P1065124 PCB_LIBRARIAN  SETUP            PTF properties cannot be deleted from the setup in PDV
4 h! V& @& C# V! ^; X1 y1065618 CONSTRAINT_MGR ANALYSIS         DRCs on board but Constraint Manager shows the columns as green.8 X- L: o% |# V  k( z
1065641 PCB_LIBRARIAN  CORE             PDV symbol editor is crashing when deleting a group using delete or CTRL+X& L' X5 T0 M* G' c  R
1065745 SIP_LAYOUT     DATABASE         The logic assign net command crashes the application2 q8 [# L3 J! ~7 w( M5 I; s
1065860 ALLEGRO_EDITOR REPORTS          Design crashes when running a padstack usage report5 T! M: i8 y* R4 `0 P
1066051 ALLEGRO_EDITOR TESTPREP         Auto Testprep generation creates TP with Testpoint to Component Locatin DRC
+ \* H5 N# w+ ^. q1 ]# \2 L9 p1066318 CONCEPT_HDL    CREFER           Issue with LOCATION visibility in flattened schematic
0 @9 _  \4 s: k  P, k5 W1067339 CONSTRAINT_MGR ANALYSIS         Relative Propagation Delay analysis in the Partition file seems very inconsitent.
  Y  c* D4 a: h5 M1067984 SIP_LAYOUT     OTHER            layer compare batch fails with write protected file
: R& H' M" O: C8 M! ~1068425 F2B            DESIGNVARI       Out of memory message in Variant Editor while 縞hange properties� command9 [( _9 S$ n8 P- {6 `8 ?
1068547 ALLEGRO_EDITOR EDIT_ETCH        Outward Fanout is not fanning out this 4 sided part as intended
0 A, f" M% g: w* w  {1068966 SIP_LAYOUT     DRC_CONSTRAINTS  DRC update aborts on this design with  ERROR -3000067: l% A, o1 Z; Q7 e3 _) j  T( p  p  X
1069215 CAPTURE        DATABASE         Capture Crash on usnig a TCL utltiy to correct design
  @2 A8 ?8 _) V+ ?) N. n1069517 SIP_LAYOUT     DIE_EDITOR       change die abstract pins tab default action from delete to modify. W) ]+ h% H/ b
1069915 ALLEGRO_EDITOR EDIT_ETCH        Allegro hangs with when doing spread between voids* c3 T" t8 z; v1 g+ O8 h6 X8 E
1070007 ALLEGRO_EDITOR PLOTTING         Export IPF omits drill figure characters for backdrill holes9 d1 y' E/ J9 r# z5 `3 x8 @* {- p, F
1071722 SIP_RF         DIEEXPORT        Virtuoso SiP Architect not writing out pins to the .dra needed for LVS flow
8 D; X8 T  E. ]& ^8 b2 s  \1072067 APD            EXTRACT          When expoting using Extracta oblong pads with anyangle are abnormal9 I/ B) v* X0 F: [
1072791 ALLEGRO_EDITOR DATABASE         Database check cannot fix error and keep report the same issues cause artwork cannot export.
4 Q- ?) ?0 h, ~6 L1072806 CIS            EXPLORE_DATABASE Query tab in CIS explorer doesn't show searh fields in 16.6
6 G( U& Z9 C3 R7 T/ p  ^; P1072843 ALLEGRO_EDITOR PLACEMENT        The move command that was present in the right mouse pop up menu during manual placement is missing in 16.54 b: y- v* c9 b& [
1072904 SIP_FLOW       SIP_LAYOUT       Probe pins not being mirrored in Die Editor correctly in Chip Down mode.
5 @+ X4 s; f( u4 S# l: j1073237 SIG_INTEGRITY  GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.1 @" ]- v" ^; V$ Y) d4 o6 Y3 ^6 z
1073445 ALLEGRO_EDITOR GRAPHICS         'infinite cursor graphics fail -ghost copies as you move cursor: F: a% c( V. B
1073464 SCM            SCHGEN           Schgen never completes.
8 ?- k2 J  S1 v; F1073587 SIP_LAYOUT     OTHER            axlSpreadsheetSetWorksheet command clears the cells in memory# g0 U5 A$ I: N  Q2 ~- v/ j! S
1073745 CONCEPT_HDL    CORE             Import design fails! f) ?( ]( G& L
1073852 ALLEGRO_EDITOR INTERACTIV       While doing a Copy Via use the last 'Copy Origin'3 E7 G- \- Z# _! q, g5 b
1074279 ADW            DSN_MIGRATION    Design Migration fails purge if there are cells with BODY_TYPE. [' M$ p. e* z8 @; g5 m9 V
1074791 CONCEPT_HDL    HDLDIRECT        User gets port exists in schematic but not on symbol message even though the port does not exist
. U* n9 \: [( i, L6 K$ s2 P' S1075135 ALLEGRO_EDITOR DRAFTING         Ability to edit dimension text block in Instance Parameter
+ x$ I+ K  l* z1 e- v( ]1075151 ALLEGRO_EDITOR SHAPE            Cannot change global shape parameter back to thermal width oversize after having used fixed thermal
- K+ J7 [6 w! _0 d8 ?) E4 A1075256 ALLEGRO_EDITOR OTHER            Import > IPF in 16.5 is dropping data.. e: {% ]% y1 E+ m/ i( w6 \- ]
1075853 ALLEGRO_EDITOR REPORTS          please add "PART_NAME" at Extract UI
% _8 ^1 }* q2 }% k( W1075934 ALLEGRO_EDITOR DRAFTING         Able to Changing Dimension Text Block
. Y5 k% v( g. g) p* G1075955 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6  using key "I" on keyboard in not centered on mouse pointer3 H1 }8 }  g2 r- v% }
1075964 ALLEGRO_EDITOR SHAPE            Shape voiding is not consistent in conjunction with odd angle and arc traces) z4 A+ B) x3 [0 v& c- ^
1076086 SIP_LAYOUT     IMPORT_DATA      missing wirebond after import SPD2+ s, w' X0 E0 ?& `; H
1076202 ALLEGRO_EDITOR EDIT_ETCH        Allegro add connect causing crash after Hotfix
, c8 d- B* M- }+ s) C( {( n1076205 CAPTURE        PRINT/PLOT/OUTPU : Printing of User Assigned RefDes
! r4 i$ R8 Q( [$ X. x( s1076536 ALLEGRO_EDITOR DRC_CONSTR       Embedded component which protrude out toward Top do not create DRC with Place Keepout on Top
; w  X5 a: n  y) P1076538 CONCEPT_HDL    CORE             Property visibility changes in attribute form not updated in schematic canvas., B% E- |: V5 Z. A
1076655 APD            DXF_IF           Dxf does not get offset value if die symbol padstack has offset value
# G+ |7 O, r. E+ |: J1076846 ALLEGRO_EDITOR EDIT_ETCH        Grid snapping broken after slide in 16.6
5 m% }* F9 h$ I. E1076891 ALLEGRO_EDITOR INTERACTIV       Symbol rotation not displayed correctly when defined as a funckey
. p9 S; f! n1 k1 w1076909 ALLEGRO_EDITOR DRC_CONSTR       Allegro crashes while placing modules from database
* ^; `/ L  }- W1077084 CAPTURE        NETGROUPS        Crash on selecting bus when Enable Global ITC is unset
9 B+ `) _2 G! r3 _6 M7 y% I1077169 APD            SHAPE            Shape > Check is producing bogus results.: p* d- o8 A) A
1077572 ALLEGRO_EDITOR DATABASE         Mechanical symbol created with 16.6 cannot be placed on board.; b* ^0 b  U$ V+ D5 h# B
1077879 ALLEGRO_EDITOR SKILL            Allegro Skill axlDBCreateFilmRec fails when 15th argument missing "draw hole only" for the first tim9 g3 k' d9 Y5 I$ [) v3 b
1078380 SCM            OTHER            Custom template works in Windows but not Linux
& k9 r2 X5 o: w  F' u1078497 ALLEGRO_EDITOR INTERFACES       Import DXF does not seem to work correctly.
; e* I0 j- F0 v% _% K0 \# J1078682 ALLEGRO_EDITOR DRC_CONSTR       Unaccetable slowness with Slide
, C7 t6 ~6 h* W/ p1079082 ALLEGRO_EDITOR PLACEMENT        Swap components, gives error SPMHGE-616, when symbols instead of components are selected for swapping
0 ~/ s% }( S) i  z1079533 ALLEGRO_EDITOR PLACEMENT        Swapping components in 16.6 results in Error "E-(SPMHGE-616): Symbol and layer embedding requirements do not match"; ]4 Z7 [; E' N0 j
1079937 CAPTURE        SCHEMATIC_EDITOR ZOOM in 16.6 is non uniform on text# H3 K3 f' G1 S- A; ^6 o& N
1082582 ALLEGRO_EDITOR GRAPHICS         Allegro hangs on a given testcase using the MMB zoom control% w. ?5 u! H2 J' i
1082981 ALLEGRO_EDITOR SKILL            Allegro crash while change the new symbol type as mechanical.  R' W7 K7 S6 D
1083230 SIP_LAYOUT     SHAPE            Shape fill in 16.6 releaase not fillilng shapes as good as it did in the 16.5 release.% w* r; F6 M6 l" f$ x
作者: rx_78gp02a    时间: 2012-12-17 21:16
看到了几个16.6的“特点“原来是BUG
作者: pcfg    时间: 2012-12-17 21:21
rx_78gp02a 发表于 2012-12-17 21:16 % V, a2 E* P- k4 y" p' l9 g
看到了几个16.6的“特点“原来是BUG
' u4 H* C8 N' B9 M! N
是的
作者: jinshan010    时间: 2012-12-17 21:24
有下载地址了吗？
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作者: MentorUser    时间: 2012-12-17 23:48
Look & Thanks
作者: mengshang    时间: 2012-12-18 05:32
本帖最后由 mengshang 于 2012-12-18 05:36 编辑 0 N& F8 \0 U# ]( ]5 V
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的确，Latest Release: 16.6-S0012 o) H# N4 @9 f) t3 O
Your Version: 16.5-S0340 ~- n8 w) \1 Q0 I3 l- @
期待着下载呢
作者: micdot    时间: 2012-12-19 22:59
本帖最后由 micdot 于 2012-12-20 10:57 编辑 4 S- S$ p8 I8 l" i# d) e0 \/ @6 D% Z
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现在提供下载地址：http://www.orcad.nl/patches/Hotfix_SPB16.60.001_wint_1of1.exe7 d9 L8 ~2 Z5 j7 X
目前，我已经下载完毕，安装后确认可以正常使用！
作者: rx_78gp02a    时间: 2012-12-19 23:13
第一个HOTFIX就有400多M，以后的会越来越大，这个怎么玩啊？
作者: ZXCLH    时间: 2012-12-20 08:54
收到，谢。。。。
作者: lae129    时间: 2012-12-20 09:01
谢谢楼上的分享!
作者: 南林维京    时间: 2012-12-20 09:11
出的真快
作者: rasytc    时间: 2012-12-20 10:46
没看懂更新了啥..
作者: x68049    时间: 2012-12-20 10:50
感謝分享
作者: sggh    时间: 2012-12-24 14:59
谢谢分享
作者: steven.ning    时间: 2012-12-25 17:49
升级后CAPTURE不能用了，PCB 可以
作者: larryfarn    时间: 2012-12-25 21:37
micdot 发表于 2012-12-19 22:59
% ~' s% \: I& {- l现在提供下载地址：http://www.orcad.nl/patches/Hotfix_SPB16.60.001_wint_1of1.exe
' ~& Q# x/ x: S& ]; G目前，我已经下载完毕 ...

% _+ q/ k, E! `) lGood job.{:soso_e179:}
作者: micdot    时间: 2012-12-28 16:57
larryfarn 发表于 2012-12-25 21:37
+ B5 s  s  v6 `1 yGood job.

+ s4 U& f0 Q8 P) `% N0 e. f1 w- K5 ?thanks！
作者: arsla    时间: 2012-12-28 17:57
升级后CAPTURE不能用了，PCB 可以 +1
作者: gdgdx    时间: 2013-1-9 18:38
安装补丁后破解后找不到license ,郁闷...
作者: 风飘雨摇    时间: 2013-1-10 16:00
16.6怎么样啊？好用吗
作者: levey    时间: 2013-2-4 21:21
链接好像不可以下载了。哪位转一下
作者: jokeyli    时间: 2013-2-4 23:32
16.5都hotfix30了



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