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标题: 秘密的事情，这个不要到处传哦，大家应该知道用法吧？你懂的 [打印本页]
作者: yejingang    时间: 2012-2-21 14:58
标题: 秘密的事情，这个不要到处传哦，大家应该知道用法吧？你懂的

2 T2 o: |% [! C! w2 \6 y: T7 xDATE: 02-17-2012   HOTFIX VERSION: 016' `/ {2 k3 `; `2 a3 J
===================================================================================================================================: @" B  d3 R. P3 i, k
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE7 U% {6 y( e- h2 ?& N
===================================================================================================================================7 Y+ r/ L# |. D) |; w
840105  PCB_LIBRARIAN  USABILITY        PTF subtype is getting changed when Save As option is used in PDV' I8 h; K4 [; q0 Y0 t$ S9 i$ E
873075  PSPICE         PROBE            Decibel of FFT results are incorrect.0 y9 |, T) ~3 Y, [9 X& C5 Q- A
938744  ADW            COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property9 Y# a  d9 l; c% e5 a5 W+ V: p2 s
943003  SCM            REPORTS          The dsreportgen command fails with network located project
- G( e" }& ~- S" |1 z8 @961530  ALLEGRO_EDITOR INTERACTIV       The problem of Display measure command# @3 F3 f' H: W# |) u* ^' W
962157  CONCEPT_HDL    CORE             Where is the setting for enabling the Enable PSpice Simulator menu?
% T: g4 I" p2 a$ D" F3 U1 O, h962206  CONSTRAINT_MGR CONCEPT_HDL      Import physical not passing all constraints from the board to frontend
  y! d2 m6 [+ t7 d968205  PSPICE         DEHDL_NETLISTER  Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.$ Q9 y# i% E3 l+ d! M
968509  PCB_LIBRARIAN  METADATA         Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS/NEG was set.' @6 U5 G( o2 g
969450  LAYOUT         TRANSLATORS      OrCAD Layout to Allegro Translator crashes) ?4 R; z# U- S% e  y- |" G
969997  CONSTRAINT_MGR CONCEPT_HDL      ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance pro~. U* R6 a8 ]& f9 K. J  B! j
971193  CONSTRAINT_MGR UI_FORMS         Copy and pasting a formula causes the application to crash on windows.
# L1 T8 ^5 H- g. R9 I* S1 @971601  CONSTRAINT_MGR CONCEPT_HDL      ERROR(SPCOPK-1053) and WARNING(SPCODD-66) because of directory structure# [; ^1 H8 n; k- w
973398  CONCEPT_HDL    OTHER            It should be not packaged with error while working the packaging process if the design has a ERROR; t) f' L$ x! L9 S7 ~6 l( B
973859  PSPICE         ENCRYPTION       Pspice crashes with encrypted model* [! a" e. a  Z- {& k5 c" z. |5 e3 p
973938  PCB_LIBRARIAN  VERIFICATION     pc.db is missing
( b$ N* j" n! B0 w. d- H974540  CONCEPT_HDL    CORE             Graphics updates are real slow1 @% |! ~" Z, T% n
974791  F2B            DESIGNVARI       Variants are not back-annotating to schematic and turning to ?
" L) a8 o& E0 m* g- @, c974818  ALLEGRO_EDITOR NC               Backdrilling produces 0 plunges yet no errors reported., o+ y/ u3 P- p# c
974945  ALLEGRO_EDITOR SKILL            Why is axlPolyOperation is giving different result and not working
6 Y! `) Z& t  z! t# @9 E) J7 b$ h8 q974946  MODEL_INTEGRIT TRANSLATION      ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology6 t( P" e' ~$ F  \; p* l1 S
975396  CONCEPT_HDL    CONSTRAINT_MGR   Constraints are dropped after migrating from 16.3 to 16.5
7 s! S6 f5 Z, T, B% o975633  ALLEGRO_EDITOR GRAPHICS         'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
3 _6 m" T4 y9 O975720  ALLEGRO_EDITOR DRAFTING         Datum dimension lines not adjusting to text move: j, A1 w$ \1 `/ R9 p* K  C0 N( ?
975745  ALLEGRO_EDITOR SKILL            cdsServIpc different 16.2 vs 16.5 when Allegro exits
. p! G7 }3 h3 N" o' b7 F2 V* w976013  CONCEPT_HDL    INFRA            Power pin connection of FPGA symbol is missing in netlist.1 E8 |! ?0 \4 q  d
976058  CONCEPT_HDL    COPY_PROJECT     SCM Copy project does not create the con and dcf files in tbl_1 views
6 |% d; {! s+ Z4 Y- P( d/ m976073  CONCEPT_HDL    COPY_PROJECT     All the constraint data is lost in the SCM copied design( b5 r8 T' a- N- P) i& U
976160  CONCEPT_HDL    CREFER           Cref fails due to some Caeviews error in the design
; u5 T4 @1 ]. [; [976204  ALLEGRO_EDITOR DRC_CONSTR       Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC/ i- }  V1 G! h! [% s, V2 f( y6 s
976448  F2B            PACKAGERXL       ERROR(SPCOPK-1069): Invalid POWER_GROUP property value. C. {, [2 [. ^- W6 q, d$ b
976521  ALLEGRO_EDITOR DRC_CONSTR       multi-thread update DRC causes the application to crash/ c$ z9 g0 z- d# x
976838  SIG_INTEGRITY  OTHER            Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.2 O3 w. ]2 k; A% l: L" E
977517  F2B            PACKAGERXL       Export physical fails after update to 16.5 from 16.34 \! M: Q# b6 X4 o* c; C& Q) E
977902  ALLEGRO_EDITOR DATABASE         generate module is crashing allegro
* G2 b2 ]9 K9 e% L" o978652  ALLEGRO_EDITOR PADS_IN          PADS_IN fails with ERROR: Finished with errors.
% F: I6 N  R/ x! q0 D978744  APD            DEGASSING        Some shapes will not DeGas on this design
+ ~6 e( r: l: q- X979940  SIP_LAYOUT     OTHER            SiP Layout Leadframe autobonding with profile selection
! ^! R2 K/ U- ^1 t2 L5 B981699  CAPTURE        HELP             Start Page still shows Hotfix 14 after installing Hotfix 15
2 z/ G0 S$ O, q9 c/ h. m5 m* ^
! B, j+ h; c/ S0 P4 h3 T; C. O1 C& |DATE: 02-03-2012   HOTFIX VERSION: 015; H4 ^8 L- P: U* J
===================================================================================================================================; z) @* J6 K" @1 Y- r2 {. A
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
3 W4 M6 w, S+ x; \2 [===================================================================================================================================2 I, e3 B  z7 Q3 |3 z7 A' u! p
871567  CONSTRAINT_MGR SCHEM_FTB        Ability to filter out Single Node Nets from Constraint Manager% |/ W. ~, m5 y# u$ G. F0 C" L5 q6 r
921436  ALLEGRO_EDITOR MANUFACT         Change in 'decimal place' for new dimension changes the already placed dimension
/ o3 X. Z8 J% o. L; t941433  CONCEPT_HDL    COPY_PROJECT     16.5 Copy Project should warn if trying to copy a 16.3 design
& \" e2 o# W% Q6 ~% d, b954375  ALLEGRO_EDITOR MANUFACT         Change dimension accuracy for few instaces of associative dimensioning. A: S# p# X; j7 [
961646  PDN_ANALYSIS   EMVIEWER         EMViewer Help > About shows wrong version0 V5 }0 R- Q  e+ i; g5 Q) f5 h
964912  CONCEPT_HDL    COPY_PROJECT     ASA project crash after using copy project
( |. K  d) o/ E1 ^967223  ALLEGRO_EDITOR MANUFACT         Bug:Oval slots orientation in one direction only
1 Q' A2 h. y0 G! P# `3 }968865  SIP_LAYOUT     DIE_ABSTRACT_IF  load of die abstract fails due to differences between component and symbol
' I/ Z: O9 L8 M3 j$ G969485  ALLEGRO_EDITOR SHAPE            Shape does not update correctly in 16.5" N, ~8 j; S  ]; {
970331  CONSTRAINT_MGR ANALYSIS         Impedance worksheet shows a zero value for impedance
6 |  b  f; l, A8 W4 L- ~7 d970600  SIP_LAYOUT     SYMB_EDIT_APPMOD Option in Die Editor to be able to "physically swap" pins  E) B+ U# k7 }4 H
970910  F2B            PACKAGERXL       Our customer has problem with pin color after pxl 16.5.
3 W# n3 B0 _' }/ i0 u; c# D3 s970970  SPECCTRA       FANOUT           Fanout Vias is placed far away from decaps and does not change the Fanout length even when max_length is reduced.
4 o/ K0 n% v, Y0 ~970985  SIP_LAYOUT     OTHER            Importing a .spd2 database file using NA2 will cause the APD/SiP tool crash8 {' w$ u3 t- u$ @! h
971757  CONCEPT_HDL    INFRA            Crash while Saving/Packaging the Design# ^  |) Z1 w& w+ g7 \
971923  ALLEGRO_EDITOR MANUFACT         Allow to change decimal accuracy for dimension instances( N) l* u: C0 E
972568  CONSTRAINT_MGR UI_FORMS         Tools >Excel missing from CM
* _# e6 w; [6 \8 C) \972821  CONSTRAINT_MGR CONCEPT_HDL      connectivity server warning: Unable to add property WEIGHT5 N) J# s7 ^* V2 }
973185  SCM            CONSTRAINT_MGR   ASA2 block not seeing all instances in a package.2 D5 m% v8 t3 X8 H3 z! c! G& m
973211  ALLEGRO_EDITOR INTERFACES       IDX Object Type Change not recognized, U1 n, _0 t+ D, J" L1 g
973214  ALLEGRO_EDITOR INTERFACES       IDX import package keepout height value change assigns incorrect value
, f8 R& z$ A1 m/ N973384  CONCEPT_HDL    CHECKPLUS        The multiple SIG_NAME has to be occurred an ERROR at the SPB16.5.
- G5 O. j# z: z' l8 H( y8 n973514  SIG_INTEGRITY  OTHER            Mapping error when Ecset is updated to constraint manager from extracted net
8 \% C/ V1 U# `7 [! A( o" N5 b973950  ALLEGRO_EDITOR SHAPE            Update to smooth crashes application
* Y( J2 K+ x" V974533  SIP_LAYOUT     OTHER            Crashes in Edit > Die Properties and obviously has a setup problem., A6 m' x* V3 m% a1 e0 Z: l
974809  ALLEGRO_EDITOR SKILL            argument available for hiding a property with function axlDBCreatePropDictEntry is not working) q. T5 L9 \# x9 m& [
976179  INSTALLATION   ISR              Installation of ISR S014 to 16.5 on windows is breaking the documentation index
$ q/ S+ y, v! N% W) t7 A9 K! r5 z  h* X4 a
DATE: 01-20-2012   HOTFIX VERSION: 014
7 q6 E" u& V5 o1 j+ c===================================================================================================================================% B% \  O: n; M1 R
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
1 z. e3 }3 |- b" R$ X# Y' b===================================================================================================================================  Q' |6 Q7 |" v# K
733285  PSPICE         SIMULATOR        Enhancement:In server-client installation use existing index file from server' c" ~( f# r. X
941020  SIP_LAYOUT     OTHER            Soldermask enhancement& J8 \2 E) U1 H; \/ b
946407  CONSTRAINT_MGR TDD              When is it safe to open a 16.5 design in 16.3?; `8 f0 H& v) I: f# o0 a* d! i  M  z
953067  CONCEPT_HDL    OTHER            Variant Editor "Error/Warning messages" form is unusable
  k9 v  E; c# R  G5 b954818  CONCEPT_HDL    COMP_BROWSER     Replace button turns to Add in component browser when a component replace is done on the schematic9 O1 k! h7 C" w8 C& X. D8 ]
956450  ALLEGRO_EDITOR DRC_CONSTR       Analysis always shows analysis failed in uncoupled length in some diffpairs0 C0 t1 r1 b, _, O5 x
958259  F2B            DESIGNSYNC       ds.exe crashes on a big design when accessing the design from network drive8 \( B5 B# f2 h7 j. {$ @# l  }$ W
958395  ALLEGRO_EDITOR SHAPE            shape voids won't merge
( O4 q2 `# v( x" w* N959212  MODEL_INTEGRIT PARSE            Attempting to use "Mark qualified" option on DML File results in dmlcheck and Modelsim wanrings.
4 a: b5 r8 {2 n959940  APD            AUTOVOID         Void all command gets result as no voids being generated.' [+ i% e" Y4 v( j# _1 \
960252  PCB_LIBRARIAN  CORE             Splash screen in PDV prevents showing error message5 p; S: r- ?3 ^  Z# D( [
961634  PDN_ANALYSIS   EMVIEWER         Cannot launch PDN EMViewer from withing PCB SI( e$ C( M( R! \9 M# `+ c% ?
961645  PDN_ANALYSIS   EMVIEWER         Standalone EMViewer will crash when opening any result file in the form of *.emv file.
* }7 I' l. d6 I: S8 n- W, w961700  ALLEGRO_EDITOR SHAPE            dbdoctor reports ERROR(SPMHUT-144): Illegal arc specification
" q( w. R1 m+ l6 p0 p9 u) o961733  ALLEGRO_EDITOR SKILL            Allegro crashes.  Appears to have a memory leak.* K: X3 ?* c9 V+ D! n! K5 f2 b8 Q" F
961758  ALLEGRO_EDITOR DRC_CONSTR       DFA check produces no DRC when the dfa bounds are not a rectangle.: g; Y7 f9 _) x" G# k- Y/ ]5 j
961887  CONCEPT_HDL    CONSTRAINT_MGR   Match Group created from ECSet cannot be deleted in the same session of CM
" p4 E* V/ g% L$ m8 q962552  APD            EDIT_ETCH        BUG:APD crashing when we try to slideget information but move works fine/ r. n  [) v, A- w
962869  CAPTURE        STABILITY        Capture crashes after RMB click on rotated parallel wires' L# l) v/ Y1 t8 m8 G$ K
963232  CAPTURE        MACRO            Macros not being played in Windows7
9 p6 l& B' C1 f" y; R963300  ALLEGRO_EDITOR DATABASE         Create > Module crashes in 16.5 but not in 16.37 w4 N1 O0 d6 J1 ^) `
963651  CONSTRAINT_MGR CONCEPT_HDL      ECsets are renamed after packaging on linux
5 a5 |# D2 M/ C% W! ]963663  CONSTRAINT_MGR ANALYSIS         Q- Why the customized worsheet for Diff pair Impedance not analysing at all for this SIP design
3 [% k+ |! R0 x- F8 \( @& \963715  SIG_INTEGRITY  OTHER            Application only adds the bottom conductor thickness for the via z-axis length) K- l2 ^4 g# [! _- Y- [. w
964068  ALLEGRO_EDITOR INTERACTIV       Allegro crash when using move alt sym mirror alt sym...
8 S( @0 Y: l3 I" q( y964267  CIS            PART_MANAGER     Capture become non-responsive, working on Part Manager and creating CIS BOM, for large designs8 w1 G: S+ K0 B1 q# _
964597  ADW            LRM              Issue of LRM license checkout after renewal license by 16.5 (ADW15.5_S23+SPB16.3)
, O  |1 t# ^2 E" L966148  APD            INTERFACES       Character Limit for DIE Files (*.die) Import% U/ L; N) w; U
966416  F2B            PACKAGERXL       Cannot package this design0 e+ l" ?0 e# J8 H$ j8 h. n5 M  L
966421  CONCEPT_HDL    CORE             DEHDL Crash when applying property on components in duplicated blocks& X! Q6 v% I, G2 b
966693  CONCEPT_HDL    CORE             DEHDL crashes when doing model assignment if CM is open, }% \1 r! F, z$ p0 c8 M" T
966795  ADW            ROLLBACK         rollback utility does not honor -product option from command line
) j0 f' a- Y. t- u1 @$ L% O* x# y967089  SIG_INTEGRITY  OTHER            Matchgroups created by ECSet not deleted when ECset is removed from object.
) {; i+ X3 b) h967222  ALLEGRO_EDITOR OTHER            PDF export is leaving data off the drawing3 m( K% S/ Q# m  N( p
967240  SIP_LAYOUT     WIREBOND         Change default bond fingers selected on multi-site leads during "bond to leads" program6 W' M4 I" k% ~7 R9 r# w) z% U, I7 X
967297  ALLEGRO_EDITOR OTHER            Dynamic Fillet&Eliminate unused stacked vias cannot be used as the Miniaturization option.
0 Q" @9 {: T" L! ^967576  CONCEPT_HDL    CREFER           Occurrence location property values do not appear in flattened schematic generated by CreferHDL
2 T, d! ~% |1 E9 h968096  ALLEGRO_EDITOR DRC_CONSTR       Mechanical Pin to conductor spacing is not followed.. ?$ @6 x. M7 p8 K; j" Q+ d
968222  SIP_LAYOUT     DIE_EDITOR       die pin loses IC net for a co-design die with multiple ports within IO-cell
, k0 U6 j7 V1 o# q3 `" ~; K* A8 i) r968358  CIS            PART_MANAGER     Capture crash on removing a part from subgroup in part manager
& C+ K$ S% r' k7 x969594  CONCEPT_HDL    CORE             The dcf file is not updated with schematic changes* [" p, q' U5 O% t

5 J) X% n- w9 G. wDATE: 12-16-2011   HOTFIX VERSION: 013
6 j: n$ A$ U1 k: C! ]===================================================================================================================================/ y8 w2 u7 y! F2 K' p8 P5 P
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
" A% H  U9 e# l===================================================================================================================================3 B7 j9 r5 H" i: \8 Q+ J
875695  SIG_EXPLORER   INTERACTIV       Enforce Causality check box doesn't work.5 K2 ^3 }& W# _; {6 R& B6 m
927148  CAPTURE        PROJECT_MANAGER  Capture crashes on creating scehmatic folder with name which already exists in design
. I( ^& Z/ i7 ]+ |  u' ]0 p6 b938013  CAPTURE        NETLIST_OTHER    The netlist in RINF Format contained two identical lines for PCB FOOTPRINT
7 k2 {' c$ N: b1 {4 D0 Y# S0 F- o941409  PSPICE         PROBE            BUG : Search accuracy wrong in new cursor window
3 W- y) R% x% u5 Z0 d9 |: ~945242  SIG_INTEGRITY  SIMULATION       Unable to select "shapes" in find filter for 'show parasitic ' command# V2 U0 U1 Y1 I/ ~
946293  CONCEPT_HDL    ARCHIVER         Archiver hangs if there is a whitespace at the end of the path of cref.dat
2 @8 P0 P& ]# B8 a9 {4 S946770  CONCEPT_HDL    CORE             揤iew Design� function is missing in Windows Mode after reseting the menus.
. t: i$ M3 \- \% N' q. N950994  CAPTURE        NETGROUPS        Problem in expanding the netgroup in Auto Connect to Bus function
4 ^* k- u8 }) P( x2 I! E953530  SIG_INTEGRITY  GEOMETRY_EXTRACT Display Parasitics is displaying wrong results for EMS2D Field Solver compared to topology extraction using Probe.) y6 a% D: r. w& \' k  K
953713  CONCEPT_HDL    PAGE_MGMT        Random page replacement/duplication in block& k1 g8 x0 H2 ^; i8 V
953917  CONCEPT_HDL    ARCHIVER         archcore should handle errors correctly
; r: o  N+ [- g5 k- B: e% I953971  ALLEGRO_EDITOR MANUFACT         NC Drill files not generated correctly when using the option "搒eparate files for plated/nonplatedholes�- E3 v- z" z. W) a5 t
954400  CAPTURE        NETGROUPS        BUS members of NetGroup are getting converted to Scalars in Export-Import NetGroup.: l8 Y. ~7 z$ Q  \5 o
954498  SCM            B2F              SCM crashes when importing physical
4 B) v, c0 m; k2 p+ `: n954623  ALLEGRO_EDITOR EDIT_ETCH        Unable to complete connection with Add Connect - related to soldermask to cline check?
& k! U, e, p# ?4 a954894  ALLEGRO_EDITOR MANUFACT         Dimensions disappear when opening database in v16.5 from v16.3
# v% b7 Y( a  W# r$ C9 i955029  CONCEPT_HDL    CORE             custom text font size not recognized in symbol view- X  c0 U: A( ~/ p( U
955133  SIG_INTEGRITY  FIELD_SOLVERS    The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.- U( p3 q' }3 j) H
955290  CAPTURE        DRC              Description for UPD0014 missing in the Browse DRC markers window
% D7 J" j4 L6 `/ s; M+ k( X( ~955299  ALLEGRO_EDITOR DRC_CONSTR       drc text to smd pin does not work any more on this database in 16.3 S039
) O- g  |/ z7 y# F955338  CONCEPT_HDL    CHECKPLUS        Need to change PART_NAME
: X. a/ G/ r, g+ \8 O7 g955447  SIG_EXPLORER   OTHER            Model path set in DE HDL Model Assignment not used by SigXP from CM in DE HDL) R( Y+ E9 e" _! f9 s7 P7 p0 k
955740  SIG_INTEGRITY  GEOMETRY_EXTRACT Crosstalk with Timing Windows does not work correctly
( B, O/ F( v# m9 ^4 P* B955749  ALLEGRO_EDITOR MANUFACT         show element Info shows symbol dimensions on incorrect subclass
& Z+ N- _+ D9 r1 k8 Y' d; t9 K7 x955912  ALLEGRO_EDITOR OTHER            Shapes with voids that are exported to PDF have gray filled area over the void' m3 ~. s6 _' k
956129  CONCEPT_HDL    INFRA            DEHDL uprev hierachical design from 16.2 to 16.5 packaging failure., c& Z3 u/ R, ?0 g2 Y
956373  ALLEGRO_EDITOR NC               drawing name doesn't display in the log file
' v- F7 N2 i- s; w& W956393  CAPTURE        PROJECT_MANAGER  "GENERAL" and "TYPE" tabs are missing from "roperties" dialogue box.
1 ]& @3 V( F- J5 R6 m: H* ^- C6 _956448  PSPICE         MODELEDITOR      Can not generate a DEHDL symbol from Model Editor, because no Capture license found* |' s3 u2 [. G1 y' q+ J- u3 P
956456  CAPTURE        NETLIST_OTHER    OrTelesis netlist not transferring user properties defined under combined5 _8 q/ m9 N( ]& }5 j+ V2 j
956489  ALLEGRO_EDITOR MANUFACT         dimensions lost when symbol with diemnsions attached to symbol origin placed on board5 p5 `4 n* L/ m" |8 W
956603  CONCEPT_HDL    OTHER            Part Manager "has stopped working" after changing a component) H, C& Q0 U4 c8 M7 k* ~$ O3 y
956751  ALLEGRO_EDITOR ARTWORK          Import Gerber command does not work correctly
( _' K) ?% I' v; V; d* v0 B956847  PCB_LIBRARIAN  METADATA         PDV - Partdeveloper symbol to function linkage broken/changed in 16.5
9 b/ I8 {$ J3 @0 `* J956987  CAPTURE        OTHER            Find from "Search toolbar" doesn't gives complete results
7 R; Z3 Q) s6 x  K956996  CONCEPT_HDL    INFRA            Correction to ERROR(SPCODD-7): Following Primitive instance causes CM to empty
0 m1 z9 R8 R0 Q1 w( L' G957009  CAPTURE        NETLIST_OTHER    Problem getting database property in Mentor PADS PCB netlist0 J8 R& f$ ]3 ~) R
957137  APD            DXF_IF           DXF out  command dose not work correctly.
8 m; b3 L1 k6 C4 j3 Z! G" k957167  APD            GRAPHICS         Highlighting for Static shape with display_nohilitefont environment variable.
9 R* Y* j4 R# `% C# j957232  SIG_INTEGRITY  OTHER            Allegro crash during Model Assignment.
, O0 h# S' x. ]/ n957267  CONCEPT_HDL    INFRA            Packager Error after Import Design) T- ]2 n& z! ?+ _  \2 i+ H
957866  SIP_LAYOUT     DATABASE         Cavity outline is not getting deleted from symbol file
% D1 i# n9 x. a' j. A4 I" D958010  ALLEGRO_EDITOR REPORTS          Wants the ability to extract "Batch"  reports from Partition ".dpf" files.
- @* |- }( }; S' r+ F, g9 Y% |4 x958252  ALLEGRO_EDITOR TESTPREP         Resequence testprep with the option - Delete probes too close crashes the design- c# X& A" m  \; h; X8 N4 u
958253  ALLEGRO_EDITOR REPORTS          Shape did not have thermal relief connected to pin but unrouted nets still shows zero.* _8 |- x1 G  E. [4 I4 ~3 X
958433  ALLEGRO_EDITOR DRC_CONSTR       False embedded component DRCs5 |; s9 ]. c7 u3 z' Q) {
958753  ALLEGRO_EDITOR SHAPE            Dynamic shape is getting corrupted in 16.5
: U; E" }3 Y! @6 V959011  ALLEGRO_EDITOR OTHER            copy problem of via and cline* `) v* f. ?: P
959101  ALLEGRO_EDITOR EXTRACT          Using extracta with excluding Thermal reliefs
4 K6 }+ a7 J: h  c6 r' N959253  CONCEPT_HDL    INFRA            Design will not open# E# h4 O& Z7 Z3 h9 S  q
959299  APD            MODULES          Getting ERROR(SPMHDB-279) when trying to update modules placed on the Top side( t8 R2 p, v8 H: l6 z5 l) s
959884  CONCEPT_HDL    INFRA            Design Uprev/concept2cm crashes with Application Error/Out of Memory Error.
( s7 R6 m) a+ R959909  ALLEGRO_EDITOR SCHEM_FTB        Site level propflow.txt file is ignored property is transferred  s% f3 a3 q: [5 X  R& X
960067  SIP_LAYOUT     PLATING_BAR      Creation of plating bar removes "NODRC_ETCH_OUTSIDE_KEEPIN" property from the clines.  b; Q- S3 n+ Y3 j7 E
960126  SIG_EXPLORER   EXTRACTTOP       Allegro PCB SI license is used automatically at Topology Extraction of Allegro Physical Viewer.
; s: c* c( d. T: x) k5 U( z: \960143  SIG_INTEGRITY  GEOMETRY_EXTRACT Running simulation in Bus sim happened crash while enable Coulpled Via model to S parameter% ?; H( q6 [/ C9 \
961349  CONCEPT_HDL    HDLDIRECT        Motorola designs have broken connectivity compared to 16.3  ^( h6 c# ^2 @, l
961816  ALLEGRO_EDITOR INTERFACES       Normal Export > DXF fails and offsets  the pins of the BGA symbol
! W% Z7 C( }9 A4 [# B: }; x0 I; {962519  SIP_LAYOUT     WIREBOND         Align option doesn't work for wb_tackpoint fingers# s- J5 H/ i* o4 {1 S

5 |9 V  F: e, }# A; vDATE: 11-30-2011   HOTFIX VERSION: 012
3 M9 r! x. n8 o3 |+ b# V# D% m& S===================================================================================================================================' C6 w8 h+ R  J! ?
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
" S. v# }7 d$ E& a( E/ J===================================================================================================================================) O& ]2 o& J4 B* U6 ?
959581  CAPTURE        NETLIST_OTHER    PCB Footprint is getting replaced by VALUE in OTHER netlist formats+ v9 o' O6 M8 Q2 q8 s$ N
3 ?$ e* u9 _6 F
DATE: 11-18-2011   HOTFIX VERSION: 011- j+ j/ D5 d' y2 i- o, |9 O
===================================================================================================================================
  ~5 w: L8 l' Y4 `  RCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
/ e8 X- a6 ]2 K# {1 B$ y===================================================================================================================================5 {9 M5 @- o# @9 y9 }
735439  PCB_LIBRARIAN  CORE             PDV Moving line-dot pinshapes by arrow keys breaks the pinshape
, o2 S2 i* M) Y894815  CONCEPT_HDL    COMP_BROWSER     Why does genlibmetadata command give 'Aborted $PROG' Message?
5 C: w1 T& L) M+ r5 M, ]903073  ADW            COMPONENT_BROWSE datasheetl_url directive should support a display string for URL
  G7 ~2 p" |/ ]909919  CONCEPT_HDL    OTHER            Why is the PublishPDF UNIX command line looking for "true" script?
" a. D7 u/ V  h6 {6 {911561  CAPTURE        CORRUPT_DESIGN   Capture crashes on trying to save the design.
% m- Z( h% }7 U2 d4 U919579  CAPTURE        PRINT/PLOT/OUTPU Print mode be selected based on schematic mode' M6 j; z% W/ s+ r7 V% p9 k
921247  CONCEPT_HDL    COMP_BROWSER     genlibmetadata.bat file does not have err defined
  D) K9 e& |' E+ U) F' W# u' y925182  CAPTURE        PROJECT_MANAGER  ENH: Feature to run update cache on all the parts in design cache at once.) ~- }% \# q- {9 s, m* o$ M+ {3 ]
926858  CONCEPT_HDL    CORE             Usability- Modify Component dialog forces user to do 'Reset Filters' to see other ppt rows
/ i( i5 l8 g8 A927657  CAPTURE        NETGROUPS        Enhancement: Placement of netgroup definitions under design cache list" _, N% z6 G+ k# s# |! q4 w, e
934684  ALLEGRO_EDITOR MANUFACT         The relation between the linear dimension and the symbol breaks.
" z) o$ k6 c: R0 p+ P935836  SCM            SCHGEN           ASA crashes when generating Flat Document Schematic
, I8 D+ r2 S2 z  X5 q& P937165  SCM            SCHGEN           Can't generate Schematic
1 d' M9 r5 a2 a0 D- }- S3 h937292  CAPTURE        GENERAL          Memory usage keeps on growing and finally gets exhausted while search* n3 y! `+ O2 I) a0 h, W% z
937322  CONCEPT_HDL    CORE             Master.tag file alters the sequence of the files and Genview fails" X8 o4 C6 ~8 J  p2 X& x
939135  CONCEPT_HDL    CORE             Unable to uprev a 16.3 Design to 16.5 with DEHDL-L License0 q9 U: B# e$ Y9 e4 E" V: h' C
940373  CAPTURE        TCL_INTERFACE    Enhancement: TCL command to add nets to Netgroup  n& L% g. J3 [" E
940547  TDA            CORE             ERROR(SPDWSD-69): highspeed cannot be checked in
1 E0 ~& e4 _4 ?940607  SIG_EXPLORER   OTHER            Inconsistancy in License usage for opening sigxp -orcad; a' e# X$ g/ Q! K  f
940790  F2B            PACKAGERXL       User doesn't want to display pin numbers after Export Physical 16.5.
& Y% g- p( u$ \3 B% M5 s' g940944  SIG_EXPLORER   OTHER            Inconsistant license usage while opening Orcad PCB SI using allegro -sq -orcad and allegro -sq
0 a, I$ P' S' B1 ?941354  CAPTURE        NETGROUPS        Enhancement: Option to rename the unnamed NetGroups
: Q5 f: O8 ]2 c* C$ j941455  ALLEGRO_EDITOR MANUFACT         The Dimensioned mechanical symbol when placed in the board does not show all the dimensions.
' `' U! z( Q0 L. g3 O4 K941863  ALLEGRO_EDITOR EDIT_ETCH        Different behavior of design in v16_3 & v16_5 when add connect is executed on a segment thru script; C( Q2 Q  }, E9 ]
941881  CONCEPT_HDL    COMP_BROWSER     How can I suppress the dialog from universalbrowser -genlibindex?  @; B1 o+ w3 k2 q
942474  CAPTURE        NETGROUPS        NetGroup member type of last added member must be remembered by Capture3 J2 V1 d0 g4 Q+ H5 O( O4 G
942522  CAPTURE        GEN_BOM          Export in excel check mark doesn't invoked BOM in Excel
! _9 s2 k0 P& Y# g: f2 E7 F942557  PCB_LIBRARIAN  EXPORT_OTHER     PDV Export to Capture crash
6 E0 o. s) @, g0 L( D# B* F  n942569  ALLEGRO_EDITOR MANUFACT         Dimension  move and change  text deletes leaderless balloon
2 w& ]% [6 Q' g942573  ALLEGRO_EDITOR MANUFACT         Balloon type parameter  has no effect on leaderless balloon.
" u) @! B8 @* C( Q- C  m+ o942613  CONCEPT_HDL    CORE             Genview supports only SCHEMATIC/SYMBOL/VERILOG/VHDL views as input type.  .xcon not recongnised7 C# H) w9 @' c* x: p; }6 @
943032  SCM            OTHER            ASA is not passing the correct reuse_module name to Allegro PCB layout.* h. q2 ]  A5 W4 ^# v
943401  CAPTURE        NETGROUPS        Alphabetical ordering of NetGroups in Place NetGroup" R9 f2 m* S( X9 i( M4 [# S
944006  ALLEGRO_EDITOR EDIT_ETCH        Vias added to shapes behave differently
- U$ {. x) x0 @$ B( x944367  CONCEPT_HDL    OTHER            Too late to do Model Assingment in conceptHDL 16.5
  \0 C. v5 ?/ J; `* X. F, X4 O944788  ALLEGRO_EDITOR GRAPHICS         Oblong Pad shows unexpected lines9 v$ |2 M8 o. P3 i- w% v! K( p5 V
945221  CONSTRAINT_MGR RETAIN_CNS       CM Conflict Resolution fails on more complex designs using ECSets and constraints
7 V3 s, b1 j' {9 w+ l946270  ALLEGRO_EDITOR PLACEMENT        The Rotation Type was changed to "Absoute" if the "iangle 90" use at placementedit mode of spb16.5
! r" {6 x- _+ _  T946350  F2B            DESIGNVARI       Variant Editor rename function removes all components
' l/ W* z$ ]- h' p1 q8 F6 a946380  F2B            DESIGNVARI       Some VARIANTX properties are hard some soft - why?
1 M3 r& x9 a' L! B946419  SIG_INTEGRITY  SIMULATION       Cannot select component on BoardModel for controller in bus setup form! x& z4 [, W/ {0 u. z$ i: W" {
946458  SCM            SCHGEN           Schematic generator adding an unnecessary page/ k  E3 P0 w. G+ ~
947667  ALLEGRO_EDITOR PADS_IN          Need support for PADS-POWERPCB-V9.3-BASIC+ N) P* e2 x$ ^! z  ~
947789  ALLEGRO_EDITOR MENTOR           mbs2brd crashes during translation on the attached design.
# P8 D; h5 U1 Z" i948110  CONCEPT_HDL    CONSTRAINT_MGR   Concept HDL craches when opening SigXP from CM
6 T! c( C, }2 x3 j( ~4 n950970  ALLEGRO_EDITOR MANUFACT         Unable to generate artwork, dbdoctor fails to fix errors.+ H* S  H3 k5 I
951901  ALLEGRO_EDITOR EDIT_ETCH        In 16.5 add connect to same net is shoved
: B6 b$ |1 z- l+ f' g951919  ALLEGRO_EDITOR OTHER            Exported package symbol soldermask and pastemask padstack locations not the same as original) S$ Q6 N$ K0 v  L. s
951926  CONSTRAINT_MGR OTHER            What is MaestroNotifyNotSetReport.txt file?
6 Q" h* V' o7 X# _951939  F2B            PACKAGERXL       Uprev to 16.5 is changing refdes for some pages
' |7 \9 u+ F% H) L: d951983  CONCEPT_HDL    INFRA            Problems converting an Allegro design from 16.3 to 16.5; C. Q: z' z- m, m0 P6 }
952057  SCM            PACKAGER         Export Physical does not works correctly from SCM
$ p& r8 w3 d& N; _* t2 q7 @9 F952217  ALLEGRO_EDITOR GRAPHICS         crash when opening 3d viewer in PCB Editor" X8 M; o( _. R
952634  CONCEPT_HDL    CHECKPLUS        Checkplus logical rule fails on a design which packages fine in 16.5
5 m# c7 g" l0 V% s- d7 P" ?2 o953018  APD            REPORTS          Shape affects Package Report result.+ ?: B. N) V# f
953337  ALLEGRO_EDITOR OTHER            Allow netname and padstack names to be visible for testpoint vias when viewed in Allegro PDF Publisher.: n% X7 d5 V: p+ m7 A2 ~. ^
953827  ALLEGRO_EDITOR EDIT_ETCH        Snake Breakout function crashed Allegro
5 H! J: Y$ P/ V" O: F. Y9 @! n953918  GRE            CORE             GRE cannot route second and third row of pad in die symbol.
! a6 G# I9 S+ G) \9 D2 ?. G3 P954055  CONCEPT_HDL    CREFER           Crefer fails with UNC install path" i( `: z* N$ J  ~
954920  SIG_INTEGRITY  CIRCUIT_BUILDER  Each neighbor crosstalk simulation crashes or returns blank report
) L$ d* j9 S/ X& d4 `$ T9 P7 U9 y. w( t) a" h  N" Z/ l7 D
DATE: 11-7-2011    HOTFIX VERSION: 010
  i, j; p/ E+ d3 N% U5 L; |===================================================================================================================================
8 I7 J1 U# B! E/ RCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
& H" Y) m2 A( A9 f& D* h===================================================================================================================================
( R( J: d9 _  v  i658866  ALLEGRO_EDITOR EDIT_ETCH        enhancement option - so that Sliding a via inside a pad does not create a cline. a5 `' I, W: W
928624  ALLEGRO_EDITOR GRAPHICS         Layer visibility control for 3D Viewer
0 G1 q6 ^& l- u8 l( D$ s* d934991  SPECCTRA       LICENSING        Specctra_adv option is not working correctly for PA3100 plus PS3500 license in v16.5 tiering profile
( V2 |1 j0 O# O+ c; B/ s, S938073  ALLEGRO_EDITOR PLOTTING         Plot Page size A0 and A1 with problem  F7 A# a% l8 W% e' X
938128  ALLEGRO_EDITOR DRC_CONSTR       DRC changes when do update DRC.
" s/ Y; s7 K) ]+ |0 c; s938648  ALLEGRO_EDITOR GRAPHICS         Enh - Requesting a way such that Package keepout appears transparent in 3D Viewer( c  P7 K, [7 U2 X
940518  SIP_LAYOUT     SYMB_EDIT_APPMOD Swap pins command doesn't complete: d) y& D* s2 |, j, J9 L. s: y' {5 D
941426  CONCEPT_HDL    COPY_PROJECT     Copy Project fails - Updating opf view This can't happen!
, \4 i- J/ l3 ?* X" N2 \! ]0 H& l/ ?941499  ALLEGRO_EDITOR DRAFTING         BUGimit Tolerance isnot working for Dimensioning7 ~! S8 t8 n6 B, a4 b
941814  CONCEPT_HDL    CREFER           CreferHDL crashes during ScheGen
- F) ~( `7 Q: G% o- S4 S' w# t, F942914  SIG_INTEGRITY  OTHER            ZAxis delay calculation$ R+ g' E6 T) E5 k- M8 f
943053  ALLEGRO_EDITOR SHAPE            Modifying the Board Outline shape will cause the tool to crash
5 L! _7 H. g& R, U7 }; G% n945321  SIP_LAYOUT     EXPORT_DATA      generation of a xml file from cdnsip for shrunken die5 I3 g1 \3 Q2 T9 M3 u
945350  ALLEGRO_EDITOR SHAPE            iPick does not work on shape boundary edit.
2 l7 C- d6 u& Y945449  APD            SKILL            When they create a new menu entry with skill APD crashes with next menu selection.% d+ n3 }6 [  ~- E" E+ A# n! j( U
946390  ALLEGRO_EDITOR DRAFTING         refresh_symbol crash when trying to refresh mech sym that has dimensions
2 Q. I$ t' h& b4 U% }946401  APD            EXPORT_DATA      stream out gdsII results in shorting of PWR/GND nets due to elongated etch7 G4 M  L. x7 q# H" R( u
946819  SIP_LAYOUT     DEGASSING        Shape degass command
, W5 Z7 y: h% W( c( {6 {946869  ALLEGRO_EDITOR OTHER            Allegro PDF arc representation needs cleaned up. M) p( S/ V! ^4 ~; B2 A
947230  ALLEGRO_EDITOR SKILL            Skill execution crash Allegro 16.5 but work correctly with Allegro 16.3
$ e# N8 }- M% \: H( B( H3 D947603  ALLEGRO_EDITOR OTHER            Component Properties (Default or User Defined) not transferred to PDF file5 ~0 c) v% ?4 X8 x  \
950995  SIG_INTEGRITY  OTHER            Netrev fatal error when importing logic. D2 T1 I) _6 S% N/ ?) X
951123  ALLEGRO_EDITOR INTERFACES       IPC fails to output drill hole info in columns 33-37! Y' v* Q  J% r- S/ x% B* Y# c
951557  CONCEPT_HDL    CORE             Cannot create the entity folder for old plumbing symbol, X2 f6 K; `  {* L& V

" A3 m+ l7 v; qDATE: 10-26-2011   HOTFIX VERSION: 009. F% z* `3 H5 a/ w
===================================================================================================================================
" u. [: L" x7 m% z; `+ H8 KCCRID   PRODUCT        PRODUCTLEVEL2   TITLE0 e* N: ~8 T3 ~$ i4 f
===================================================================================================================================5 s( P3 `1 W7 I
945788  CONCEPT_HDL    CORE             Some component properties on the parts are incorrectly changed after Import Sheet
: d- n5 W' e, ], k  `1 V945789  ADW            LRM              Some component instances are not updated by LRM even though cache ptf is updated from reference" D4 j9 v( C( I, p3 F# P/ s8 \2 Z

) v' s: p' K5 f0 }+ y$ LDATE: 10-21-2011   HOTFIX VERSION: 008
) K% O7 g' Q. |5 m/ |1 K===================================================================================================================================
+ j+ G' K) a1 `% L; ACCRID   PRODUCT        PRODUCTLEVEL2   TITLE: j: Q# L* T+ \- n$ H: f& N3 I
===================================================================================================================================
* z. C2 ]+ n9 P' v# z! e/ N906827  ALLEGRO_EDITOR DATABASE         Logic > Parts logic does not work correctly.+ O( O2 i$ ^1 y6 ^  @( }
923346  CONCEPT_HDL    CORE             Not able to move the reference designators inside hierarchal blocks after uprev to 16.5
" L4 O- K5 K- }) o* m1 d926347  ADW            COMPONENT_BROWSE Usability- Libflow Part check in comment should end up in Comments attribute for UCB/Designer to see it
2 v) |. e8 ^0 ?; {' t9 L. }929348  F2B            BOM              Warning 007: Invalid output file path name
3 j! {+ y4 ^: v! x2 V5 ]! {  ]( ^9 n929777  CONCEPT_HDL    OTHER            Component Revision Manager gives internal error
& K. q+ r9 r' l2 G7 Z930783  CONCEPT_HDL    CORE             Painting with groups with default colors( B# P* A) x7 O  @; O
936748  ALLEGRO_EDITOR INTERACTIV       "Unplace Component" menu inconsistent between General Edit and Placement Edit Mode.
7 i/ p. W6 z# Y% a938143  ALLEGRO_EDITOR CREATE_SYM       Why is this Extra Property 'ECSET_MAPPING_ERROR! @) H$ M* F& g3 X0 x* D1 T$ w% w; Q
938281  SIP_RF         OTHER            export_chips creating bad data when symbol is split and contains V- V+ pins0 Q* B, B9 D( @
938812  ALLEGRO_EDITOR SYMBOL           Cannot create a BSM with this DRA, errors out but does not state a reason.& N8 `2 W( y/ q2 ^
939075  CAPTURE        TCL_INTERFACE    Texts are getting garbled in command window5 J0 a; k! k8 c' R5 m
939193  F2B            PACKAGERXL       ERROR(SPCODD-439): Connectivity server is unable to load the design." D6 W! [- W' @0 `! U
939199  CONCEPT_HDL    DOC              "Retain electrical constraint on net" mismatch between schematic (YES) and design (NO); y3 ~. j, i* F+ g9 u8 [0 U9 h( ?
939346  ALLEGRO_EDITOR SHAPE            Shape disappears when updating with variable shape_rki_autoclip set.
/ q/ z( L7 M" z0 m3 A. f! b( q939901  CONCEPT_HDL    INFRA            NET_SPACING_TYPE shows �?� on lower hierarchy level nets after Upreving to 16.5 version.
: [! D9 ~5 C% |4 ?+ \939918  PSPICE         PROBE            Print > Preview for output file causes Pspice crash." A4 v" v3 d2 o& @, M
940217  CONCEPT_HDL    COMP_BROWSER     UCB reports 'No Symbol found for the part'
* \8 @# A' r$ z% d7 d7 a940835  CONCEPT_HDL    INFRA            Desing package different after uprev to 16.5 where comp instance  propeties are lost  lost3 j6 L4 M& C# P0 o- [
941125  ALLEGRO_EDITOR DATABASE         Performance advisor doesn't skip non plated slot padstacks3 v* ~+ V- G3 A4 g# O
941876  SIG_INTEGRITY  OTHER            Illegal model name cause pxl fail in 16.30 R: p. n2 w% g' \# n  ]0 a
942210  SCM            OTHER            Is the Project File argument is being correctly passed?0 Y6 C( v% |4 Y0 n" i9 V2 v3 Q' r
942274  CAPTURE        PROJECT_MANAGER  Crash on renaming a Design Cache part in Project Manage after doing replace cache
" ~4 D- ~* |  x5 I: q942839  ALLEGRO_EDITOR GRAPHICS         Graphics Issue- Pads are not visible/ r5 b  j& X2 w2 q
943055  ALLEGRO_EDITOR SKILL            axlDBCreatePropDictEntry causes application to crash- ~3 o) C, j$ U* {' S# b; }9 d
5 R& {& e8 `. L2 R- I0 Z, q
DATE: 10-21-2011   HOTFIX VERSION: 0077 }- I) t3 n- F( l4 J
===================================================================================================================================* S. }  B3 H. C- V, r+ p
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE( B9 T  t9 @% |1 A1 s$ M
===================================================================================================================================+ o9 f5 c, J; d- _; [
841096  APD            WIREBOND         Function required which to check wire not in die pad center.. E6 i+ I7 a) U! I4 t
903263  CAPTURE        SCHEMATIC_EDITOR ENH: Selecting parent netgroup must select the underlying netgroup bits.
8 @4 x1 o- a" C5 N906692  ADW            LRM              LRM window is always in front when opening a project+ `$ g* p# j$ W, F1 b
912942  APD            WIREBOND         constraint driven wire bonding
" F7 O& V" C* w' |912951  CONCEPT_HDL    CONSTRAINT_MGR   Need to manage temporary files on Linux systems. j5 X4 U1 Z: g6 O0 }5 a
915178  SIP_LAYOUT     DIE_STACK_EDITOR Die Pad names changing when updating Die in a design- @& k8 X& D; p/ b# u9 ^
917887  PCB_LIBRARIAN  VERIFICATION     Part should not be released if the alt_symbols has errors! l' Y! U! o( l' A+ @2 r
923315  SIG_INTEGRITY  GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure3 O6 G4 `( N0 F0 Y1 x
927382  CONCEPT_HDL    CHECKPLUS        'Verify Symbol' forces the use of 'Concept_HDL_Studio' license1 V+ Y# f% Z8 \6 F2 a" `
927664  CONCEPT_HDL    CONSTRAINT_MGR   Internal Error disposeipsp8 b4 r  X( J. d# ], k# t
930152  CAPTURE        NETGROUPS        Scalar net names when being connected to net group overlap when connections are made one by one
$ t' X* @2 T5 c930180  CIS            LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation3 p* H/ J. m& R/ ^0 O, b9 o
930188  CAPTURE        DATABASE         Capture 16.5 crashes in being re-invoked.
( o' o) |$ H$ u  q930541  CAPTURE        NETGROUPS        NETGROUP element renaming doesn' renames the associated net ?
9 U+ ?2 \3 K4 W9 ?( U% m7 @; ^930866  PDN_ANALYSIS   SETUP            OrCAD PCB SI Session crashes when we open PDN Analysis with "OrCAD PCB SI" license.
6 ~  x- C$ ~* ~1 u3 h& U930926  ALLEGRO_EDITOR GRAPHICS         Via and Holes not visible eventhough set to Visible in Color form9 h% p" X1 Z2 B; S3 h3 b8 s
931274  ALLEGRO_EDITOR DRC_CONSTR       Negative Plane Islands waived DRCs reappear after performing update DRC.# d% S- y1 q* j! ^& r1 Y' x% f
932091  CONCEPT_HDL    CORE             Prop attached to SIG_NAME property# H* L/ a; i1 R' j4 x
932255  ALLEGRO_EDITOR GRAPHICS         Change in Zoom level makes arc segment to disappear: L6 z( ]; q2 O
932292  ADW            LRM              LRM crashes during Update operation on a customer design. K. N6 T# ?: m2 Z
932639  SIG_INTEGRITY  OTHER            Add Connect command hangs for about 14 seconds and then returns.$ Z" Z% l* l& i* P; l& F2 H
932704  APD            DEGASSING        Shape > Degass never finishes on large GND plane  T4 s4 [) J; u8 `* W
932871  APD            GRAPHICS         could not see cursor as infinite
3 I5 p: x* r$ }* A  H- a932882  CAPTURE        SCHEMATIC_EDITOR Capture crash with FIND command - ISR05
' `  |8 A' w+ V# k" `9 O932969  CONCEPT_HDL    CORE             ConceptHDL crashes when you save the design in 165 > hotfix #05
' q: {* s+ \; u( b, @/ w7 Y933024  CAPTURE        NETGROUPS        Naming restrictions for NetGroup members; t9 u1 Q" ~1 {
933145  F2B            PACKAGERXL       Add Subdesign list is truncated in Force SubDesign Design Name pulldown
' a  o  U# P8 B0 B. |- ], U. H933214  APD            ARTWORK          Film area report is larger when fillets are removed
- e- M5 {; ~8 I8 ]( `, l933356  CONCEPT_HDL    CORE             Net prop display size become 0 if it was attached to SIG_NAME prop.
+ h. _* C, G) i' d& L& ^7 i933532  ALLEGRO_EDITOR COLOR            Bad color assign and initialisation during creation of new subclass
8 ^* l9 q, G( Q: \, V933549  ALLEGRO_EDITOR OTHER            Chart text missing in export PDF file.5 Q8 e) {& h5 w  |6 p/ v
934008  ALLEGRO_EDITOR REFRESH          refresh symbol updates symbol text to some unexpected values, P5 g% ^" U+ e
934031  ALLEGRO_EDITOR DRC_CONSTR       Bug : Update DRC removes Waived status for some DRCs1 k8 s$ J* g$ s/ K$ v% i
934087  CONCEPT_HDL    CORE             Opening DEHDL and Model Assignment before design loads causes crash3 ]$ ^4 l5 c. K% L: c# |" y
934396  CAPTURE        SCHEMATIC_EDITOR Find operation is not searching power symbols with + or - signs." `& j6 Z4 ^/ |% ~% L/ [/ O
934533  F2B            DESIGNVARI       The Variant Editor errors are not written to the variants.lst file" k% d3 ~; F+ A% c/ O5 q" w
934811  SIP_LAYOUT     UI_FORMS         CDNSIP should not hang if contraction value in z-copy command is out-of-bound
1 f2 `% k2 p# u8 `, U" x934909  SCM            UI               Require support for running script on loading a design in SCM
* ~* Q! q) e4 A3 \$ l- Q! W" X935632  CAPTURE        SCHEMATIC_EDITOR SHIFT+Mouse wheel scroll(horizontal) of page is not working in Auto Wire Mode.  q' \( {- F  D. K! o
935794  ALLEGRO_EDITOR SHAPE            BUG:Shape not filled in 16.5 but it does in 16.38 s: I, Q0 y' W5 G3 q
935988  ALLEGRO_EDITOR INTERFACES       When attempting to downrev this 16.5 design to 16.3 the tool will crash
# x% l& C5 M2 q8 y7 m, j* b936056  ALLEGRO_EDITOR DRC_CONSTR       place_manual crash while moving mirrrored symbol
8 r7 n$ Q" d$ O* X936098  ALLEGRO_EDITOR SKILL            axlDBCreateCloseShape does not work correctly.
7 @  M( H" \: g0 t4 ?7 U/ i$ ]  C: I936212  ALLEGRO_EDITOR INTERFACES       DXF not created if Blocks created for Symbol and padstack: [! u" ~4 J  P: V3 J' j+ h) B
936797  CONCEPT_HDL    COPY_PROJECT     Copy Project crash) u6 l$ J7 \% A4 k. m3 k
936808  ALLEGRO_EDITOR DATABASE         Allegro crash replace mechanical symbol# M9 m/ Y- [; G+ I
936853  CONCEPT_HDL    CONSTRAINT_MGR   DEHDL crashes when trying to extract net from CM
, F4 z  p' E9 p- H/ _9 \1 a937087  CIS            DESIGN_VARIANT   Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE
# z! }! `: Y6 p# V& \, j, g3 t937173  CAPTURE        OTHER            Wrong license information "UNLICENSED" in Capture >> Help >> About
! D& ]2 z- y4 b4 E937290  APD            PLATING_BAR      Plating Bar checks does not recognize connection made through etchback through shape.. y' r' d: M5 T' u/ B% Y
937411  ALLEGRO_EDITOR DATABASE         downrev_library  reading from one directory and writing to another hangs the command.; r$ y4 g- r& _7 Q" [" K3 E
938235  SIP_LAYOUT     STREAM_IF        Die Orientation is not correct after importing a stream file.3 V/ O7 W% v9 B$ M) R" X+ }
938273  ALLEGRO_EDITOR OTHER            PDF export is is not opening viewer with ads_sdlog variable set% r  G7 T! D- {3 `
5 N+ N% s8 _6 q$ K5 _$ `1 N% H
DATE: 09-16-2011   HOTFIX VERSION: 006
. i& i0 i, T" D===================================================================================================================================9 {! y+ R, r/ v$ ?2 h
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE/ P1 A! S7 E: |" W" I/ x8 n- Y
===================================================================================================================================8 W7 g% o1 j% ~2 C6 Q0 c! @. }
820131  CONCEPT_HDL    OTHER            Moving symbols to other page will make Allegro components unplaced because logical_path changed.
+ W; i/ _9 u0 r+ J# j( S863860  CONSTRAINT_MGR SCHEM_FTB        CM should display or Local Interface and Global nets to help defining low level constraints
5 q. ?5 L6 i! i9 D" W. \3 {919822  TDA            CORE             Cannot configure LDAP to only list the login name+ k" M; g) _; V% \2 O, B* g& }
922907  ADW            TDA              搇ast_callout_file� directive in the BOM section is empty causes tda for show Access Denied error
7 ^: g  H4 T0 f" A924322  ADW            COMPONENT_BROWSE Random - No instance properties are added on Add To Design (RMB or double click) from Search Results
/ F# P/ D% V, t. C* f9 T1 A5 d924448  F2B            DESIGNVARI       Design does not complete variant annotation
1 M! q1 x2 M0 }  L* E! o925584  CONSTRAINT_MGR SCHEM_FTB        16.3 upreved Design passes the SLOT/Function Properties to PCB
8 f* l$ X3 K( ?6 P927102  ALLEGRO_EDITOR OTHER            Question of Conductor Detailed Length Report
7 S; i: y4 A- K* B1 ~8 T& j$ n927104  F2B            DESIGNVARI       Tools > Annotate variants crashes when there are ASCII characters in the property values+ I1 l4 J* [% ~( ?
927142  F2B            DESIGNVARI       Incorrect pop up asking while executing variant editor from the command line
- @( @# ^9 r- |& v* Y927166  CAPTURE        NETLIST_ALLEGRO  ENH: Feature like NET_SHORT in Capture Allegro flow which allows user to short 2 or more power nets" w2 H# S; A  w9 z/ T. V
927410  ALLEGRO_EDITOR DATABASE         ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor
/ B* O* j, L- X3 M$ i$ L; Z927475  CONCEPT_HDL    CORE             About forcereset command of nconcepthdl% l- H, O0 O: e
927498  CONCEPT_HDL    CORE             Pin_Name starting with minus causes incorrect behavior for $PN display
+ x' F5 P5 {) c! P927608  ALLEGRO_EDITOR PADS_IN          Import PADs fails with error message: Failed to close the Allegro database2 p/ v6 d& v+ [* X. w! A: k" s% N$ v
927637  SCM            CONSTRAINT_MGR   ASA crashes on change root and also performance is too slow.
& v2 @; P: e) _. s6 D928429  SIG_INTEGRITY  OTHER            Request - Package Wizard to work in PCB SI.
3 B/ E% Z* T, e1 N928483  ALLEGRO_EDITOR DRC_CONSTR       Running Update DRC removes Via List DRC Error when via is actually not in the list
- b5 i# Z2 l8 M4 j& z928738  PSPICE         PROBE            Y-axis grid settings for multiple plots
1 O+ l! _2 o  z! ^; i928748  PSPICE         PROBE            Cursor width settings not saved% j- ^( R& Y8 Y1 R2 }  G
928779  CONCEPT_HDL    CORE             Error (1053) occurs on a copied part in SPB165 release
! m0 ~3 _+ Q& }928838  CONCEPT_HDL    CONSTRAINT_MGR   ECSets not migrated in 16.5& Q$ h) W$ `" p2 L( Q6 e  p
928885  SIG_EXPLORER   EXTRACTTOP       PCB SI crashes when extracting a net from Probe4 S8 e0 C! K7 ?: W- {% f. q
929284  CONCEPT_HDL    ARCHIVER         archive does not create a zip file
5 E) |+ I, \! U7 f" ]6 R, {# k929542  SIP_LAYOUT     DIE_ABSTRACT_IF  net issue of multiple ports of co-design die in SiP
9 c* ]  |& F* t& P$ h- B" T929656  ALLEGRO_EDITOR PADS_IN          PADS translation fails with Microsoft Visual C++ Runtime Library error3 S7 t9 [- g7 m* G# J( }. I7 R
930063  ALLEGRO_EDITOR TESTPREP         Test prep crash Allego when it can not create pin escape3 C$ {* k: h$ a" d
930217  CAPTURE        NETGROUPS        Net aliases doen't gets assigend to bus bits if bus name is checked in NETGROUP.
* M6 m+ @/ L% c1 M$ L" y# q930355  SIP_LAYOUT     WIREBOND         about "wirebond add nonstandard" command! c# t7 Q) L2 u% }( L- w* v: r
930607  APD            OTHER            Layer mapping information is reomved from Layer conversion file upon exporting DXF from board file.
7 u9 M  E8 j: Q+ o930646  ALLEGRO_EDITOR DRAFTING         Bug - Adding Linear Dimenstion for ISO standard add the Angle information as well
- C/ Z6 H) F5 Q8 _; l930894  CAPTURE        TCL_INTERFACE    PDF export doesn't  creates property file if some symbols are used in page name/folder name! b: m) P6 V  \: h% {
930944  ALLEGRO_EDITOR OTHER            Setting variable 'appmode' equal to 'none' is not changing the Application Mode when reinvoked7 a- h. u1 H/ m* U7 L, u% D
930978  ALLEGRO_EDITOR SCHEM_FTB        3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens
% A! s5 b; g" O- N! m5 d0 f+ a931248  ALLEGRO_EDITOR DRC_CONSTR       Match Group was removed if member nets became xnets.: c* w7 }- O. g4 I$ R# B2 {
931278  CONCEPT_HDL    INFRA            $PN gets copied when upreving design from 16.2 to 16.5 version- f2 {+ H' E# b- n) [
931349  CONCEPT_HDL    COMP_BROWSER     DEHDL craches and corrupts connectivity file when using Modify command extensivly.
2 }8 l) A( q) ]) `1 d7 Z
) O* U+ e) X6 o' \  LDATE: 08-31-2011   HOTFIX VERSION: 005
: e4 ~5 R# X& y7 u$ C- G===================================================================================================================================
" u6 N$ K! ]) K6 _- K9 J1 HCCRID   PRODUCT        PRODUCTLEVEL2   TITLE- r7 O% D" b) ~, }, {
===================================================================================================================================  ?2 m) N/ @  I. v+ X
825848  ALLEGRO_EDITOR SHAPE            Shape not filled when edges from 2 RKO shapes touch around mouting hole$ N3 s: k9 X9 l$ {
837723  CAPTURE        PROPERTY_EDITOR  Occurrences of external design not related to current root should not show
- \) B! U: m" c891079  CONCEPT_HDL    CORE             DEHDL crashes with large number of commands in Winodws mode
, x  W9 _% D- b" v0 q/ H# y910908  SIG_EXPLORER   OTHER            Cannot open top if Tx AMI dll name contain more than 2 dot.
5 k, o" F5 S1 J- _' z914036  CAPTURE        LIBRARY          ENH: Option to delete a corrupted part from a library and leaving other parts intact in the library.. z7 b0 g0 z! ?, d. C; s
914679  ALLEGRO_EDITOR INTERACTIV       Custom toolbars are not retained when switching between brd to dra and back to brd file using the File > Recent Designs
7 ]0 A. I" o7 u9 H% U$ J7 `2 F! \914870  MODEL_INTEGRIT OTHER            mergedml fails to merger 2 DML files from the model integrity
  y5 D& V2 \# {! G4 n" l915645  ALLEGRO_EDITOR MANUFACT         Allow the user to place the cross-section chart at a desired location
" n+ j- v% J2 i+ c915653  ALLEGRO_EDITOR INTERACTIV       unable to delete non-etch shape( n: f, g7 x! U8 J0 Z1 l5 r* H) Z
915711  ALLEGRO_EDITOR MANUFACT         dimensioning tolerancing by limit not working
' X* M! i$ ^# m0 h9 j) _5 [916321  CAPTURE        GEN_BOM          letter limitation in include file- }) q' b9 `9 a4 R
916907  CAPTURE        SCHEMATICS       揂uto Connect to Bus� should place the wire through non-connectivity objects2 E/ x8 {, h) J+ ?8 r3 @# N
920327  CONSTRAINT_MGR ANALYSIS         The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus.1 h/ D1 d1 |% o$ i# x+ \0 t' A
920753  ALLEGRO_EDITOR GRAPHICS         If I confirm to padshape with zoom-in after install the s002 It was changed to wrong shape.2 h/ Y& Q, e3 W) p0 s0 x
921097  ALLEGRO_EDITOR GRAPHICS         Padstack seen partail filled when Zoomed in even "static_shapes_fill_solid" is set
$ a+ t5 H# ~+ J9 e: x- s921226  ALLEGRO_EDITOR DRAFTING         Unable to select Package Geometry class when dimensioning in the symbol editor.
& T3 b" M4 S. H1 h921623  ALLEGRO_EDITOR GRAPHICS         Bug : Symbol not visible when zoomed in 16.5 S002
3 G8 C. p: O' n: {4 s921891  ALLEGRO_EDITOR DRAFTING         dimensions are lost after downrev(ing) a SPB 16.5 design with associative dimensions/ U# G4 p1 C- f  F. X
921937  ALLEGRO_EDITOR COLOR            Padstacks with shape symbol are not showing correctly" y( B+ N  O. d$ z, C
922066  CONSTRAINT_MGR ANALYSIS         Custom measurement Actual not being cleared when layout changes.
% W' C5 ?5 r6 L; B' }$ U922117  PSPICE         PROBE            Label colors are not correct in Probe
3 @5 `8 E# _  @# O4 u922519  ALLEGRO_EDITOR SKILL            add_bviaarray command fails for some clines but not all
  c# n6 d% c( |8 I923224  ALLEGRO_EDITOR GRAPHICS         Thermal flash Display problem in Allegro v16.5 Hotfix S0026 q, L+ V7 X8 Z4 P/ x+ o
923286  CAPTURE        DRC              DRC markers not reported for undefined RefDes
6 B5 Z  a9 d) J$ m; ^923362  ALLEGRO_EDITOR PLOTTING         Print to Postscript file not correct in 16.5
2 U: \$ y8 B8 ?5 \923416  ALLEGRO_EDITOR PAD_EDITOR       Pad Designer crash on clicking on the Arrow before Soldermask_top
" G6 o: u4 f3 f+ |+ T) Z5 H923507  CONCEPT_HDL    CONCEPT-PCBDW    The function of Import Design in the SPB16.5 Design Entry HDL (for data of ADW15.5_S23 + SPB16.3)2 b4 D: y+ c! L6 M& P. v
923910  CIS            PART_MANAGER     Copy & Paste operation from Part Manager copies properties only to first section of the part.' s5 F% w5 Y' \" _0 |4 d
923913  CAPTURE        PROJECT_MANAGER  Capture runs slow on attached design
8 Z/ |* m1 J+ t$ D' t& h  F) `7 Y923937  CONCEPT_HDL    CORE             Back annotation time significantly increased with the metadata generation on
/ H$ C" K2 Q7 o" n# D923949  ALLEGRO_EDITOR INTERFACES       Incremental DXF_IN gives 'Invalid subclass' error& Z$ p/ s$ |4 ~# {6 P/ ]& U
924458  SCM            OTHER            Project > Export > Schematics crashes
# i0 c4 G. d$ U  }/ Y$ o924621  ALLEGRO_EDITOR SHAPE            Dynamic shapes are disappearing upon updating them to smooth.
$ T9 f. X2 g* `925193  SIG_INTEGRITY  FIELD_SOLVERS    Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect
7 l1 x* e$ P+ w* [1 w925195  ALLEGRO_EDITOR DRC_CONSTR       Incorrect pin to shape DRC error' m% Q3 G3 G# p7 \% s
925338  CONCEPT_HDL    CORE             This application has requested the Runtime to terminate it in an unusual way
0 U) U6 c' v* V, A  d& K& E925435  CAPTURE        TCL_INTERFACE    Capture crashes if 揝ave design as UPPERCASE� option is disabled.
5 q6 e4 t/ g5 O' A4 ?3 H925530  SIG_INTEGRITY  OTHER            Why the single line impedance value for Top and Bottom layers are different for this design?3 ?: ~9 P0 r2 ~/ U2 R' F" `  @
925864  ALLEGRO_EDITOR DRAFTING         Ability to add dimensioning to different CLASS/SUBCLASS
: d* c* y0 ^) Q& t2 v5 Z% D+ |925976  ALLEGRO_EDITOR MENTOR           mbs2brd fails to import data  [' B( v6 F$ J9 J: [
926409  SIP_LAYOUT     DRAFTING         Exporting a 16.5 design to 16.3 will cause the leader/dimesion lines to be removed.
# o, `/ Z4 B4 q926443  CONCEPT_HDL    CONSTRAINT_MGR   In new 16.3 "035" ISR Concept2cm will crash with error.( V7 f8 R9 k0 N  k$ |% a+ `( j
926503  CAPTURE        GENERAL          Memory leak Capture/Pspice
. v) \" s' z7 ]6 m) Q926553  CONCEPT_HDL    CONSTRAINT_MGR   CMGR ERROR There is no net in the Cset that has pins matching those in net 1 in the Xnet
' d8 T+ M# |$ Z4 _! m+ @926691  ALLEGRO_EDITOR OTHER            Crash while Importing Technology File in CM, with Overwrite Constraints.
& ^0 M" L" h0 Y0 \# n926887  CONSTRAINT_MGR CONCEPT_HDL      Pin pairs lost after Export Physical
7 \: l5 y9 S; F) i% a2 m9 G927159  CONCEPT_HDL    CONSTRAINT_MGR   Export Physical fails due to errors in ConCM.log when SIGNAL_MODEL injected property is ''
1 M  r# r" ^) T* N; N$ a3 S; ^3 U. y: l  }3 m/ p% Q9 K
DATE: 08-19-2011   HOTFIX VERSION: 004/ C! f3 U( S+ T6 x
===================================================================================================================================
* b3 Y7 v/ E8 o% g5 y' YCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
$ V. G# d4 R1 X! S5 @: a+ u9 m( E===================================================================================================================================
. r" r: \/ c" e) `" ~6 j785417  CONCEPT_HDL    COPY_PROJECT     copyprojectui crashes with a Windows runtime error( p) x8 ~/ O, M' T- v: @
851044  CAPTURE        GEN_BOM          "Export BOM report to Excel" does not appear in the Standard Bill of Material Window.; L$ {; F( b7 ]+ k: O
868216  PSPICE         MODELEDITOR      Encryption of subckt names, internal nodes, comments1 n+ Y8 C8 I8 F* U, z$ r
870247  PSPICE         SIMULATOR        Encrypt a model and simulate it, info about inside nodes being dumped in the probe file
) u& |* U" m4 v" T877091  CAPTURE        SCHEMATICS       Save JPEG, GIF, PNG and other image formats in the database in its compressed form! y8 ~8 y- C) d& H3 ]
894059  CAPTURE        OTHER            Enhancement: Adding column in edit>browse>parts window& x5 H4 b' U) k* U0 c
895902  RF_PCB         OTHER            Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1
) g0 }5 z2 c3 U; d2 e, p2 G2 j895919  RF_PCB         OTHER            Round trip Allegro to ADS to Allegro requirement
( p2 N9 z( e; K' R1 r903102  ALLEGRO_EDITOR OTHER            Zcopy shape command for cline seems not to work correctly.
0 ?  W% f# T: ?( a7 B: L- H7 i905562  SIG_INTEGRITY  SIGWAVE          Noise margin seems not to be measured correctly with Eye Measure function.7 ]4 P0 H  X" }6 _& `- N1 D
909469  SCM            TABLE            ASA crashes when opening project
( z' o2 @+ _" z909595  APD            LOGIC            Inconsistency between export die text out and show element after pin swap( v( D: f! c: f, M5 {0 O5 r! K
911123  CONCEPT_HDL    CORE             16.2 Design uprev to 16.5 fails with ERROR SPCOCD-1523 F: z; I/ m1 d2 b$ S
911569  CAPTURE        EE_INTERSHEET_RE Q: Why is capture assigning incorrect Irefs in attacehd design ?) ?+ X3 q! n( K8 f- W
915657  ALLEGRO_EDITOR OTHER            Allegro PDF Publisher  Mirror capability
, p5 `4 e" n2 ]2 W. }+ ?0 {1 `/ ?: u915755  CONCEPT_HDL    CONSTRAINT_MGR   Cannot view net in SigXP
  ~1 h9 L& d5 @: z916062  CAPTURE        GENERAL          Auto Wire Crashes Capture
) B7 B* Y  E+ @7 S5 V916820  F2B            OTHER            RF create netlist with problem, Q7 B8 E* H9 D5 E, g
917967  ALLEGRO_EDITOR REFRESH          Update symbol resets refdes location for bottom side components only.* S, U4 E3 U6 d9 |% J8 M) U3 |
919343  ALLEGRO_EDITOR PLACEMENT        Place Manual is crashing the board file1 f. U" g( ^; g3 Y, F
919481  CONCEPT_HDL    CHECKPLUS        CheckPlus isGlobal function is not working! v( s1 D! k9 _1 d- ]% g
919510  CONCEPT_HDL    PAGE_MGMT        takes 10 min to insert page in DE HDL
6 y  W4 T2 y0 \: @$ }- y8 j919976  APD            DATABASE         Update Padstack to design crashed APD.
2 V, ~* {- }2 w5 }& P920418  SIP_LAYOUT     OTHER            SiP enhancement to Auto Assign Pin Use to add ability to change the pin use definition
- Y) b8 u* ~7 @+ y" t, _6 w: ]4 s2 O- V920420  SIP_LAYOUT     LOGIC            SiP enhancement to Logic Auto Assign Net to display a dialouge Auto Pin Use assignment should be run) H5 i0 Y4 R8 X; a2 g* k0 z. N3 |6 v+ U
920712  ALLEGRO_EDITOR ARTWORK          Program has encountered a problem ... error when creating artwork
) d3 A% x; M* Z3 F: I7 S( R' P7 j920763  ALLEGRO_EDITOR ARTWORK          Soldermask gerber missing thru-hole pins
: {  R' ~$ K0 @8 D" {920976  ALLEGRO_EDITOR GRAPHICS         Question regarding the difference in the behavior of 3D Viewer w.r.t. height_min
7 ^" H8 C7 F* @! b; @- d/ a$ b920993  ALLEGRO_EDITOR DRC_CONSTR       Minimum Metal Spacing Error is detected on Same Net' }6 l: G2 r: G5 f, \9 D
921727  ALLEGRO_EDITOR DRC_CONSTR       Pad Boundary causing P/P drc to adjacent symbol.
7 W8 l, d% D+ B( I922579  CONCEPT_HDL    CORE             Xcon file gets corrupted upon Save of Hierarchical design with Global nets tied to interface nets
- |: i2 v, k4 X9 E' f# A922592  CONCEPT_HDL    CORE             DE-HDL does not report illegal connection when  Global Net  tied to  interface net using an Port symbol and named  t/ F6 B3 ~/ e
922758  ALLEGRO_EDITOR DATABASE         Allegro crashes while placing second mechanical symbol with route keepin
6 Q. c# W4 A7 L( H; B6 t922839  ALLEGRO_EDITOR DFA              The DFA drc display is unstable.
* C' h1 Y) V2 ^2 L1 f% c: e) i923293  ALLEGRO_EDITOR INTERFACES       File> Export> IDX is failing for this design while creating an empty error log., F9 }2 y8 g! `" o7 [( [  T+ g. m
924772  ADW            PCBCACHE         Import Sheet is not bringing in Parts used in the source pages into target cache ptf. p: y# D6 \: V2 N4 O2 X- N3 G4 t
7 L1 m# |+ s7 y; O. n# m
DATE: 08-4-2011    HOTFIX VERSION: 003" z, V& l5 O* o7 d  {
===================================================================================================================================
' o+ C& E; h; V6 f! aCCRID   PRODUCT        PRODUCTLEVEL2   TITLE$ f5 b) v+ N& z; C% F! I% x
===================================================================================================================================; E9 z% t: I# t0 g7 b: c$ G: H
787414  CAPTURE        PROPERTY_EDITOR  Part value can抰 be moved on schematic if a part has been copied to a new design and not saved yet.
4 N1 P% ^$ w9 L: P) ^+ }; t+ \903898  PCB_LIBRARIAN  GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics
: E4 l) s3 x- G5 p! @; u9 O1 J/ @904287  ALLEGRO_EDITOR ARTWORK          some cline with arc is missed, when creating artwork., o2 q0 g& f1 D
904418  CHANNEL_ANALYS SIMULATION       channel analysis sim does not give valid result
3 `  [! z3 m( D4 S( ~( p905777  SIG_INTEGRITY  SIMULATION       User gets popup message that halts an analysis until it is acknowledged* K& V  E& m8 q+ A! q
906139  SIG_INTEGRITY  OTHER            Bus sim result were cleared at the next run even if no preference changed.4 W% ~- J. N* H, V4 t- G7 \9 m- Y' g
908680  SIG_INTEGRITY  OTHER            Extra prop delay due to resistance$ ^' g6 v' \. I" {
909583  ALLEGRO_EDITOR SKILL            axlPolyOperation AND operation is not working correctly.
' e; s/ \2 w6 O" A910315  ADW            LRM              Import Design with ADW causes partmgr and pxl errors5 F' Z& j$ I9 e9 o, x
910689  CONCEPT_HDL    CONSTRAINT_MGR   NO_SWAP_COMP warning after uprev to 16.58 \5 ^0 P0 b, _4 ]) e$ Y
911684  CONCEPT_HDL    CONSTRAINT_MGR   Attribute Definitions are incompatible for attribute 'HEADER'. when attempting to place in 16.5
4 w5 n8 ~8 i6 r; H912343  APD            OTHER            APD crash on trying to modify the padstack* v: h; E6 C/ z
912384  PCB_LIBRARIAN  CORE             PDV Symbol Editor often freezes when moving groups objects by arrow keys
: ?( u5 ~# [" g912853  APD            OTHER            Fillets lost when open in 16.3.- P/ u7 a' M. [9 E) l3 y& {
913586  ALLEGRO_EDITOR ARTWORK          Cannot create the drill figures in this design.( \& @1 L8 R" q# Y2 O4 j
914009  ALLEGRO_EDITOR DRC_CONSTR       Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.9 L7 I3 l3 @6 m8 s. u+ z  y# a8 M0 L
914110  CONCEPT_HDL    OTHER            DEHDL 16.5  Uprev overides property values  on hierachical blocks
! e. `. T" U/ ~5 C/ y914264  F2B            OTHER            Cross Probing from DEHDL for global nets present inside block doesn抰 highlight in PCB Editor.: G: C9 M; Y& H! F& L" D" b9 S+ U
914309  CONCEPT_HDL    CORE             16.5 DEHDL crash on saving the user design
" N2 D( ?. w5 ^7 T914558  ALLEGRO_EDITOR ARTWORK          Gerber6x00 output creates unpainted niche in a shape
+ L+ f' Q$ V( O- t914633  ALLEGRO_EDITOR ARTWORK          Artwork failing in v16.5 while the same design when downrev'd to 16.3 is working fine.
7 w0 Q$ {; f* W- h' {4 k9 |# A914634  ALLEGRO_EDITOR SKILL            IsThrough flag for a padstack is reset8 s! |' a" C2 k5 Q3 C& v  H+ h
914746  ALLEGRO_EDITOR DRC_CONSTR       DRC Update repeats takes longer on each successive pass.1 Q8 [. j$ u0 Z' W5 I  O
914962  ALLEGRO_EDITOR SHAPE            Corruption with Shape filling
1 M% P# u2 {: k! w915583  CONCEPT_HDL    CORE             performance issues in 16.5 compared to 16.33 Z0 E- R7 u. R8 a* u
915630  PCB_LIBRARIAN  OTHER            Error when running SI Model Interface Comparison using IBIS models
2 D8 A6 M1 c8 o9 p; E/ F" ]% ]915742  CONCEPT_HDL    HDLDIRECT        I get a newgenasym error and crash when trying to save the symbol
9 H/ i/ K9 j  `916154  SCM            NETLISTER        scm crashes when exporting physical database to allegro
7 L6 _# t8 w: K& P916448  CAPTURE        NETLIST_LAYOUT   Capture 16.5 Layout netlist contains errors  `  N9 W3 g6 N2 q, l) f$ R
916462  ALLEGRO_EDITOR DATABASE         Edit>Split_plane>create hangs Allgro PCB Editor! `) J7 w7 i3 }
916469  ALLEGRO_EDITOR REPORTS          One Unrouted pin does not show in Unconnected Pins Report
) J8 x/ V* P& l% I- E8 l916495  ALLEGRO_EDITOR INTERACTIV       Pick selects components from invisible (Off ) layer) h) D- U$ ~% A2 |% Z
916889  CAPTURE        NETGROUPS        How to change unnamed net group name?
* f% _  L0 r- J- _4 Y3 ]917002  ALLEGRO_EDITOR OTHER            Allegro PDF Publisher creates extra circles not available on film% n4 T" L* m, E; L  q
917434  APD            OTHER            Stream out GDSII has more pads in output data.& j+ u% u( F! I. O4 P4 `1 X
917739  CONCEPT_HDL    INFRA            Global Net tied to port is getting split into 2 nets in 16.5, in 16.3 it is treated as a single net
) M6 B2 T$ Y8 r7 K' W8 ?1 x918187  CONSTRAINT_MGR OTHER            Missing acGetTotalEtchLength predicate.
" T. ^9 Y" }0 c918576  CAPTURE        DRC              Incorrect DRC is reported for visible power pins which are connected to power symbol9 K7 D' @6 t/ c
4 ], q3 a' q, w: V% a9 R1 @, a
DATE: 07-24-2011   HOTFIX VERSION: 002
; y, S1 F. r+ w+ \3 {  b4 b===================================================================================================================================( M( u' V9 t8 t- `' H: z
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE$ M: q1 y/ h9 E8 a+ C$ d3 A
===================================================================================================================================
  g7 @9 n* `1 [* d5 o  f527444  ALLEGRO_EDITOR EDIT_ETCH        Slide command needs to be enhanced for same net spacings0 \4 t: P6 q  O7 p- C4 i! N
583257  ALLEGRO_EDITOR EDIT_ETCH        Add Connect and slide command needs to be enhanced for same net spacings.
. e2 d5 c- m/ P0 {% w! u592956  ALLEGRO_EDITOR EDIT_ETCH        Same net traces will not push and/or shove each other.
( S  T+ p: ~# X8 s$ S& V3 `" S745285  ALLEGRO_EDITOR EDIT_ETCH        Requesting a true "shove" in Route > Slide for Same net routing.
  @) T3 V0 O* a$ k) V1 e773503  CAPTURE        OTHER            Doing "Mirror Horizontally" creates extra un-connects or extra junction dots in Capture V16.3.
' S" W* ]- g$ Q; f/ n- j+ f774270  F2B            PACKAGERXL       Require to ignore space in Pattern setting to prevent duplicated Refdes.3 W" V: S2 D; N) m8 H3 _
799984  ALLEGRO_EDITOR INTERACTIV       Enhance the Fix command to select just cline segs0 k, k; V+ N6 j) O/ ]
809008  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".
, J  M5 w2 B/ R. s810058  CAPTURE        SCHEMATIC_EDITOR New nodes get appeared within the design when we select the design and do "Mirror Horizontally".6 n/ r: }6 ^. j4 [' G3 |
821133  ALLEGRO_EDITOR MANUFACT         Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format
, R) O0 u# r' @* f" _) k831710  CAPTURE        SCHEMATIC_EDITOR Capture adds extra junctions to design by itself
0 x! q& v  c, m3 p8 f  |5 k1 r/ ?  J842410  ALLEGRO_EDITOR EDIT_ETCH        Ability to slide with "Shove" for "Same Net" segments/vias.
4 y; t" Z+ O- r1 s+ t854971  ALLEGRO_EDITOR INTERACTIV       Capability to add cline segment in a temp group8 C1 q: o' t) |& }& l
860772  ADW            PCBCACHE         Save Shopping Cart (pcbcache) is crashing component browser  K7 \4 J4 S- r% k  J
867842  CAPTURE        PROJECT_MANAGER  Capture crash with 'Open File Location"" A% N4 M4 l# Q. k' r
868306  CAPTURE        CONNECTIVITY     mirror vertically removes junction creates extra nets8 A: ?$ R4 h/ M  k
882677  EMI            RULE_CHECK       bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE
1 `9 i# L4 x8 c5 `9 v891439  ALLEGRO_EDITOR INTERACTIV       moving cline segments
4 O$ j; @4 n; ?5 z. L893544  ALLEGRO_EDITOR INTERFACES       IPC-D-356A netlist issue with BB vias.7 Y. G' g3 ^2 S
893765  ALLEGRO_EDITOR PARTITION        Mail command not sending out email on Linux platforms.9 ]* N* N) A# |" F: b) d
894390  SIP_LAYOUT     EXPORT_DATA      Generate all balls in the xml file for export to EDI's readPackage command
" q9 l0 i% _* s- ^  u2 t% v7 |895933  APD            DATABASE         Update Symbol shifts the center of the Dynamic Fillet and creating DRCs
2 Y8 T! H( I( H6 W8 a* h896598  ALLEGRO_EDITOR PLACEMENT        error message is misleading8 q5 ]: v5 s- c$ J
897196  CIS            LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library
$ U  f- l( H' c8 t* ]898598  ALLEGRO_EDITOR MENTOR           Negative planes from Mentor Board Station not being translated.& f$ N8 Z3 f4 y: J9 f
899556  ALLEGRO_EDITOR ARTWORK          Import artwork seems not to work correctly.0 R! V0 A3 V  r( N8 ]% V
900501  ALLEGRO_EDITOR PLACEMENT        "lace Replicate Apply" is showing lot of DRC's during placement of replicated circuit in 16.5* ?8 x8 e  ]+ S$ Z& `2 w
901141  CIS            EXPLORER         Japanese character appear garbled in CIS explorer window.
" |( {. A6 W( r9 A' n7 v901666  CAPTURE        OTHER            Home page of Flowcad-Switzerland and Flowcal-Poland is not preserved on captre restart on start page& n9 E' V; `* i4 T9 _: ]' B2 {
902066  ALLEGRO_EDITOR DRC_CONSTR       Shape in Region not follow the constrains
1 C0 `* T; f, m. G902349  CAPTURE        LIBRARY          Capture crashes while closing library
3 n. |# X: n8 y+ D" x0 H( I* [902508  F2B            PACKAGERXL       SPB16.5 Packager-XL consumes much more memory than 16.3
3 M7 B% S" Z0 h+ q902841  CAPTURE        GENERAL          Capture Start page does not show7 c, g& w5 R5 P4 {9 a+ g! x; j7 s
902876  F2B            PACKAGERXL       Packager fails on the design upreved in 16.5$ H+ F8 b& q7 T. Q
902959  CONCEPT_HDL    HDLDIRECT        HDLDirect Error while saving design2 G; i. [, A$ R* E
903171  PSPICE         NETLISTER        Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs?
2 [3 R9 A) V* R1 k6 U$ w903713  ALLEGRO_EDITOR PARTITION        Placement Replication do not work fine in the Design Partition
# j* s" _2 g, Q! F( p, f903799  SIP_LAYOUT     DIE_EDITOR       Disappear die pins after exiting co-design die editor
6 i, B% j4 Z: ?" E, i904021  ALLEGRO_EDITOR OTHER            Export PDF from SPB 16.5 produces a file not text searchable0 p& L: P  O; N0 z' E( o7 Q8 P3 t
904339  CONCEPT_HDL    CORE             new design crashes using the attached CDS_SITE
7 I! Q- c2 U8 d( C904522  F2B            PACKAGERXL       Part will not package in 16.5  but packages in 16.3
/ \6 p  U! o# [; [2 _$ F- p3 S  `4 _904764  APD            OTHER            Enhance Scale Factor of Stream Out to support 4 decimal places9 k; J8 j: o0 f2 n; B3 r# w* t
904771  ALLEGRO_EDITOR MANUFACT         Pin Number display issue.
! ^: o( `( r' R# D9 E7 L904853  ALLEGRO_EDITOR GRAPHICS         Enhancement for showing Static shape as it was seen in 16.3; |, K8 Y9 x+ ~. K) u! p# Z% p
905144  CONSTRAINT_MGR ECS_APPLY        Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM
0 b* J6 n& v% i905314  F2B            PACKAGERXL       Import physical causes csb corruption
' X0 F0 N, M. J  w905337  CONCEPT_HDL    CORE             ConceptHDL crashes after Import Design process.
6 [( A5 T& G1 W. L2 J905533  ALLEGRO_EDITOR INTERACTIV       Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible
, Q  D& e3 g4 K905796  CONCEPT_HDL    CONSTRAINT_MGR   Fujitsu CM issue inaccurate concept2cm diff pair issues+ i; I# S, l! A& Q( W3 U; L" @
905811  CAPTURE        EE_INTERSHEET_RE interesheet references in the form of grid grid page number instead of page number grid/ O8 o# s: H2 G# F+ m
906118  CONCEPT_HDL    CONSTRAINT_MGR   Cannot open CM if SIGNAL_MODEL value was not assigned in ptf.. V; T" n" H) H' }4 |
906153  ALLEGRO_EDITOR SCRIPTS          Unable to run allegro script in batch mode on the attached board.
. D0 G' C5 r4 q; ^906182  APD            EXPORT_DATA      Modify Board Level Component Output format
, G5 j9 M" Q4 f* `+ v7 S' C906200  ALLEGRO_EDITOR DFA              Enh- DFA drc invoked in Batch mode returns false constraint value in Show Element
: u; H8 e5 v8 I( n; `' {5 z906517  PSPICE         PROBE            PSpice new cursor window shows incorrect result.  i. ?1 F# R$ b$ d5 x9 i0 [
906627  ADW            COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl.1 ?$ I: f$ P4 m6 j8 W2 N' u
906647  SIG_INTEGRITY  LIBRARY          lib_dist creates a signoise.log in current directory (with backup files like ,1 ,2 etc.) on each run( E: W3 `& k6 h5 Y
906673  F2B            PACKAGERXL       Ignore the signal model validity check during packaging
. Q, j" J6 L; G8 _' b. [! B7 c# [906688  ADW            LRM              A copy of source design gets created in worklib of target design after 'Import Design'
  z0 X: Z; q# j+ Q) r* ^906750  ALLEGRO_EDITOR PARTITION        Importing design partition removes the testpoint reference designation. y/ y' m; I8 y- S6 u* J  }9 o& s
906874  PSPICE         NETLISTER        Error less than 2 connections for unconnected hierarchical pin
* ?8 X6 B1 Q) _; F  `907095  F2B            OTHER            Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used& J8 V# s; Q) G* A+ n
907424  ALLEGRO_EDITOR GRAPHICS         Allegro add option for pre 16.5 shape display% |; U5 n7 Z' P2 p
907490  CAPTURE        NETLIST_LAYOUT   16.5 Layout netlist is not correct. It differs form 16.3 layout netlist./ z; K) t4 c: }
907884  SIP_LAYOUT     MANUFACTURING    Need to add an "NC" pin text option for "Manufacturing Documentation Display Pin Text"
9 R3 ?0 V. e4 |0 d  M! F- B907885  SIG_INTEGRITY  OTHER            Matchgroup targets lost when importing netlist  to Allegro layout in HF31' w+ K2 _7 Q( h& Z
907929  CAPTURE        TCL_SAMPLE       TCL command to delete a property from parts in a library is not working correctly
5 n- T. K: O+ \; t* Y907933  SIG_INTEGRITY  OTHER            Single line impedence not working in OrCad PCB Professional9 o/ c$ D( }  E7 q
907963  CONCEPT_HDL    CORE             Design uprev issue when moving from 16.2 to 16.5, M" {, f6 }9 r; s% {" U  K
908000  SIG_INTEGRITY  OTHER            Inconsistence z-axis delay reported on Tpoint when define at via location.9 B! J: s7 c3 X- h2 m, {
908057  CONCEPT_HDL    CORE             DE HDL crash with the cut and paste of a signal name& Q9 ^- d! H1 |, l
908060  CONCEPT_HDL    CORE             CTRL+LMB Option not working correctly in 16.3
6 e; x2 t" J: [# j( R& q* F! g2 X$ m908210  CAPTURE        CONNECTIVITY     Connection is being lost while dragging a component
3 m; |3 Q, V, D( T/ A# ~908241  CAPTURE        DRC              DRC error column is blank in DRC markers window in 16.59 I8 s1 M1 m. y3 o
908339  RF_PCB         BE_IFF_IMPORT    mechanical holes VIAFC are not at the right place
  _' @: Z. e* a& a7 ~/ K, c- m( L. j0 h8 k908534  SIP_LAYOUT     SYMB_EDIT_APPMOD issues with symbol editor and copying pin arrays) U- `7 O" \7 Y8 b% N. o+ ~
908535  F2B            DESIGNVARI       When I try to view my variant file the variant editor crashes/ `) s7 p: |$ f, y
908595  APD            3D_VIEWER        Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b
+ J5 k$ o4 f2 n908849  CAPTURE        ANNOTATE         Getting crash while annotating the attached design
" C1 N6 y7 A( s4 z* C$ W908874  CONCEPT_HDL    CORE             Part Manager - No Part Found error when using CCR# 775788 feature! f( A6 B; @: g
909077  CONCEPT_HDL    CORE             After packaging pin numbers remains invisible even when $PN
1 a1 W' i4 q9 v5 i' G909104  ALLEGRO_EDITOR SYMBOL           Warning message needs to be modified. It does not save the symbol and also not tell the actual problem.* d) x& p- n! J
909417  ALLEGRO_EDITOR REPORTS          "report -v upc" returns 'Segmentation fault' on Linux; i/ h6 ?& Z7 x& U
909635  SIP_LAYOUT     DIE_STACK_EDITOR Add Interposer crashes in SiP Layout, [7 K. \/ L9 `) I9 d4 B
909749  ALLEGRO_EDITOR MANUFACT         Allegro Crash during dimensioning
& V# Q' Y% \0 ~% D$ }# a  K909760  SIP_LAYOUT     MANUFACTURING    Create bond finger solder mask doesn't follow the mask opening as defined in the padstack" g6 ]1 A9 c& T4 D$ i3 k, G, \
909861  F2B            PACKAGERXL       NetAssembler broken within the latest 16.30.031
. z+ l3 U8 H. W: k910006  CONCEPT_HDL    INFRA            Motorola design fails to uprev from 16.3 to 16.5, xcon file is getting corrupted.
- s. K  m2 b; p9 r8 [7 `910141  CAPTURE        NETGROUPS        Modify NetGroup definition does not update Offpage Connector
) V  t: y& I7 b$ @910340  ADW            LRM              Import design in schematic, only 1 page import,  the entire block is getting imported.
8 ^, p' w; x  Q2 h1 A- G9 Z: g910678  SIG_INTEGRITY  OTHER            The Analyze> Model Assignment> Auto setup is not creating/assigning models to discrete components in 16.50 s! J9 T, j1 K$ X5 y( _5 M
910713  F2B            DESIGNVARI       Variant Editor crashes when you click web link under Physical Part Filter window.
% ^/ |8 P$ B3 ~- I1 B910936  F2B            PACKAGERXL       ConceptHDL subdesign net name is inconsistent, g, R" B" D% [; V- m# A
911530  ALLEGRO_EDITOR SYMBOL           Package Symbol Wizard does not create symbol with the name given  X/ h1 E- q$ ^$ B- P3 ~& g) y, r
911631  CONCEPT_HDL    CORE             DEHDL crashes when opening a design, \5 B' i, J" J  F
912001  ALLEGRO_EDITOR OTHER            option_licenses entries are made in allegro.ini even when not set as default
* N1 \1 b  S3 f, S2 G- N0 C8 C7 Q912459  F2B            BOM              BOMHDL crashes before getting to a menu
+ k( j% n: w( A913359  APD            MANUFACTURING    Package Report shows incorrect data
+ a# d% B' O* x- A$ @3 z6 w- a& j7 q4 K
DATE: 06-24-2011   HOTFIX VERSION: 001) l6 w3 S' p* z' x
===================================================================================================================================4 m& v) P0 M, B0 \+ k
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
: }# ]  o- |% C" K# X===================================================================================================================================7 T! y5 C0 J7 y, u3 a2 v/ D* k$ }: [& e
293005  ALLEGRO_EDITOR DATABASE         Allegro crash when attempting to move mech. symbol
8 e& O6 A4 h* m9 B" l+ @- P8 `" u298289  CIS            EXPLORER         CIS querry gives wrong results
& U) Y. a5 O, g( h! j2 i366939  ALLEGRO_EDITOR OTHER            Cannot attach refdes on silk subclass with add text9 v. K) m: c; A" p9 q; F
432200  ALLEGRO_EDITOR MANUFACT         Fillets with an arc are required for Flexi designs( M/ |; b( o/ j; j- F+ n; J4 b
443447  APD            SHAPE            Shapes not following  the acute angle trim control setting.. s! A) x2 p7 X9 Z' P* k7 W
473308  PSPICE         AA_SENS          Passing variables to lower level blocks using subparam1 ]3 n9 p# ^8 k8 B! C8 a
517556  PSPICE         AA_SENS          Advanced Analysis does not support variables being passed down the hierarchy0 A7 G$ u% E! s1 \2 P% Q4 ?
548143  ALLEGRO_EDITOR SHAPE            Dynamic shpe on Etch TOP will not void properly.
' c$ ]4 ?0 _/ {% B& R606959  ADW            COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart
, n# R8 u$ m, j9 F616466  ALLEGRO_EDITOR SHAPE            Solid shapes are not getting filled# q1 O# [) I" V* O+ d2 o" k% R
641358  SIP_LAYOUT     DIE_STACK_EDITOR Request for Via and Multi Layer Pin support for DIE stack Area (blue region)
9 Q3 G+ A% T6 j& W$ [6 Q644122  SIP_LAYOUT     OTHER            SiP Layout - xsection -  ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor
1 u- }, Y  G. |& a6 D/ e: Z* z645816  ALLEGRO_EDITOR SHAPE            Slide a cline all removes gnd shapes on board" Q8 B: W: s9 B; C  g& b$ P
725355  ALLEGRO_EDITOR SHAPE            User can not voided Logo correctly.: ~% ~! [  Z9 ^; n& h
763569  CONCEPT_HDL    CORE             Display status of Hide/Show unconnected pins icon in DE HDL UI+ b1 s$ W" W/ K) F
770021  CAPTURE        BACKANNOTATE     Changing pin group property after pin swap resets pin numbers% g0 {, w3 a' b0 e, O- c
792126  CAPTURE        PROPERTY_EDITOR  Attempt to change display for occ prop resets0 x5 _0 x' f  S
799014  CONCEPT_HDL    CONSTRAINT_MGR   concept2cm errors not shown in export physical after hier_write
4 l% z5 q$ V+ U4 ?* `803147  CIS            LINK_DATABASE_PA Link DB part should not change RefDes of multi package part
/ Z* h: Y6 [* h8 C. V) P804240  PSPICE         DEHDL            Problem in simulation result for a multi-section split part.8 V( L6 E) A( ]1 }; l' U+ d
809118  CAPTURE        NETLISTS         ENH to compare two schematic Capture designs" Z$ L7 U3 g% f# L3 L" K
816568  ALLEGRO_EDITOR SHAPE            shape disappears when update to smooth.. State no etch
4 U$ z5 f( i. h5 l) |! `830053  CAPTURE        STABILITY        DXF export fails if schematic folder name as /
7 }3 [4 h+ R4 P7 e4 Y( ^/ ]832108  ALLEGRO_EDITOR SHAPE            Shape void incorrectly.
( t% `! N7 p' l/ R% G# c- V833542  CONCEPT_HDL    CORE             PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL
( }" N) z9 M' O9 h6 }# S0 G2 v- W3 J/ S835777  CIS            DERIVE_NEW_DB_PA For XLS, donot display table as worksheetName$worksheetName to avoid 8012 error
5 y0 N! R- W  K$ I837640  CIS            GEN_BOM          date format of CIS BOM has broken macros of 16.2 in 16.3 version' ~" j$ I3 @9 _9 ]$ k8 ~( O
844074  APD            SPECCTRA_IF      Export Router fails with memory errors.. O' ?  T3 K7 q5 w+ Y" ~5 T# }
851595  CONCEPT_HDL    CORE             Pin numbers overlap on the pin and increase in size+ v% M) w7 w% j9 V
852832  CAPTURE        BACKANNOTATE     Why is Capture crashing with Mentor back annotation?
' A- @, F0 q& G& t% h( L) b& ~7 h" p855015  ALLEGRO_EDITOR OTHER            The rats are NOT connecting to the ends of the clines like they should be.9 ?# G8 v3 z  K9 C7 M
859883  CAPTURE        NETLISTS         ENH to compare two schematic Capture designs4 Y/ J9 J- @: I. v' n
866009  SIG_INTEGRITY  OTHER            Net with Pull-up/down should not be used for Diff-pair.
8 f$ x, M3 S' e3 H( S2 y866830  SCM            REPORTS          Multiple lines added as separator between title block and report header instead of single line# K7 \1 h& `. ]" l& U: C& g
866833  SCM            REPORTS          Extra indentation is left in the left side of the report when the Line Numbers are set to OFF0 J5 G* b* U0 E9 ?1 E, A- Y1 i: @
868618  SCM            IMPORTS          Block re-import does not update the docsch and sch view, a. j4 w. J( `; f7 J2 {( h4 o
873402  SIP_LAYOUT     LOGIC            pin swap for co-design die in SiP$ Q, T1 f9 H6 [" I( D* f' q( ]
874010  SIG_INTEGRITY  OTHER            PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property.
# W& M) F0 s7 ]5 T+ o874400  ALLEGRO_EDITOR INTERACTIV       Flip mode issue with move command5 ]4 r# @' Z) q9 d$ u# S& M
874966  ALLEGRO_EDITOR INTERFACES       Placed mechanical component do not get Ref Des or part number in IDF file
/ h' M' T% J+ F- `( M875709  ALLEGRO_EDITOR REPORTS          Film area report generated incorrect data at l1
9 ?- g, f3 b$ d% ]4 n8 a876275  CONCEPT_HDL    CONSTRAINT_MGR   Constraint Manager not retaining target net0 `$ N6 H7 n5 N" a0 Y, \7 W
879361  SCM            UI               SCM crashes when opening project+ a) t" L) r: p- q* G; [/ v
879496  CONCEPT_HDL    OTHER            Customer wants to have the tabulation� key as separator in HDL BOM.- V" N& W, z& m) E* w
879514  PSPICE         AA_MC            Monte Carlo to handle equation as comp VALUE.' k$ N: W5 ^1 u6 u; M5 S: H
881845  ALLEGRO_EDITOR SHAPE            Delete island deletes complete shape9 E% G# S) Z" K: M* u4 k+ j
882413  PDN_ANALYSIS   PCB_PI           PDN Analysis should support routed power nets+ z: b5 A! Q! n& ?# s. c2 r' [
882427  PDN_ANALYSIS   PCB_PI           PDN Analysis target impedance should have a variable multiplier9 w  V/ _+ p% B0 n& y
882567  SIG_INTEGRITY  OTHER            PCB SI crash if boolean type prop was specified to VARIANT env." k3 ~' T1 ]# ]5 y+ }; B3 I) X" l$ a
882644  ALLEGRO_EDITOR PLACEMENT        PCB  Place Replicate Function automatically match Enhancement! q7 U7 S! j( b+ P! M
883164  ALLEGRO_EDITOR INTERACTIV       Vias marked fanout moves away from position when moving component
9 Q( p& I/ M2 I0 ^+ L  j883224  SIG_INTEGRITY  SIMULATION       crash while reflection simulation from Constraint Manager
" z' E7 e1 r% Q* u" s9 y/ {" K0 k883760  PCB_LIBRARIAN  METADATA         Incorrectly formatted revision.dat file in the metadata folder
9 G  J$ ~) O8 r8 n4 A6 W) b885391  SIG_INTEGRITY  SIMULATION       RLGC data sampling algorithm and w-element interpolation.
2 h( w6 U& C; X: `. E' S2 j6 U7 `2 e885849  ALLEGRO_EDITOR MANUFACT         Silkscreen Audit cannot find Solder mask for the text string, H' T9 x% A* j
885996  SIG_INTEGRITY  OTHER            The effect of sn_maxwidthlimit user preference is not seen in cross section impedance calculations
/ L- S7 J5 z) |7 d" y0 ^1 F' M886090  ALLEGRO_EDITOR INTERACTIV       Add Arc w/Radius does not snap to grid
8 j! ~5 J% A: m& w; L6 J) |0 @887180  CAPTURE        SCHEMATIC_EDITOR Signals Navigation window doesnt get updated for Buses; _/ u8 `& G8 v2 q' F2 I8 r4 x
887442  APD            SHAPE            Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails.% ^3 T) z3 z8 |) s6 g  W$ b
887578  SCM            AUTO_UI          Component Replace pops-up the DSPANE-204 Message
4 H4 r5 @& M8 M887926  SIG_INTEGRITY  GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane." L5 t! M# z- [8 p
888414  SIG_EXPLORER   OTHER            View Trace Parameter display the thickness of dielectric incorrectly.( R! k$ I9 z8 |5 e" v2 @  P5 D2 G" T
888600  CONCEPT_HDL    CREFER           Cross References not added to Schegen schematic: _" ~0 z; v, j9 q* z+ N2 a
888679  SIP_LAYOUT     SHAPE            Can't create the Dynamic shape on layer M1_sig without unwanted horizontal openings appearing.; {) E+ Q; H) t
888804  ALLEGRO_EDITOR OTHER            Fillet will become static shape after import from partition board./ q3 ^  `0 ]) L  U2 M; H
888945  CONCEPT_HDL    OTHER            unplaced component after placing module7 j; |& i7 L: v9 L
889222  ALLEGRO_EDITOR SHAPE            Allegro freezes/hangs when adding shape as Polygon with OpenGL ON.
3 q2 [6 e: D" c1 }889365  SIG_INTEGRITY  GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3& B3 j8 M0 V/ }) G
889404  ALLEGRO_EDITOR OTHER            Incorrect pad size for Top conductor padstack written to column 59-62.3 `, R$ @4 A4 M, b( @) z
889426  CONCEPT_HDL    CHECKPLUS        CheckPlus does not find single node net
) ?9 K8 I- n" _. U) A6 l889636  ALLEGRO_EDITOR MANUFACT         Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form
: m4 `" [8 T* S6 k3 P8 d3 M891235  F2B            PACKAGERXL       Packager crashes without creating a pxl.log file
7 e" |, {8 J- `) ~( s" ?891292  ALLEGRO_EDITOR SHAPE            arc routing causes weird undesireable shape fill performance
2 ]$ s9 |5 Y8 T# X' u) K891856  ALLEGRO_EDITOR EDIT_ETCH        crash when sliding diff pairs
/ @, T9 Y/ ^% i: n. ]892375  ALLEGRO_EDITOR PLACEMENT        Place Replicate Update disband other groups, irrespective Fixed property added or not.7 f3 a. B2 [7 m9 A
892455  ALLEGRO_EDITOR SYMBOL           Why the overlapping pins are not reported with DRC?
5 o$ n- R0 L4 U8 _3 e+ l892541  SIG_EXPLORER   OTHER            Export/Import layerstack through the technology file is changing the layer thickness
+ `0 v" p4 s2 O! B; X+ s892766  APD            WIREBOND         Excuting Finger moving cannot push aside finger to move with together by shove all mode3 C+ u' w# I: u! P9 [& Z
892907  ALLEGRO_EDITOR DRC_CONSTR       DRC not reported for etch_turn_under_pin violations6 y- z4 g6 y0 D5 S9 u$ S2 c
892963  ALLEGRO_EDITOR SKILL            Bad shape boundary created after axlPolyOperation 'OR9 o$ h! n3 t/ a0 [3 D
892964  SIP_LAYOUT     LOGIC            Request that Edit Parts List use Dashes "-".
( {/ x; T) t- j1 H+ g! g; m' A893295  APD            WIREBOND         Why move wirebond command does not shove wirebonds? This result in drcs.
/ b" p: r: Q# `% T) \5 I893706  CONSTRAINT_MGR OTHER            On line DRC hangs on partitioned board5 _, w3 G8 m. D6 P/ L3 ^7 c
893743  APD            EDIT_ETCH        Route behavior when spanning pads not as expected.
8 z. |0 p* ?; }9 E7 K; t& s893783  SIP_LAYOUT     OTHER            Padstack Design Editing update File menu with a Update to Design and Close instead of 2 operation4 I3 C  f3 D) f8 T, f
894456  ALLEGRO_EDITOR REPORTS          Request Net names be added to Propagation delay lines of the DRC report., Z. e! [) ^7 S" \
894499  SIG_INTEGRITY  LIBRARY          Tool crashes when moving a cline or selecting the Info icon with OpenGL on., [2 r' D) O) {, O' F, o
894582  APD            SHAPE            When making a dynamic xhatch Via shapes surrounding are abnormal.  w+ L+ r" _# K2 x
895542  SIP_LAYOUT     WIREBOND         SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON  j9 n  v2 x! S. x9 h
895591  ALLEGRO_EDITOR PCAD_IN          Importing PCAD file fails to get to the point where we can map layers- q, H, I/ U) i) a  I
895757  APD            ARTWORK          Import Gerber command could not be imported Gerber data
; L6 B! V0 M+ z# R! }$ a, b6 o895964  CONCEPT_HDL    CHECKPLUS        The CheckPlus command getFileSubstrings is not working correctly
9 E5 z) T5 d6 `5 B( h: X% K896428  SCM            UI               Changed Ref Des value not maintained in DEHDL block when part is replaced
5 ~; @5 e/ F+ O8 N8 |896655  CAPTURE        EDIF             Import/Export Design of Hierarcy design with OrCAD Capture
# x: ?. ?9 J& {+ h4 i896846  CAPTURE        IMPORT/EXPORT    Import edif2cap and capture is crashing
# }& D* L& _; D3 Y( }4 Y897155  ALLEGRO_EDITOR REPORTS          Copper coverage in L2 and L7 looks like the same but film area report had large gap.% E& V- v- |7 O9 C
897654  CAPTURE        EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.
8 }5 i; D( p- G5 c3 S+ V* H899344  RF_PCB         BE_IFF_EXPORT    dlibx2iff does not provide the component boundary drawing- ?1 d$ B; c# @3 i( l3 g* T7 A
899629  CONSTRAINT_MGR OTHER            ECset for Total Etch Lenght is not present in OrCAD Prof1 p( Q' t" S$ W5 L4 o* \' {% m, W
900175  CONCEPT_HDL    CONSTRAINT_MGR   Few Xnets are lost from Match Group after packaging and importing the netlist to board file.
/ B; ?7 ~8 S! N* o2 h8 k  c900481  CONCEPT_HDL    CORE             Genview creates a larger symbol without taking the no. of pin in consideration; F& B1 u2 R* U+ x3 x% o3 u
900813  ALLEGRO_EDITOR DRC_CONSTR       With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable.
  _! Y2 o) o2 d& B, j3 Y; ?/ q900905  PSPICE         STABILITY        Simsrvr crash and RPC Server unavailable error while running simulation.
% X" J+ F! Z' O4 ^( l* L7 X$ V901783  CONCEPT_HDL    CORE             CDS_PART_NAME is annotated on the schematic canvas after running back annotation in 16.5
( O" @1 r0 I* C0 q0 V. w901909  APD            EXPORT_DATA      The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong% j# t/ o0 `8 h- ~, c3 h* ~: o
901987  CONCEPT_HDL    OTHER            SPB16.5 zoom fit does not center the page while ploting the schematic page
' g, I% e1 n  `7 ]6 P5 |! U902133  CIS            OTHER            The visible part property value are being shown very distant from part graphics on schematic/ k( p( b3 i+ D% W
902166  SPECCTRA       ROUTE            Specctra crashes when reading in "bestsave.w" file
8 g2 b( _) g" g! \3 X" M. q' N902170  ALLEGRO_EDITOR DATABASE         Diffpair Issues with OrCad PCB Designer Professional
8 z! W  X9 j; U: ]7 x902177  CONSTRAINT_MGR CONCEPT_HDL      Option to view the layer thickness in CM worksheet through worksheet customization# d8 e" T( F4 N' F& r
902463  ALLEGRO_EDITOR INTERACTIV       APD crashes when we click ( show element ) on certain components/ E0 ?" o: _+ V8 L
902621  CONCEPT_HDL    OTHER            Design Differences (vdd) Crashes
/ D& z" v7 e6 g. p4 J902909  APD            WIREBOND         die to die wirebond crash
! ]7 o- U% e3 O+ R$ Y2 w902933  ALLEGRO_EDITOR PADS_IN          Pads_in fails while reading PADS ASCII file body
$ W6 C' f+ o3 P: p8 S903284  PDN_ANALYSIS   PCB_STATICIRDROP IRDrop voltage gradients are plotted outside of the PCB outline
: d" l% J( p& [9 D& O* T/ ]903680  CONSTRAINT_MGR ECS_APPLY        Constraint Manager not passing all hiearchical member objects to a custom measurement.) X7 P+ C# f" ^* S9 c
904403  ALLEGRO_EDITOR DATABASE         Allegro crashes when refreshing module
作者: penny190    时间: 2012-2-21 15:01
有沒有搞錯~~一個月出了兩個HOTFIX( t; H( g$ X8 p/ k' i5 ?9 i4 L( j% f$ u
到底有多少問題
作者: cxyjoe    时间: 2012-2-21 17:40
没看到下载链接啊
作者: jingjing4996    时间: 2012-2-24 18:21
什么东西
作者: ice-river    时间: 2012-2-24 20:03
乱七八糟！
作者: ice-river    时间: 2012-2-24 20:04
给个hotfix链接者硬道理！！
作者: zhangyg    时间: 2012-3-1 17:17
有链接吗？
作者: 蛋炒翻    时间: 2012-3-1 18:45
秘密收藏
作者: ACTODC    时间: 2012-3-2 11:02
这个是什么啊，是补丁的内容吗
) h) D3 R4 t6 Q7 m' Z6 ^+ @
作者: promissingwh    时间: 2012-3-2 16:50
看起来好象是好东西，有点儿像命令，但是不知道用来做啥的呢？
作者: meimei5192    时间: 2012-3-8 15:09
提示: 作者被禁止或删除 内容自动屏蔽
作者: piedgogo    时间: 2012-3-8 15:17
本帖最后由 piedgogo 于 2012-3-8 15:19 编辑 . L  q6 x) K1 h$ d8 r7 S0 s
9 E" \% i) y: y9 _* w' T/ k- u" `
噗，没认真看
作者: yangtse427    时间: 2012-3-9 09:08
看不懂
作者: kbhf518    时间: 2012-3-12 22:27
表示压力很大 啊！
作者: hellojazz    时间: 2012-3-12 22:44
这是什么
作者: wuyinhe    时间: 2012-3-13 08:41
是什么呀
作者: xjlovex    时间: 2012-3-13 18:30
這是個什麽情況啊····求解釋
作者: lolen    时间: 2012-3-15 14:22
1. j1 R" |" S8 D9 S$ o3 S; ?! n+ J  Q
作者: tuzhiquan    时间: 2012-3-15 17:14
:'(
作者: s59710210    时间: 2012-5-21 11:31
?
+ p7 D6 S4 K: R3 H: {# f
作者: d10miao    时间: 2012-5-21 13:19
什么东西？
作者: smileduty    时间: 2012-5-22 21:04
这个是你安装补丁以后，在程序\Cadence\Release 16.5\README CCR这个文件里面的内容，就是更新说明
作者: Vincent.M    时间: 2012-7-21 12:47
什么东东？
作者: xiyuziju    时间: 2014-12-23 16:53
这些是错误吗，有没有相应的解释造成的原因和解决方法、
作者: winson_wei    时间: 2015-10-28 17:02
发课》法克：伐客？
作者: maikll    时间: 2015-11-2 13:27
什么情况， 不懂



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