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具体更新的内容我也不清楚！呵呵！作者: gagmeng 时间: 2012-1-12 08:04
多谢共享，这更新实在是比较快，跟不上了啊作者: lae129 时间: 2012-1-12 09:09
多谢了！作者: rainbowII 时间: 2012-1-12 10:54
谢谢分享作者: sharpcolin 时间: 2012-1-12 11:11
都更更新了什么内容作者: tester1018 时间: 2012-1-12 17:16
多谢分享~作者: interrupt 时间: 2012-1-12 17:58
好东西作者: zlei 时间: 2012-1-12 18:34
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DATE: 12-8-2011 HOTFIX VERSION: 041. t4 _, `- ~7 d$ C
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CCRID PRODUCT PRODUCTLEVEL2 TITLE& s' x) m% W) f d0 P$ a5 u* r: n+ }
=================================================================================================================================== % a/ F6 m# j6 B- _875695 SIG_EXPLORER INTERACTIV Enforce Causality check box doesn't work. # y/ z( r! L R( Z" H944006 ALLEGRO_EDITOR EDIT_ETCH Vias added to shapes behave differently4 b% r, R/ Z! h6 X
946293 CONCEPT_HDL ARCHIVER Archiver hangs if there is a whitespace at the end of the path of cref.dat% U& W3 ~+ }1 M I4 L5 Y5 r2 s
951919 ALLEGRO_EDITOR OTHER Exported package symbol soldermask and pastemask padstack locations not the same as original% c; u9 Z% G# n1 a- B4 i7 B" x
952057 SCM PACKAGER Export Physical does not works correctly from SCM! z# h0 ^& i& [5 m
953018 APD REPORTS Shape affects Package Report result., z5 D6 v% ~$ b! k
953279 SIG_INTEGRITY LIBRARY mkdeviceindex is adding dml file listing in env file4 B) T' O: [$ W6 @- m
953827 ALLEGRO_EDITOR EDIT_ETCH Snake Breakout function crashed Allegro 4 x6 a& u m1 p; k0 s# Q; H953917 CONCEPT_HDL ARCHIVER archcore should handle errors correctly & f5 K1 f6 B3 _* k$ T953971 ALLEGRO_EDITOR MANUFACT NC Drill files not generated correctly when using the option "“separate files for plated/nonplatedholes”; G' s! w% G$ \2 e+ {
954055 CONCEPT_HDL CREFER Crefer fails with UNC install path & ]4 L. K' u- ^* P# b954858 CAPTURE LIBRARY_EDITOR Closed polyline used in pin shape is not appearing while using custom pin in part.4 R" B8 b- Z& b4 L: }
955029 CONCEPT_HDL CORE custom text font size not recognized in symbol view ! m' S6 x* u& X% @2 u# z955133 SIG_INTEGRITY FIELD_SOLVERS The Field solver creates the differential trace model which is reversed T(D1) and T(D2) of bottom side.+ @) m2 [' T5 Y* M1 ~- K
955299 ALLEGRO_EDITOR DRC_CONSTR drc text to smd pin does not work any more on this database in 16.3 S039 " P. ~2 x4 {# ?3 `6 M955338 CONCEPT_HDL CHECKPLUS Need to change PART_NAME + ~0 X: R S1 @' R0 b956751 ALLEGRO_EDITOR ARTWORK Import Gerber command does not work correctly . d( C; T1 L4 r- X/ d958252 ALLEGRO_EDITOR TESTPREP Resequence testprep with the option - Delete probes too close crashes the design% N/ s6 p% p: q7 v! v
958945 CONCEPT_HDL CHECKPLUS Checkplus from 16.3 is not running with our "Allegro Design Entry HDL XL (16.5 licenses): C$ z5 h n4 q' ]$ y
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DATE: 10-21-2011 HOTFIX VERSION: 0403 g& ^) X" a% v" G& C
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CCRID PRODUCT PRODUCTLEVEL2 TITLE . o9 X+ z. b' B# G+ S5 S c===================================================================================================================================2 w3 q3 o" k- G
735439 PCB_LIBRARIAN CORE PDV Moving line-dot pinshapes by arrow keys breaks the pinshape7 `3 F8 \, ]$ \
935438 CONCEPT_HDL COPY_PROJECT Copy Project changes read-only hierarchical block permissions 9 w: [2 N. d/ Y; a! w935836 SCM SCHGEN ASA crashes when generating Flat Document Schematic8 R5 _2 l* W' t' c
937165 SCM SCHGEN Can't generate Schematic' n" J0 p( ?4 Q
941426 CONCEPT_HDL COPY_PROJECT Copy Project fails - Updating opf view This can't happen! 2 r! y4 C$ p) _; }* o: `" A941814 CONCEPT_HDL CREFER CreferHDL crashes during ScheGen 1 A- z: E* K) S! d942522 CAPTURE GEN_BOM Export in excel check mark doesn't invoked BOM in Excel* L* W# k) Z* Z/ J
943032 SCM OTHER ASA is not passing the correct reuse_module name to Allegro PCB layout. & W7 B1 z1 A5 X5 M, P% D/ _946350 F2B DESIGNVARI Variant Editor rename function removes all components. ^* K- W c' I) x
946419 SIG_INTEGRITY SIMULATION Cannot select component on BoardModel for controller in bus setup form L4 ~- g: R7 ]3 Q* ^6 J% K& S( E947789 ALLEGRO_EDITOR MENTOR mbs2brd crashes during translation on the attached design. , U& R6 F: ~2 S1 J 4 M' c( s5 O: E" Q+ H6 D+ rDATE: 10-6-2011 HOTFIX VERSION: 039 / S8 e9 G$ D! Y ?7 k=================================================================================================================================== 2 ?9 m: ?' t4 G, I: gCCRID PRODUCT PRODUCTLEVEL2 TITLE5 g# J$ I5 A* v9 E9 D& y' p
===================================================================================================================================, ]% H6 ^2 L4 S
841096 APD WIREBOND Function required which to check wire not in die pad center.: K7 N/ |, K8 Z3 c T" B' l
912942 APD WIREBOND constraint driven wire bonding # C% ?8 M0 t! b' k8 c" c' E917887 PCB_LIBRARIAN VERIFICATION Part should not be released if the alt_symbols has errors2 m! K! W2 U! `9 c7 n, `
923315 SIG_INTEGRITY GEOMETRY_EXTRACT crosstalk simulation fails with TMP popup failure3 j, {! w9 ^; Q/ L% H: l
927950 APD DATABASE My customer name their layout cross section subclass name as “wire” in Die type. 8 j# }, ~( x9 u3 p! c! a. S929348 F2B BOM Warning 007: Invalid output file path name1 @6 F& Q$ T/ R/ E; o9 ]% `
930783 CONCEPT_HDL CORE Painting with groups with default colors. q F; z* q5 Y& Y$ U6 B3 u' Y: f
932091 CONCEPT_HDL CORE Prop attached to SIG_NAME property6 K( x" O1 f( b8 s
932871 APD GRAPHICS could not see cursor as infinite 4 V9 t# }1 [: |! a. _933356 CONCEPT_HDL CORE Net prop display size become 0 if it was attached to SIG_NAME prop.- e/ E. ]% C2 o8 m$ w7 z
933532 ALLEGRO_EDITOR COLOR Bad color assign and initialisation during creation of new subclass8 I" D! S3 R @$ d% X
934008 ALLEGRO_EDITOR REFRESH refresh symbol updates symbol text to some unexpected values7 y& N) K+ p$ k$ ?+ c5 e/ T6 P
934533 F2B DESIGNVARI The Variant Editor errors are not written to the variants.lst file. r4 z" C$ f/ ~: c
935911 CONCEPT_HDL CONSTRAINT_MGR Mapping of constraints fails after importing layout constraints% f' `& [: R5 V
936098 ALLEGRO_EDITOR SKILL axlDBCreateCloseShape does not work correctly. 7 S4 L! u: n1 U& ]/ A* v936794 CONCEPT_HDL CORE Unable to select Allegro Design Entry HDL XL/ S; u2 C) |$ s, M! c8 J8 z! y" J
937087 CIS DESIGN_VARIANT Upreved design becomes very slow in Variant view mode. DELEET THE DESIGN AFTER RESOLVING THE ISSUE ) j/ r. j$ r1 ~! h! Q937173 CAPTURE OTHER Wrong license information "UNLICENSED" in Capture >> Help >> About! |- U( e4 I5 Z, `- r6 F. n2 H# X
937290 APD PLATING_BAR Plating Bar checks does not recognize connection made through etchback through shape. & L1 ?( Z# k0 \* A937411 ALLEGRO_EDITOR DATABASE downrev_library reading from one directory and writing to another hangs the command. ; @7 ~7 c: [9 e: W5 `) H* }938143 ALLEGRO_EDITOR CREATE_SYM Why is this Extra Property 'ECSET_MAPPING_ERROR 4 x9 q9 U+ p! Y8 m$ V938281 SIP_RF OTHER export_chips creating bad data when symbol is split and contains V- V+ pins % T) a" u: L, {939918 PSPICE PROBE Print > Preview for output file causes Pspice crash. ' m6 j/ G3 r! }940217 CONCEPT_HDL COMP_BROWSER UCB reports 'No Symbol found for the part') o6 n J( X1 A
! I. k" Q+ k0 }% g' y( n0 Y% Z) ?DATE: 09-21-2011 HOTFIX VERSION: 038" E! O0 R; O$ x: m: W' V9 ^7 \
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CCRID PRODUCT PRODUCTLEVEL2 TITLE j6 y7 A5 P9 w3 @; a8 b2 `. i=================================================================================================================================== # d2 y7 b4 f! e8 y+ C924448 F2B DESIGNVARI Design does not complete variant annotation0 |: S1 ~& f' b5 Y" m: ^+ n. `
927104 F2B DESIGNVARI Tools > Annotate variants crashes when there are ASCII characters in the property values- e' }2 W) [7 I m0 l
928738 PSPICE PROBE Y-axis grid settings for multiple plots1 L, d' { W% t" ~4 i0 H- Y
929284 CONCEPT_HDL ARCHIVER archive does not create a zip file 7 {6 o8 }) W( K/ G$ i" i7 Y9 G930063 ALLEGRO_EDITOR TESTPREP Test prep crash Allego when it can not create pin escape 9 M0 r: m# r H9 G930180 CIS LINK_DATABASE_PA Visible property position on schematic get reset on "link database part" operation & }4 ^8 l& A: U! o1 B. g6 l930355 SIP_LAYOUT WIREBOND about "wirebond add nonstandard" command 9 E% M, q$ U" X# g2 s4 C! A6 U930894 CAPTURE TCL_INTERFACE PDF export doesn't creates property file if some symbols are used in page name/folder name, R9 e, z, {" Y
930978 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin error - Pin is connected to net <netname> not reconnected no longer happens + M8 u" u' l' w7 z" f; k( I, o. `931248 ALLEGRO_EDITOR DRC_CONSTR Match Group was removed if member nets became xnets. 4 ]0 {% o! l0 c+ I8 u+ u931274 ALLEGRO_EDITOR DRC_CONSTR Negative Plane Islands waived DRCs reappear after performing update DRC. 4 s% ]9 f4 d1 f932639 SIG_INTEGRITY OTHER Add Connect command hangs for about 14 seconds and then returns. 2 z# R- B( O+ W4 Y7 n7 \- W6 g933145 F2B PACKAGERXL Add Subdesign list is truncated in Force SubDesign Design Name pulldown 9 b" [' r4 m1 R/ W* R0 n3 l* O# o+ p: S+ ^
DATE: 09-9-2011 HOTFIX VERSION: 037 0 ^" c4 o9 s. x* g* S8 _; E===================================================================================================================================: d+ N f. |+ ~0 ]# d) Y" w
CCRID PRODUCT PRODUCTLEVEL2 TITLE9 y" g, M3 U4 T9 V# e+ }
=================================================================================================================================== 4 C$ W* @- W- ]9 \9 l734687 PCB_LIBRARIAN IMPORT_CSV PDV Generation of entity view fails after CSV Import ) H- f h3 _, v5 A' u, J( z' P% r; I734718 PCB_LIBRARIAN IMPORT_CSV PDV Import CSV corrupts parts and generates duplicate $PN on some pins m) z" j/ z7 U, Z6 P3 k" ` \820131 CONCEPT_HDL OTHER Moving symbols to other page will make Allegro components unplaced because logical_path changed. + f0 v M, F3 p" ?3 x0 Z1 J+ Z868712 SCM UI Why can't I modify CAP associated component? ; Z/ Q! b! p: A9 @9 T920327 CONSTRAINT_MGR ANALYSIS The TotalEtchLength predicate in Constraint Manager does not work for a netclass with a bus. - D9 A% d3 k* p2 _* Z922066 CONSTRAINT_MGR ANALYSIS Custom measurement Actual not being cleared when layout changes. & Z8 r( n4 O- F* p4 g9 R925338 CONCEPT_HDL CORE This application has requested the Runtime to terminate it in an unusual way m. T+ E( H+ A: \+ w
925530 SIG_INTEGRITY OTHER Why the single line impedance value for Top and Bottom layers are different for this design?8 _) ^8 e. O" t( _/ G% [4 Z0 g" h
925976 ALLEGRO_EDITOR MENTOR mbs2brd fails to import data& N9 J3 x2 v" [/ w' `. w; n; O
926503 CAPTURE GENERAL Memory leak Capture/Pspice: @& M: ?1 t3 c7 S* k
926887 CONSTRAINT_MGR CONCEPT_HDL Pin pairs lost after Export Physical - M" l# S0 z5 J) @0 y927637 SCM CONSTRAINT_MGR ASA crashes on change root and also performance is too slow. 8 k- y( A% ^6 p! j% v) E) |6 m F$ `928286 CONSTRAINT_MGR INTERACTIV The value of pin-dealy has gone with long match group name. . R) J) D- S4 m4 Q/ r+ n: H+ y( y. ~928483 ALLEGRO_EDITOR DRC_CONSTR Running Update DRC removes Via List DRC Error when via is actually not in the list ( O6 t; [3 r9 L* N3 E929174 ALLEGRO_EDITOR OTHER Display mesure get different result between 16.5 and 16.3- k' \9 `! e* Y& g) f9 Q
929656 ALLEGRO_EDITOR PADS_IN PADS translation fails with Microsoft Visual C++ Runtime Library error0 B8 E. ^$ s4 J5 I$ Z
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DATE: 08-26-2011 HOTFIX VERSION: 036 . B+ x0 n5 p9 D===================================================================================================================================- I! v" `; N( p( Z$ e! T* {/ _
CCRID PRODUCT PRODUCTLEVEL2 TITLE # L! |! i5 S W9 T=================================================================================================================================== + E) t# w8 x# c8 r I! H% f891079 CONCEPT_HDL CORE DEHDL crashes with large number of commands in Winodws mode# Y9 e: c$ ]+ }9 s
909595 APD LOGIC Inconsistency between export die text out and show element after pin swap* {2 @$ q2 s7 `9 \' a
914870 MODEL_INTEGRIT OTHER mergedml fails to merger 2 DML files from the model integrity* \0 b/ E2 ^! f
916321 CAPTURE GEN_BOM letter limitation in include file7 F$ @ Y3 [( n ]! L" V
917967 ALLEGRO_EDITOR REFRESH Update symbol resets refdes location for bottom side components only.7 |' a" A2 x: [: j) K
919976 APD DATABASE Update Padstack to design crashed APD.) j+ C0 @4 [, ?2 T; v
922519 ALLEGRO_EDITOR SKILL add_bviaarray command fails for some clines but not all 7 X5 v, `& I8 F: W. W+ O; O923910 CIS PART_MANAGER Copy & Paste operation from Part Manager copies properties only to first section of the part.* K1 R C( ]/ s7 T7 ^( H6 {1 W8 `. `
924458 SCM OTHER Project > Export > Schematics crashes7 y. |$ ]- o) n3 x- o5 P( g/ f* d5 A
924621 ALLEGRO_EDITOR SHAPE Dynamic shapes are disappearing upon updating them to smooth. f, i$ H0 W0 }4 J" ?6 P f
925193 SIG_INTEGRITY FIELD_SOLVERS Diffential Impedance (DiffZ0) values computed in the layer stack-up is incorrect# T4 ], x, G) Z
926443 CONCEPT_HDL CONSTRAINT_MGR In new 16.3 "035" ISR Concept2cm will crash with error. * p" U- T9 M: N' R& S# n) H0 }2 ^& Q" ~" r$ K2 e6 U5 H
DATE: 08-12-2011 HOTFIX VERSION: 035& U$ b; J% R. @5 K* T! D
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CCRID PRODUCT PRODUCTLEVEL2 TITLE0 t; I4 v4 r2 D7 {) X# e
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861956 CAPTURE IMPORT/EXPORT V16.3 is not respecting if the net names were written in LOWER CASE or UPPER CASE in EXPORT FPGA. ' E2 N% P; w# s2 y/ Z868216 PSPICE MODELEDITOR Encryption of subckt names, internal nodes, comments: T3 `4 z3 s; h/ u, C0 D' N
870247 PSPICE SIMULATOR Encrypt a model and simulate it, info about inside nodes being dumped in the probe file! \: a; w3 X& X! }
874010 SIG_INTEGRITY OTHER PCB SI crashes when the Xnet is extracted with VARIANT_TO_IGNORE property. `( _0 ?* ]" \* q8 Q8 D G
882567 SIG_INTEGRITY OTHER PCB SI crash if boolean type prop was specified to VARIANT env. ! l( W# o: Z# `' T, ~, |! O7 s895902 RF_PCB OTHER Alphanumerical allegro pin numbers are unusable in ADS 2009 Update 1/ A7 K8 B2 E, ?3 U1 ?8 j- X
895919 RF_PCB OTHER Round trip Allegro to ADS to Allegro requirement9 p( o% r' K" ]. G. P8 x' H
903102 ALLEGRO_EDITOR OTHER Zcopy shape command for cline seems not to work correctly. + F; C/ w+ k! J# Y: J1 I905533 ALLEGRO_EDITOR INTERACTIV Pin numbers for components on BOTTOM Side are moved in Preselect mode,when the BOTTOM layer is invisible # I" @9 S' U% | ]% O) c0 R$ m% F905562 SIG_INTEGRITY SIGWAVE Noise margin seems not to be measured correctly with Eye Measure function.8 }- M; Q$ k/ C+ n0 s
905777 SIG_INTEGRITY SIMULATION User gets popup message that halts an analysis until it is acknowledged / n/ i I" Q7 l1 B, \) p915630 PCB_LIBRARIAN OTHER Error when running SI Model Interface Comparison using IBIS models * A0 A @" x+ |* b; i0 }' F: m& ]& N915755 CONCEPT_HDL CONSTRAINT_MGR Cannot view net in SigXP ' S }5 P9 Y# o5 l( k% @0 U' X+ A916462 ALLEGRO_EDITOR DATABASE Edit>Split_plane>create hangs Allgro PCB Editor( `6 g6 P8 t& v# {: s7 z, i% ]% O% S
916495 ALLEGRO_EDITOR INTERACTIV Pick selects components from invisible (Off ) layer! Z. Y' \& \. q3 a+ I, y; P
917434 APD OTHER Stream out GDSII has more pads in output data.1 G8 ~2 H1 [, V' o7 Z$ a% T
918187 CONSTRAINT_MGR OTHER Missing acGetTotalEtchLength predicate. * x3 ?: x5 n" j0 D4 A' L1 `918576 CAPTURE DRC Incorrect DRC is reported for visible power pins which are connected to power symbol' ~$ Z& Y5 X1 m) t3 G* ~0 _9 [
919343 ALLEGRO_EDITOR PLACEMENT Place Manual is crashing the board file # q" {# h2 V. r8 a. G/ Z919481 CONCEPT_HDL CHECKPLUS CheckPlus isGlobal function is not working3 N7 r9 Z9 M# [9 a: j
920712 ALLEGRO_EDITOR ARTWORK Program has encountered a problem ... error when creating artwork! [7 P* o3 ?1 y' D3 V. n
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DATE: 07-29-2011 HOTFIX VERSION: 034 5 ?) D6 a8 a) Z" ^: @6 P===================================================================================================================================' k/ L6 }# |$ k: Q" d$ p
CCRID PRODUCT PRODUCTLEVEL2 TITLE 2 \: B1 W) C# {' w===================================================================================================================================! b$ ^) u# ^+ O/ q( x
882677 EMI RULE_CHECK bypass_plane_split fail if BYPASS_XXXX_EFFECT_DISTANCE% q8 A, l& y7 D+ H
897196 CIS LINK_DATABASE_PA Schematic Contents are not shown in CIS window while link Dbase part for parts placed from library $ c& k6 Z) G, n: O6 ]902066 ALLEGRO_EDITOR DRC_CONSTR Shape in Region not follow the constrains# ]# _/ p" D' S
903719 ALLEGRO_EDITOR INTERACTIV Nets highlighted by netclass cannot be selected on the canvas to dehilight ' b7 t" w' E; @5 W$ [" A4 S903898 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV move symbol graphics and Undo causes corruption in graphics' Z$ @* e# F: Y" i# z+ {
904287 ALLEGRO_EDITOR ARTWORK some cline with arc is missed, when creating artwork.1 A! ]) e: ^, ?& _ J2 ]# l# P
905796 CONCEPT_HDL CONSTRAINT_MGR Fujitsu CM issue inaccurate concept2cm diff pair issues' z' o2 T3 O9 I% Y c& z
907885 SIG_INTEGRITY OTHER Matchgroup targets lost when importing netlist to Allegro layout in HF31 $ Y4 c7 h3 H, S* J908057 CONCEPT_HDL CORE DE HDL crash with the cut and paste of a signal name 0 ^0 |% b ]- G6 F4 A0 Z908060 CONCEPT_HDL CORE CTRL+LMB Option not working correctly in 16.37 a# b0 c9 f6 U" h) g
908680 SIG_INTEGRITY OTHER Extra prop delay due to resistance8 U; p& Q) H N; e2 D
908874 CONCEPT_HDL CORE Part Manager - No Part Found error when using CCR# 775788 feature ! p2 U9 H; X/ m v) C3 o909635 SIP_LAYOUT DIE_STACK_EDITOR Add Interposer crashes in SiP Layout , B, H$ U. Y/ r) d910713 F2B DESIGNVARI Variant Editor crashes when you click web link under “hysical Part Filter” window. 0 U) u! d8 L. G- A! O910936 F2B PACKAGERXL ConceptHDL subdesign net name is inconsistent/ `6 g6 k7 H1 u- d
911415 ALLEGRO_EDITOR COLOR assigned color cannot be removed4 d8 y0 [# D/ m4 N! X1 _. f% W
912343 APD OTHER APD crash on trying to modify the padstack& h* ^0 `8 b, d
912384 PCB_LIBRARIAN CORE PDV Symbol Editor often freezes when moving groups objects by arrow keys% |9 {+ I: o' j' [2 u% g1 H. l
912459 F2B BOM BOMHDL crashes before getting to a menu 3 m0 \7 U* S# j5 a* j+ [912853 APD OTHER Fillets lost when open in 16.3. 1 K% |6 T4 b+ C; `% Z* e7 a913359 APD MANUFACTURING Package Report shows incorrect data" g0 W: }9 x- j+ C5 m
913521 ALLEGRO_EDITOR SCHEM_FTB Netrev error “(40) Object not found in database” for a part which is packaged correctly in FE - A- U" N R# d- e3 S+ P: t- A# K913586 ALLEGRO_EDITOR ARTWORK Cannot create the drill figures in this design. ! m2 v; v5 ^) d) y914009 ALLEGRO_EDITOR DRC_CONSTR Diff impedance worksheet showing almost zero impedance for differential pair in attached testcase.3 P+ T1 i. x6 O5 V1 m0 k
914558 ALLEGRO_EDITOR ARTWORK Gerber6x00 output creates unpainted niche in a shape8 b3 A8 C7 D% Z9 L% t& L f
915742 CONCEPT_HDL HDLDIRECT I get a newgenasym error and crash when trying to save the symbol & p! b! e* t2 s [: k* _$ N916469 ALLEGRO_EDITOR REPORTS One Unrouted pin does not show in Unconnected Pins Report 4 D! d# v+ `5 ]: B' {6 Q9 a% f6 A, Y; {1 ]
DATE: 07-15-2011 HOTFIX VERSION: 033 4 |7 Y' D/ n0 ?===================================================================================================================================: b) i3 P! H- c
CCRID PRODUCT PRODUCTLEVEL2 TITLE e8 ^# z8 {% t0 X( f
=================================================================================================================================== 0 f; x! ~) N" o' }746562 CONCEPT_HDL CORE Deleting attribute causes other property value to move/change 6 ^6 q, b3 |( h) f4 n+ K902349 CAPTURE LIBRARY Capture crashes while closing library$ L3 w! `6 F/ k5 @
903171 PSPICE NETLISTER Why Capture is treating hierarchical power ports as floting nets in complex heirarchy designs? # a2 G- h( M4 B! p F# r" T903713 ALLEGRO_EDITOR PARTITION Placement Replication do not work fine in the Design Partition & Z9 W0 W# y" H1 c, M& m905337 CONCEPT_HDL CORE ConceptHDL crashes after Import Design process. 4 L* ?. `& i1 C906153 ALLEGRO_EDITOR SCRIPTS Unable to run allegro script in batch mode on the attached board.# z. b' ?5 H7 A0 \
906517 PSPICE PROBE PSpice new cursor window shows incorrect result. @3 f0 H; H" G9 c
906627 ADW COMPONENT_BROWSE ppt options are not read if ucb is launched from FM. works fine if launched from dehdl. 4 Z4 Q" l1 Y- ~$ t1 O+ E906750 ALLEGRO_EDITOR PARTITION Importing design partition removes the testpoint reference designation6 M9 w3 G' a" @
906874 PSPICE NETLISTER Error less than 2 connections for unconnected hierarchical pin " p* d6 `; F# Z8 a, }2 L907095 F2B OTHER Part Manager does not show Error as Undefined when directive ptf_mismatch_exclude_inj_prop is used 5 |; p. l' y: p! x1 a5 L! H908000 SIG_INTEGRITY OTHER Inconsistence z-axis delay reported on Tpoint when define at via location. 9 j/ m6 R3 u' W4 |& {908595 APD 3D_VIEWER Cadence Design 3D viewer" screen pops up and is all black because the colors have all converted to b- Y* ^6 i3 x4 M; w
908849 CAPTURE ANNOTATE Getting crash while annotating the attached design - z' ]& j8 M( d0 `$ V909760 SIP_LAYOUT MANUFACTURING Create bond finger solder mask doesn't follow the mask opening as defined in the padstack: O/ ^$ ?1 O y
909861 F2B PACKAGERXL NetAssembler broken within the latest 16.30.031+ [. }2 l* U- H/ o& c2 O
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DATE: 06-22-2011 HOTFIX VERSION: 032 " }% g+ B1 ]! {0 J. K7 Q===================================================================================================================================! i) a4 M" T3 o* w+ l
CCRID PRODUCT PRODUCTLEVEL2 TITLE 9 {+ M& A- Y" K+ u$ t' {=================================================================================================================================== . [2 V" b4 V7 R) X& G$ ^+ L774270 F2B PACKAGERXL Require to ignore space in Pattern setting to prevent duplicated Refdes. d0 S( h" R! \% R/ S) H6 ^5 E0 \# y833542 CONCEPT_HDL CORE PDF publisher font is NOT WYSIWIG with respect to what seen in DE HDL 9 `$ D1 W1 _. f! ~1 v893544 ALLEGRO_EDITOR INTERFACES IPC-D-356A netlist issue with BB vias.8 ^# z6 _) M9 @+ {$ d0 {
893765 ALLEGRO_EDITOR PARTITION Mail command not sending out email on Linux platforms. ( G2 k# p: f7 J( ^" m895933 APD DATABASE Update Symbol shifts the center of the Dynamic Fillet and creating DRCs , J: {' s6 T" J897484 SCM CONSTRAINT_MGR No match found for 'fileops.txt' in the search path. a" O5 W, X- F( ?* G8 a: y
899556 ALLEGRO_EDITOR ARTWORK Import artwork seems not to work correctly. $ @4 G h4 h: b1 O& {! m. ]) U* j902959 CONCEPT_HDL HDLDIRECT HDLDirect Error while saving design A* V9 Q( F* Q3 D903680 CONSTRAINT_MGR ECS_APPLY Constraint Manager not passing all hiearchical member objects to a custom measurement.# b9 e) r0 g$ z9 }% m- O# |
904403 ALLEGRO_EDITOR DATABASE Allegro crashes when refreshing module 1 U0 B ^6 i' Z4 y5 j904771 ALLEGRO_EDITOR MANUFACT Pin Number display issue.* ]$ ^' s* c7 l C- w
905144 CONSTRAINT_MGR ECS_APPLY Min Line Spacing is larger than Primary or Neck Gap less(-) Tolerance but No Warning in CM 7 [3 U6 ^+ Z$ ^# V* I* x$ j905273 ALLEGRO_EDITOR MANUFACT Drill legend creates more tables than nclegend creates tapes L& \+ n* ^+ l% F6 P. m905314 F2B PACKAGERXL Import physical causes csb corruption 8 G, m1 o- m, M, E5 D5 W4 y! i1 o7 T" W7 r
DATE: 05-28-2011 HOTFIX VERSION: 031 ' R y# Q2 \6 c=================================================================================================================================== " K L( M; x+ f% {1 L7 ZCCRID PRODUCT PRODUCTLEVEL2 TITLE+ a( L* f2 U6 Z) ^( q
===================================================================================================================================7 L: |5 {5 s$ g0 z* {, g+ m
606959 ADW COMPONENT_BROWSE Key properties with blank values are not getting read in shooping cart 8 i% U i* R* A# P" l i/ x) O644122 SIP_LAYOUT OTHER SiP Layout - xsection - ERROR Adjacent conductive layers are not allowed, but these are diestack layers not conductor, e6 R: L6 V" a
799014 CONCEPT_HDL CONSTRAINT_MGR concept2cm errors not shown in export physical after hier_write 0 g1 c: W: a% ~( o2 G866830 SCM REPORTS Multiple lines added as separator between title block and report header instead of single line) p5 C# ^- T" R0 J9 ]
866833 SCM REPORTS Extra indentation is left in the left side of the report when the Line Numbers are set to OFF5 ^1 ], [+ k+ E3 \
868618 SCM IMPORTS Block re-import does not update the docsch and sch view % H+ {0 ?9 C( A869971 SCM OTHER Lower level hierarchical block schematics missing $LOCATION values 1 n9 ~0 c8 }! s1 Q2 j/ V" r# G$ X877091 CAPTURE SCHEMATICS DSN file size becomes very large after placing picture and not change after deleting it 5 f3 f( z4 v t5 x" q879361 SCM UI SCM crashes when opening project9 e7 K/ T( X& s. B& X# d+ x
879496 CONCEPT_HDL OTHER Customer wants to have “the tabulation” key as separator in HDL BOM. - Z8 q" y$ q. p0 d) B0 `! L$ Y883760 PCB_LIBRARIAN METADATA Incorrectly formatted revision.dat file in the metadata folder ) v/ Q0 d% z: x7 Q( G6 k885391 SIG_INTEGRITY SIMULATION RLGC data sampling algorithm and w-element interpolation.( B6 V% k# t* t. J7 |) c9 H
886007 CONCEPT_HDL CORE All the read only pages are called PAGE1 in our hierarchical design : H f' @! F9 d889426 CONCEPT_HDL CHECKPLUS CheckPlus does not find single node net& L' E0 J1 N: c
892375 ALLEGRO_EDITOR PLACEMENT Place Replicate Update disband other groups, irrespective Fixed property added or not.' J8 ]: N7 L1 Z
892541 SIG_EXPLORER OTHER Export/Import layerstack through the technology file is changing the layer thickness( h: i W6 c7 s4 U5 J u3 r, j" u5 L
893743 APD EDIT_ETCH Route behavior when spanning pads not as expected. $ [' q+ v* X6 K% _7 |3 ~% t894499 SIG_INTEGRITY LIBRARY Tool crashes when moving a cline or selecting the Info icon with OpenGL on. & j& F" B7 } O3 L. l" w894582 APD SHAPE When making a dynamic xhatch Via shapes surrounding are abnormal.# m% {- S/ j1 c9 e9 \" `: N x
895542 SIP_LAYOUT WIREBOND SIP design crashing when moving bond finger using blur mode BLUR_BONDFINGER_PRESRV_CON3 }; J6 Q) I# |+ i$ h
895591 ALLEGRO_EDITOR PCAD_IN Importing PCAD file fails to get to the point where we can map layers, Q* G; w! }, h: d# G4 x
895757 APD ARTWORK Import Gerber command could not be imported Gerber data 1 x2 D$ `7 B; l+ s895964 CONCEPT_HDL CHECKPLUS The CheckPlus command “getFileSubstrings” is not working correctly 9 w! ?- y* T/ Q+ z8 t l896302 CAPTURE LIBRARY Pin spacing option in Generate Part from spreadsheet4 P! F3 X. ]! T+ q
896428 SCM UI Changed Ref Des value not maintained in DEHDL block when part is replaced - E, ^6 j, S$ }/ ^! i8 f, D897362 CONSTRAINT_MGR TDD Unable to create Region Class in Constraint Manager" p' n3 n. v {2 w* Y: l
897654 CAPTURE EE_INTERSHEET_RE Capture crashes on adding intersheet refernces in abbreviated format on attached design.- u& u, P4 b- y/ q- g+ B) d
898941 ALLEGRO_EDITOR REFRESH update symbol moves refdes location of component placed on bottom side6 Q5 E! ^; e" \. L. G, Z
899344 RF_PCB BE_IFF_EXPORT dlibx2iff does not provide the component boundary drawing , ^4 q5 n3 i. u: |2 R- B& ^# G900175 CONCEPT_HDL CONSTRAINT_MGR Few Xnets are lost from Match Group after packaging and importing the netlist to board file. ' w$ |1 l5 z4 N. z1 ^6 C900481 CONCEPT_HDL CORE Genview creates a larger symbol without taking the no. of pin in consideration , _, @# K7 P& q4 ?; u b$ g& ?5 [900813 ALLEGRO_EDITOR DRC_CONSTR With rotated pads, pad (pin - via) soldermask spacing DRC is unreasonable. 6 C, v6 [! p# U900905 PSPICE STABILITY Simsrvr crash and RPC Server unavailable error while running simulation. 5 s* A& f k3 X3 G5 K; H901909 APD EXPORT_DATA The "package_pin_delay_length.rpt" with Z-axis delay turned on seems wrong- p: Y. E5 N$ L5 ~8 y
902133 CIS OTHER The visible part property value are being shown very distant from part graphics on schematic! p: l. K# f' V3 L. m1 N; k
902166 SPECCTRA ROUTE Specctra crashes when reading in "bestsave.w" file 9 o- t3 Z4 ]" H9 F902177 CONSTRAINT_MGR CONCEPT_HDL Option to view the layer thickness in CM worksheet through worksheet customization% Y. h% j- t( n( u! j% K; C
902463 ALLEGRO_EDITOR INTERACTIV APD crashes when we click ( show element ) on certain components: U) m# {; a# ?+ S$ @: Y
902909 APD WIREBOND die to die wirebond crash ' _. p( ? M: N2 g7 ?* A7 I902933 ALLEGRO_EDITOR PADS_IN Pads_in fails while reading PADS ASCII file body - Q0 w k% x! y; X8 B3 }. b" c+ d$ ]/ O9 a6 W& S: {' M+ W, z
DATE: 05-14-2011 HOTFIX VERSION: 0301 N. @9 ]" M( H, b6 j3 ^$ x) N {
=================================================================================================================================== / Z% e) J" ~( O* l' w rCCRID PRODUCT PRODUCTLEVEL2 TITLE 1 [/ Y, y% D" ^. U) `* ^: Q& H===================================================================================================================================, p6 }* x+ w+ t7 ?/ M% h
738247 CONCEPT_HDL HDLDIRECT Generate View hangs 0 v8 _) n8 M* E# y1 K) e; v803147 CIS LINK_DATABASE_PA Link DB part should not change RefDes of multi package part' i1 O! m/ S b' H
837640 CIS GEN_BOM date format of CIS BOM has broken macros of 16.2 in 16.3 version1 n) P/ Y9 I0 h0 G. C
838763 CAPTURE GENERAL Deadlock situation is reached while opening BOM reports ("<something>.BOM" cannot be opened)+ k1 P* x, u% U' I$ |
858245 CAPTURE IMPORT/EXPORT PCAD import does not work in 16.3% C' V2 r7 g, ]* W4 x
860905 SCM UI Part cannot be replaced after it's added ) J$ S% {8 y. L( P869528 CAPTURE SCHEMATIC_EDITOR Refdes increment on copying part is not with respect to occurence value. 0 X, I& ^) k8 D+ A, f873402 SIP_LAYOUT LOGIC pin swap for co-design die in SiP % g9 g3 \, P5 O877994 CONCEPT_HDL CONSTRAINT_MGR Assigning ESpice model to active component with Class $ X& y0 G- B* j& C; N' S. w. O* W883164 ALLEGRO_EDITOR INTERACTIV Vias marked fanout moves away from position when moving component( v- `$ p* U' {+ |" Q% I1 u
887442 APD SHAPE Copper pour of Dynamic shapes on Top layer which contains many existing signal traces fails./ E E _% t$ Y( G# w5 g
887477 CAPTURE NETLIST_OTHER Other netlist is missing some nets and components after refdes changes in the design , h1 U4 ?. o* t& Z) x887578 SCM AUTO_UI Component Replace pops-up the DSPANE-204 Message : x4 B2 y2 u/ d) T3 ~, V887926 SIG_INTEGRITY GEOMETRY_EXTRACT Field solution failed if diff trace on bottom doesn't have reference plane. : X- u4 z7 k3 l9 ~* Q4 Z888414 SIG_EXPLORER OTHER View Trace Parameter display the thickness of dielectric incorrectly.9 _% M' `! \$ l# X# j0 b5 h
888600 CONCEPT_HDL CREFER Cross References not added to Schegen schematic$ o# O0 o3 I) h# S
888804 ALLEGRO_EDITOR OTHER Fillet will become static shape after import from partition board. ! @ W9 O. J' N, K. Q888945 CONCEPT_HDL OTHER unplaced component after placing module + N: a$ i8 I' i; e4 t9 x889365 SIG_INTEGRITY GEOMETRY_EXTRACT top/bottom trace impedances extracted to sigxp are wrong in 16.3 # p p( q5 r% s- @; w" |889404 ALLEGRO_EDITOR OTHER Incorrect pad size for Top conductor padstack written to column 59-62.6 k. x0 g/ J' z' e% d3 F0 a
889636 ALLEGRO_EDITOR MANUFACT Incorrect spelling of "Visibility" in "Film Control" tab in the Artwork Control Form / m/ H# r! s5 l891235 F2B PACKAGERXL Packager crashes without creating a pxl.log file3 H( f$ b/ P" D
891856 ALLEGRO_EDITOR EDIT_ETCH crash when sliding diff pairs 3 I! Z. h) i$ [0 Y7 J" t! n892455 ALLEGRO_EDITOR SYMBOL Why the overlapping pins are not reported with DRC? @ g: B) R* {( h" D& s9 U; B892766 APD WIREBOND Excuting Finger moving cannot push aside finger to move with together by shove all mode 3 L8 T3 ~4 J- O1 f+ i5 c6 t892907 ALLEGRO_EDITOR DRC_CONSTR DRC not reported for etch_turn_under_pin violations# k. B( H" J# o0 W2 d$ r5 r
892991 APD BGA_GENERATOR BGA Text In Wizard creating two refdes text at the same location. - E! r+ ?3 [+ }8 ]3 z$ L893295 APD WIREBOND Why move wirebond command does not shove wirebonds? This result in drcs.2 B9 Y: k6 d8 d
. D s% `9 T& G5 s+ R4 @2 d& kDATE: 04-22-2011 HOTFIX VERSION: 029 0 K0 W) M3 u) I2 u===================================================================================================================================4 n( X6 Z! Q1 l
CCRID PRODUCT PRODUCTLEVEL2 TITLE + o' x% ^# e7 Z# E5 t$ Z# E: V$ d=================================================================================================================================== - o z4 J/ E* \. i5 K& T789198 CAPTURE PROPERTY_EDITOR Newly added user property to a symbol can not be moved on the schematic page.3 W/ }; u, F8 p3 \" `7 T# a! ?
812501 CAPTURE NETLIST_OTHER Extension of PADS netlist is .NET in V16.3. It should be .ASC. 1 ]2 \( s! D2 q, Q; J7 ?, E842161 CIS GEN_BOM CIS standard BOM taking long time4 V0 l) L7 S w0 u3 I: E' k9 |& [& g
844125 CAPTURE NETLISTS Normal and convert view placed in same design don't get netlisted due to duplicate power pin names. 2 g% k% W7 L# G; N* A! H& @847688 CAPTURE PROPERTY_EDITOR Property Editor changes selection on Display , ?5 V4 h+ M& Y851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window. ( [% o3 J8 F7 {862785 CAPTURE NETLISTS RINF netlist with net attributes generetaed by capture 16.3 is not getting loaded in CADSTAR tool & ~6 t2 c5 K8 d868118 CAPTURE NETLIST_ALLEGRO Differential pairs not getting netlisted in hierarchical design.% B7 U8 p) s- h3 d+ ?
880219 CIS GEN_BOM Standard CIS BOM does not viewed properly if underscore presents in Part_Number property' }0 \! @. P% R3 J0 m
881792 ALLEGRO_EDITOR SHAPE Cannot Delete the Islands on the shape. No Error reported. 2 Q- ~( Q0 n1 R) I2 m8 F. e a882128 SPECCTRA HIGHSPEED Difference in length report between Allegro and SPECCTRA5 B* w* Z. V6 W' X, D
883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager' H! N9 B7 V" K/ Y% K: S3 m/ v9 B
883291 SIG_INTEGRITY OTHER Z-axis delay causes incorrect actual values for delay 4 t# i p5 B: v E/ j, J/ n883971 APD EDIT_ETCH APD crashed when I tried to add cline in (-6674.79 -7506.74) via. , `7 y, ^# M. t9 B$ i884061 CAPTURE SCHEMATIC_EDITOR multi-line text zoom doesn't work correctly 0 X7 l1 `7 _) a! u- Z: ?) S884181 ADW DBEDITOR Parts get released anyway without any errors flagged. & Y9 y5 x- e. K& s885019 CAPTURE GEN_BOM Create BOM causes Capture crash with include file7 T" s- L# ~& S/ P
886437 ALLEGRO_EDITOR SHAPE Change of behavior of NET_SHORT between 16.2 and 16.3 7 q. r9 d' e2 u$ x887190 ALLEGRO_EDITOR PADS_IN getting parse error during PADS to Allegro Import/ U. `" T$ D8 V G1 K" _$ V
887348 ALLEGRO_EDITOR MENTOR mbs2brd translator crashing without any error message in attached testcase -v16.3s027 % j; Z0 V0 b' a j' m0 F2 s; N+ I3 O% q8 }# T4 y2 I; R# w; n. w
DATE: 04-8-2011 HOTFIX VERSION: 0284 K' A8 `- J& M6 }5 H H+ J
=================================================================================================================================== ) U3 \) s, ^0 A+ N, J$ }, q8 h$ ACCRID PRODUCT PRODUCTLEVEL2 TITLE 1 H5 P& z) e/ g=================================================================================================================================== z+ `: j: H' ~* h5 S1 _. A704398 CONCEPT_HDL CORE In Windows mode basic shortcuts do not work when in German language 8 l! j) |* q9 f, Q. `771137 ADW LRM LRM reports 'Injected Mismatch' for a value based on capitalization of ptf value# |8 |) u z$ @
872547 CONCEPT_HDL CORE Document schematic - Published PDF is missing Bookmarks : ~+ w, }3 f/ T+ u, n0 _/ z875001 CONSTRAINT_MGR OTHER Click on the Constraint Manager selected net filter icons crash software. + w8 |( E" J# z, _; n. [9 c& I875039 CONSTRAINT_MGR ANALYSIS RPD margin is not calculated in 16.3 - \1 i+ Y! O0 y7 a. H876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net $ V6 P9 v `% d7 Z5 Q% ^$ p5 ~: m877912 APD DRC_CONSTRAINTS Shape to Shape DRC seems to be behaving inconsistenly above 90 um spacing on mcm database. " g u8 I( N* A' U) ?" L. k. s0 U878022 CONCEPT_HDL CONSTRAINT_MGR NO_XNET_CONNECTION is not working unless defined on last discrete before receiver # J! a1 D8 f+ `. r! y878519 SIG_EXPLORER OTHER View Trace Parameter - stripline trace model display incorrect distance to the reference plane7 @9 i" n9 I2 Y# v& \$ V
879529 CAPTURE NETLISTS Misleading bus/pin ERROR [NET0081] message from PSpice netlist3 x: U0 P. e4 }9 f4 n7 o
881455 ALLEGRO_EDITOR INTERFACES Some Drill Figures missing while Exporting DXF 2 J% k/ y$ O+ L881711 ALLEGRO_EDITOR SCHEM_FTB Spacing constraints(Net Class) from schematic are not transferring correctly to the layout % {" w) t4 Q0 k1 w d882277 ALLEGRO_EDITOR DRC_CONSTR Get Bogus (false) "Thru Pin to shape spacing" DRC for Oval slotted pads. 5 c, M3 Z2 m/ f$ X4 V882408 SCM SCHGEN Export physical fails due to netlisting error with the ASA exported schematic( n4 t. k( v1 j5 e) R, G3 @
882796 APD OTHER GDS stream import results in a set of bumps misplaced... possibly rotated 90 degrees- c" @2 Y: `- p: N) h
" C- A# D) M! ~+ W2 d$ m- L$ f+ WDATE: 03-25-2011 HOTFIX VERSION: 027: @5 R5 j3 \. n, g
=================================================================================================================================== 0 x6 v% O9 s" r' r6 mCCRID PRODUCT PRODUCTLEVEL2 TITLE2 c1 g# E( t. c. V
===================================================================================================================================5 r# s5 j3 D; x( F
820901 EMI SETUP Request EMC system.conf file that can be read from CDS_SITE. U8 ^1 c! D/ x* U1 d9 S- k861999 ALLEGRO_EDITOR DRC_CONSTR DRC hang after padeditdb % B, C( E; f3 N9 m862463 CONCEPT_HDL RF_LAYOUT_DRIVEN Rotating and Mirroring RF components in DE-HDL requires RFFLIPMODE property to be correctly updated/ {5 a+ l9 |4 _0 q% F1 z2 c5 [+ A
867223 ALLEGRO_EDITOR SHAPE Shape fill disappears when Negative shape is converted to Positive in Cross Section0 w+ Y+ V) W* k* y) |5 X
868733 CONCEPT_HDL ARCHIVER ASA Archiver not saving the entire design.: u/ z5 S9 S9 d/ f! t! M! `
871548 ALLEGRO_EDITOR MENTOR Shapes missing after mbs2brd translation" A2 p, H. h' h) ^1 Q4 J
872003 SIG_EXPLORER SIMULATION TDR simulation results were different between 15.7 and 16.3.0 i2 {( b1 M7 t- E
872464 CONCEPT_HDL CORE DEHDL script works in SPB16.2 but not in SPB16.3 7 b7 J! O6 Z! W5 Y6 w# ]1 c% A873772 SCM CONSTRAINT_MGR Importing a block results in subblocks coming in without properties $ p( Z1 a1 ? }874335 SPECCTRA ROUTE Route Custom crashes SPECCTRA after routing for some time during "Running Route Phase". " Z6 E2 m# F1 i874989 CAPTURE SCHEMATICS Schematics jumps to another page after a mouse click/ q8 L" M* @1 R
875161 CAPTURE NETLISTS Creating Allegro netlist hangs Capture/ d6 a" ~# ^" B$ g
875411 ALLEGRO_EDITOR NC NC drill produces Error processing extract . Program terminated. ) y( _# m* a4 q+ i8 K6 x4 [876004 ALLEGRO_EDITOR SHAPE Unused pad suppression problem in Allegro v16.3 since S020~S0243 L6 N; \+ ~) \0 N: s
876045 ALLEGRO_EDITOR SHAPE Oval hole drills do not void shape with hole shape drc when the regular pad is smaller than hole ( {" m7 h5 \# U! J5 o876168 SPECCTRA_MENT_ IMPORT option to have a switch to prevent merging of plane layers during mbs2sp1 Z( P" K2 n- J0 f/ x, z$ \
876210 ALLEGRO_EDITOR SHAPE When updating shapes to Smooth the tool will hang.4 i* B2 m8 w, w' D; k+ B' P. J+ T
876284 ALLEGRO_EDITOR DATABASE Executing SKILL file crashes Allegro+ p8 N, d# Y2 q
877057 ALLEGRO_EDITOR MENTOR Footprints are shifted when importing from boardstation. ]! [5 J. x) h8 A. r& a" v- F
877549 SIP_LAYOUT WIREBOND Wirebonds not moving correctly when on an Interposer smaller than the die. % T) U- S5 ^( p) C" C4 l877862 APD WIREBOND APD crashed when add Wirebond without any dump and cannot record script. + _- Y# ~' t5 l9 [# |7 s" ]878199 CIS DERIVE_NEW_DB_PA Change in Regional Setting causing problem in derive database5 M1 g0 r1 v$ `$ K3 i/ f) H2 m% T
878216 APD OTHER stream_in - Stream file scan failed 8 K' N9 ?* J) R878400 APD WIREBOND unable to add a wire bonding on few die pad L4 d8 e$ [/ q6 z" Q* d
- `) L% Z0 a3 k4 Q/ ^
DATE: 03-11-2011 HOTFIX VERSION: 0260 g0 N5 v' W- z* i& |
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CCRID PRODUCT PRODUCTLEVEL2 TITLE O/ l2 l$ e& {2 p9 D8 a& |=================================================================================================================================== 5 Q. h) a. n8 D& j6 Y- s851882 SCM SCHGEN Multiple issues with the ASA generated schematic in preserve mode while using square bracket& v9 |+ b! ^1 v& L
852063 ALLEGRO_EDITOR EDIT_ETCH What is being displayed in the HUD when a percentage is specified as a tolerance? . ^1 `8 D5 ]2 V Z" Z854502 ALLEGRO_EDITOR DRC_CONSTR DRC not detected until DBDoctor is executed. Status form and sum dwg report are incorrect. 1 q0 K: I, S8 m- ]2 Y0 t856797 EMI RULE_CHECK Arc segments were detected as warning by bypass_plane_split. ( F+ c* [6 L3 M# P0 _) ^- G2 r859213 PCB_LIBRARIAN CORE $LOCATION size in PDV and DEHDL differ1 s+ s/ {/ N# q
860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser. y! |: G+ c# J+ g
862259 SIG_INTEGRITY FIELD_SOLVERS EMS2D run twice during View Topology. * P$ U5 m* N, F! \865158 ALLEGRO_EDITOR SHAPE Shapes are not voided with Dynamic Shape Fill modes with Regions $ f2 X R8 w1 S865295 PCB_LIBRARIAN CORE Part Developer crashs with symbols having Japanese notes1 w) R' V- Y7 L
866095 PCB_LIBRARIAN EXPORT_OTHER Export DE HDL part to Capture Part Crashed2 y7 b! U8 H" H7 Y' j% D
866835 SCM UI User arguments not used over project arguments for new tool* ~3 F/ \% O7 m/ ^3 K
867102 CAPTURE LIBRARY Incorrect pin number gets assigned to pin if a PDF is opened before writng the pin number. 2 i5 D- I1 ?/ K2 r4 y4 A" v868092 CAPTURE GEN_BOM Capture BOM in V16.3 is different than that of V16.2 for attached test case. F* _0 ^0 p" F- X: P$ g
868517 ALLEGRO_EDITOR ARTWORK A pinhole was made in the artwork file. 5 i6 V" v+ n- M) a; Y868646 ALLEGRO_EDITOR SCHEM_FTB Change in the PIN_GROUP at the chips level not propagated to the board file does not allow the swap " S% ~& T, O" O. f9 S) H2 }868844 PCB_LIBRARIAN CORE BUBBLE_GROUP with no value causes problematic symbol / l1 C! X. N5 R5 ]$ _3 H1 @869326 CIS DESIGN_VARIANT View Variant is not showing part as Do Not Stuff, i# ?+ L9 O( x, h' R+ d
869547 ALLEGRO_EDITOR SCHEM_FTB Error while parsing the alternate symbol 6 G4 Z! S0 p9 P9 b6 E+ o5 \7 i869931 SIG_INTEGRITY OTHER DML Library Management rewrites library longer then 512 characters into multiple lines.% q7 W; l) a, u5 V7 G
869960 F2B PACKAGERXL PART_NAME property added to Export Packageable schematic parts 4 u) E1 v. k' I- e1 ?870392 APD EDIT_ETCH Route > Slide not performing as expected in 16.39 U* F3 r# k3 `* R
870704 ALLEGRO_EDITOR PARTITION 2nd import of parttiotion unplace components in master5 o2 k: L7 Y* s( o# M0 S: G: S4 R
871177 CAPTURE LIBRARY Keyboard shortcut for closing the Place Part window 0 ~5 x9 }: u2 [9 F* |' j871552 PSPICE SIMULATOR Pspice tool crash- |# t3 ~0 |$ _& {3 u
871643 ALLEGRO_EDITOR INTERFACES IDF in batch and GUI for dra files fails to calculate extents correctly! y$ O9 r3 h1 ?& p3 ~
871968 ALLEGRO_EDITOR COLOR After using Clear All Nets, Color Dialog box needs to be reopened for adding custom colors.5 g' F% I8 x- H3 u: V$ H, l
872352 APD WIREBOND Move Guide paths crashed APD.3 c3 e9 D' w: U# `6 b, x
872380 CONCEPT_HDL COMP_BROWSER DEHDL crash when editing the ppt_optionset.dat file from Part Manager. . ?- e% K& s3 U3 k+ y2 p9 T872450 APD WIREBOND Wire to die edge angle remains highlighted in red for wire bond status window in v16.3, `" N+ P$ y( z& g! k
872787 APD WIREBOND Some Unused Wire profiles be purged but still existing in Bond Wire Profile of Color Visibility?0 u! L& I0 r, v! O
873217 ALLEGRO_EDITOR TESTPREP Testpoint generation not working correctly ; O5 s* y, j3 `! `873500 APD REPORTS Total Plating value is 0+ k k4 P# ?) t( a4 R f! k4 m
873505 APD MANUFACTURING fillet size changed when recreate Plating Bar ! D( T) f# _1 p. [! ^7 L873600 APD OTHER When attempting to Display Pin Names the tool takes a very long time.2 f& ^2 _- I' j2 A7 @% P( c
874341 ALLEGRO_EDITOR OTHER "Gloss>Convert corner to arc" command made an unnecessary circular arc. 4 t# h& Y. B: R: { ! C8 H X* C+ v: V# n: ?DATE: 02-26-2011 HOTFIX VERSION: 0259 O! r, [0 v5 D) Q
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CCRID PRODUCT PRODUCTLEVEL2 TITLE - f- k4 ]1 M+ |=================================================================================================================================== " [3 G" r4 k( V U746063 CIS OTHER CIS Query Does not display initial search results7 S3 L6 r9 V3 l
779588 ALLEGRO_EDITOR PLACEMENT Symbol outline not rotated with component.& U" A4 e& C5 N7 l+ E
805616 ALLEGRO_EDITOR ARTWORK Allegro produces warning about database extents exceed film size " n% K: r; }- h3 @, s% N6 }8 m843145 CONCEPT_HDL CORE Cannot copy grayed out properties in the Attributes form to the buffer & F4 G: o8 X' u j0 [: g( a. a845607 ALLEGRO_EDITOR EDIT_ETCH Sliding with arc gridless enabled leaves extra segments behind and 45 degree segment.6 t8 }( q1 A$ U4 q9 `8 I& X k5 J# y
850428 SIG_EXPLORER SIMULATION SigXP failed to simulate the topology with designlink.& e# y& L3 T8 {- Z4 ?2 g
853665 SPECCTRA CHECK Scheduling violations reported incorrectly. 8 J3 R0 L- @9 l$ ~855534 CONSTRAINT_MGR OTHER formula result does not update when length changed. b3 M3 b! z1 D
855793 CONCEPT_HDL CORE Rename Pin on Block is not working in DE HDL with HF 218 ], [$ E* d& y: J; @6 C' g
856306 ALLEGRO_EDITOR INTERACTIV Modifying pad instance corrupts db6 ~0 H- ]# {; x8 H, \6 q
859437 SIG_INTEGRITY GUI Log Scale setting of EMS2D was cleared by re-open design. 9 N6 A! _& _' Q& E- [859850 SIG_INTEGRITY GEOMETRY_EXTRACT Allegro freeze during topology extraction with EMS2D. * B; t, j/ N/ E- F% n9 [860366 CAPTURE CONNECTIVITY Netlist is different in V16.3 than in V16.2% g; q. y3 U) y$ N+ U9 I4 Z! J
860809 F2B BOM Bomhdl failed to create the design view check for existance of the packaged directory; r- l* _% d( T Q; r: w8 U
861027 CONSTRAINT_MGR CONCEPT_HDL Unable to synchronize the constraints$ d/ S& B, z% B- D
862137 SIP_LAYOUT OTHER SPB 16.3 SiP Logic - Derive assignment is unable to resolve connectivity of shapes + @2 ?: L7 S a862980 ALLEGRO_EDITOR EDIT_ETCH When sliding a via the potential DRC behaviour is inconsistent.' c3 a8 j- _2 r# w' |
863400 SPIF OTHER SPIF does not translate the oblong pads correctly0 A' n! Z' L- `8 o9 ?% U
864363 APD REPORTS The Wirebond report is failing because there are Non-standard Bond wires present.; C9 m+ i4 j$ j S
864621 ALLEGRO_EDITOR DATABASE Database corrupted after adding layers in Cross Section and trying to save the board file.6 ]+ r( \! i, b# _$ c' C u
865875 ALLEGRO_EDITOR MENTOR mbs2brd translator results in broken/unrouted nets even though the BoardStation design is fully routed* M6 h, F' D! Z2 z% b$ e2 c6 W
866202 CONSTRAINT_MGR OTHER Worksheet File import fails with error message due to character limit 6 |' ~6 a7 A3 L' u866726 CONCEPT_HDL CREFER TOC (table of content) not generated in schcref_1 schematic (CREFER flattened output).+ _7 s& x; U6 a: V7 s
867238 CONSTRAINT_MGR INTERACTIV Split Xnet for diff pair crashes PCB editor ( l) E. Y0 t3 z% {9 T* a& `3 C867696 SIP_LAYOUT DIE_STACK_EDITOR When doing an Info on this design it will crash. 9 |2 v. F) X) B2 _5 b5 b; J867742 ALLEGRO_EDITOR DATABASE Thermal Pad view for shapefillet on Negative layer 5 U: s# m: V# X6 k% ^867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location" / t% I2 N3 K) J9 S7 v$ q& H868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets 4 `9 C, b) W3 l/ W& o7 S869758 CAPTURE GENERATE_PART Generate Part option "Copy schematic to library" does not copy schematic page attributes 8 X# T% |7 z6 o) Z: [. s$ B/ a869941 ALLEGRO_EDITOR PADS_IN PADS_IN unable to import Power PCB 2005.0 file in 16.3 but works with 16.20 c5 k* S' b J, ?/ [# A
870301 SIP_LAYOUT SHOW_ELEM When selecting Info and then a rectangle shape, the tool will crash.4 ~0 ?: {7 i( Z$ V. {' `& y
0 u2 N2 p' `% W$ Q4 y. b
DATE: 02-11-2011 HOTFIX VERSION: 0247 \' M0 {1 L. a- [: |
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CCRID PRODUCT PRODUCTLEVEL2 TITLE # n1 v6 ?0 K: Y/ b" K===================================================================================================================================* J5 x- w6 z8 i0 m: D" ^+ c
858051 ALLEGRO_EDITOR OTHER Allegro's Help>About... System Info... doesn't work on Win7' G; r/ C4 F/ ^
862703 ALLEGRO_EDITOR DATABASE crash when doing a save_as8 ~3 U9 P$ l R9 K
866288 ALLEGRO_EDITOR NC Drill customization table won’t let you add characters in lower case - Q- o! U7 x! [9 l" O5 N% `866310 ALLEGRO_EDITOR DRC_CONSTR Testprep doesn't create a DRC for Testpoint > Component4 W9 b: s6 t1 @8 x `) K
866652 ALLEGRO_EDITOR SCHEM_FTB Allegro Spacing net class not updated with new logic9 h3 S5 M! X3 x- W! j, T
b, v; |; |1 TDATE: 01-28-2011 HOTFIX VERSION: 023; F& v. `+ a1 d! {2 s3 y: `0 h
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CCRID PRODUCT PRODUCTLEVEL2 TITLE8 c1 u/ O+ u+ B P
=================================================================================================================================== 3 M- ~$ p. S+ z- g4 I4 i' p739067 SIG_INTEGRITY SIMULATION about modal delay of diff pair net$ }+ {5 v* \# E) a, j: p# l5 L& s" i
742237 CIS FOOTPRINT_VIEW 3D Footprint view in CIS Explorer: @9 ?4 C( N/ u9 \ z
762702 CONCEPT_HDL CORE Unable to change color settings4 i/ a+ ?; [# a- W9 {1 [/ ^: r
800333 CONCEPT_HDL CORE Text change cursor not working on Solaris and Linux4 C( f4 t$ b$ u/ }, @5 l
837479 CONSTRAINT_MGR DATABASE Import dcf with custom column cuases a problem, a/ f2 ^8 e4 j* A) H" }
846679 ALLEGRO_EDITOR SHAPE Through Pin can not be voided correctly in dynamic shape. 0 ]6 T3 F! g3 b852255 CONCEPT_HDL COMP_BROWSER DEHDL crashes when adding part from cat file( f. [" c) |9 H7 T7 h4 l/ ^# B
855553 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts , C) T( l& z# g3 m/ `856459 SIG_INTEGRITY GEOMETRY_EXTRACT No waveform was output if users set the Via type to Analytical type 5 ]4 W f( b) }3 c857030 SIG_INTEGRITY OTHER Inconsistency when signal model has "legal" spaces within it. $ L' }9 G; q. B5 D' p# R857120 APD WIREBOND Enhancement for Redistribute Fingers. & E' s) ^, |$ S0 z0 m Q857165 SIG_INTEGRITY OTHER Model Name Changed Warning appears every time after Export Physical : c. e& I$ a/ p' C- V857237 ALLEGRO_EDITOR SCHEM_FTB UserDefined mapping mode( h$ \: s* ?+ _8 B/ q
857650 ALLEGRO_EDITOR DRC_CONSTR Hole to line DRC unavailable on inner layers for mechanical pin with no regular pad definition.4 k8 m: U# o! K8 a& x7 ]
858046 MODEL_INTEGRIT TRANSLATION Ibis2signoise fails translation when the unit of Pin section is "ohms". 6 J) I9 V* W4 L% h* B# d; `' K858154 GRE DETAIL Net not following the plan during Plan Topological- G# w8 B9 `& g& V& q8 H, M/ z* P
858192 SIP_LAYOUT SHAPE Program crashes when attempting to add polygon shape. . B" ?9 q& D* h2 u r$ e8 N* W858307 CIS DESIGN_VARIANT Homogenous part not showing correct DNI on schematic" p9 T9 w4 r6 j$ H# |. S7 L6 |
858624 ALLEGRO_EDITOR PAD_EDITOR "Save Padstack to 16.2" command is needed in 16.3 pad_designer.4 j' c' g! b$ ^. L+ E3 N& ~
858814 ALLEGRO_EDITOR MODULES place module not placing figures present in mdd 7 o) _3 M @4 Y1 {0 z$ N. v y- F$ a: I859514 APD IMPORT_DATA Die Text-in cannot change unnamed Begin Layer to selected pad layer in step 4: W# a2 y0 {& n0 V; Q" J+ ~5 ?2 {6 O1 [
859640 ALLEGRO_EDITOR PLOTTING Shape based pads not output as polygon in IPF* g/ J) O$ z- f% \0 E; n2 M! `" j
859680 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts z/ {2 T/ ]; l. ~0 b4 G2 h5 f2 F
860069 ALLEGRO_EDITOR OTHER Import Logic hangs then crashes and displays Netrev warnings. 6 \ w$ n9 A7 e* t6 L860535 APD DXF_IF a2dxf got an error message& ]/ ~4 m! D$ d/ @0 A
860860 CONCEPT_HDL COMP_BROWSER Component Browser freezes 4 l" g0 S- |8 ]) }' W6 T861295 CONSTRAINT_MGR ECS_APPLY Diff pair PCSet value overrides ECSet values in constraint manager spreadsheet. 5 r$ S7 k) q3 K862279 SPIF OTHER running 'Allegro PCB Router' Crashes % F) N. W ?7 m* u# m% g% z2 c, Q* t5 m" k: I
DATE: 01-14-2011 HOTFIX VERSION: 022& @1 ^6 n9 Z; `2 J0 t. }4 G+ s2 n# ?* \
===================================================================================================================================. \ q9 h6 l8 q4 i
CCRID PRODUCT PRODUCTLEVEL2 TITLE 1 J7 o& g% G: A+ I. |===================================================================================================================================- G7 {9 P) a, F$ i( X c
372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default $ {4 |$ e' h) l8 j5 [769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability ( M- \5 j8 l [ s772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled0 f8 P2 s8 B2 t" ]
830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems. 9 z5 i) `5 C6 |. v1 n) K4 ^833981 RF_PCB FE_IFF_IMPORT DE HDL Import IFF unit conversion and unit display in RF schematic - E* Z& L$ w5 M! f. e835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc5 U$ |8 n. Q5 a5 H6 W9 e
840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad( d: }& [, t4 I A/ P3 _
844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP 0 t6 V! _! x; q: `5 ~846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct. J7 p& M' W0 j4 i, q" W" g( x846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula 6 B1 T2 r" y0 Y+ Z0 J, b846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM ?! ]; B" ~7 T" D/ |6 S8 l, k
847278 CAPTURE TCL_INTERFACE TCL/TK PDF Export Change Page Size - H9 l" W4 M7 t- R9 ?847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP.# p$ C- W# ?# ]/ e9 W
848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work 6 |* i, B- J4 E; [& {8 z849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design. ( e) X# d: i2 r6 W( Z# }851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM6 {( x0 {$ O2 B- ^+ N
851171 F2B PACKAGERXL Design will not package with exclude_cdsNotOnSym 8 k5 d1 c$ a- h. W$ h7 G3 E f* Y! o851290 APD PADSTACK_EDITOR APD/SiP crashes when the user defined mask layer is edited with padeditdb. 4 ~: R' T8 g9 @* T851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes " ]8 x& k+ ^8 ?% D851658 APD EDIT_ETCH bunceback behavior while slideing cline $ E' n, U( H: h* k) E& x! R2 U0 V7 H851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update.' z* ?: `& E7 x2 z `8 a
851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via & Text causes Allegro to crash & J9 g% T2 I3 I- B: l2 E4 ?; Y1 M852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE8 ^* W9 `4 z0 q6 q, U
852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM# [/ Y/ ^- h k) j4 y4 D# K9 S
852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date 6 f& o& |5 |9 t- O3 Y/ \+ Q& _852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 424 i6 o+ b( _, l0 r
852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set 4 t& ~5 ~# o) I" D3 i( r' f853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg > Artwork if any Parameter syntax is wrong in art_param.txt 1 _2 c0 t6 g) M. Q3 B# ~% e9 c' Q1 v854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect.- }9 e7 F& p' S# `# t
854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange. # c2 J1 Z& x/ m; n5 _ N854293 APD OTHER dynamic fillets were disappeared when open in 16.3. ) {" v) B5 m" U" `. A6 H854356 ALLEGRO_EDITOR OTHER Fillet adding doesn’t check same net spacing rule in both static and dynamic mode. 2 U0 Z1 @ f' t. p9 ~855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected 6 r# n+ e' ^8 S855124 APD PLOTTING The "load plot" command did not import Drill symbols(Figure) and Characters in APD. ! [; ?! B$ r( X% r855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry ) d. Z# ?/ S5 @9 f856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations ( {& b) G8 b, U. w# T E& C P856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted.& n+ J+ l# p4 }- _6 f
856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing3 w, M" G; L0 F( s- B. W: O
8 a3 t0 r1 b' S; T$ E
DATE: 12-10-2010 HOTFIX VERSION: 021; F) H2 ~4 J4 m4 @7 j3 ?, F. h' f6 s
=================================================================================================================================== ' M4 Z0 s# ^; P! o' VCCRID PRODUCT PRODUCTLEVEL2 TITLE+ T) H1 h( B" c4 o/ K: {1 S
=================================================================================================================================== 3 m7 {$ V' ~! \' [: o g/ n. z708992 ALLEGRO_EDITOR SCHEM_FTB Design Differences fails with Error #534. C/ {7 X0 d/ W/ h* e; s
748982 CIS FOOTPRINT_VIEW Respective pin number from schematic does not get highlighted on 3-D footprint viewer. ( Q9 E1 B: g6 w9 X775788 CONCEPT_HDL COMP_BROWSER Component Browser search is too slow * n# Z" U0 `% l& ^( M802152 PCB_LIBRARIAN IMPORT_EXPORT cap2cond design translator is also looking for Capture feature string in license - this is break from 16.2, y. l, [" _. v9 u& |
803910 ALLEGRO_EDITOR GRAPHICS Request Rat like display for REFDES text to component. ! i8 H. o. a9 v( S& g1 j% o* Q7 \823599 SCM REPORTS Ability to generate DEHDL style BOM report Y# G$ E% c7 n. D* k' J
826558 CONCEPT_HDL LWB-HDL Module definitions for cells is not included in the simulation verilog netlsit on LINUX 3 j, j E! B# V828689 CONSTRAINT_MGR OTHER formula constraint lost when Constraint Manager closed 1 i1 W7 }4 w% j831192 SIG_INTEGRITY GUI Cannot close Analysis Preferences window. - d7 i, y) E/ d! F9 b' p# u/ v831229 ALLEGRO_EDITOR INTERACTIV When mirroring sym PLACE_BOUND shape does not mirror til placed' |: p$ E1 x: c! N# f
832315 ALLEGRO_EDITOR SCHEM_FTB ECO.txt file should not list net names if schematic and board files are synchronized. & I+ v6 O# i6 m+ E/ ~) j832644 ALLEGRO_EDITOR DRC_CONSTR DRC error disappears when the size of Constraint region is changed.( _$ N* M+ U6 }, S) f b0 K
833061 MODEL_INTEGRIT TRANSLATION Model Integrity IBIS2DML fails to convert data correctly for pre-emphasis using Driver Schedule/ R8 Z2 t- l: A6 s- t/ g7 k
833487 SIG_INTEGRITY GEOMETRY_EXTRACT Probe sim failed if VARIANT_TO_IGNORE was set. 4 S+ z" T& C3 `7 r6 T8 i z5 D9 U833922 CONCEPT_HDL CORE Move pin on blocksymbol using Block -> Move Pin command change the Pinname textsize 0 H1 e0 I# q/ ~- a3 u5 _834103 ALLEGRO_EDITOR DRC_CONSTR dynamic diff phase highlight not showing 5 H: J0 G2 {0 w$ B% K/ I- U: y$ |9 }7 o834868 SIG_EXPLORER OTHER View Trace Param crash if sweep param was set for loss tangent. / d4 y6 {/ }: f( M' f0 B835006 CONCEPT_HDL OTHER Locked BACKGROUND directive is changed in DEHDL session / w4 J2 f6 E" J z3 x835326 APD SPECCTRA_IF Specctra does not open from APD using Allegro Package Designer XL (Legacy) license# J1 l8 o' u0 n
835622 CONCEPT_HDL CORE DE-HDL crashes when selecting wire having global sig_name in opened block schematic) e! [+ e( ?. b8 h1 u) n) P- j% l
836962 CONSTRAINT_MGR ANALYSIS Simulation will crash " W5 [% F i, C5 _/ E0 `. }3 x6 ?837216 CONSTRAINT_MGR OTHER Custom measurement Rslt lines being duplicated in a different worksheet. % ~% }% c1 S5 A# _' \$ l837322 CAPTURE LIBRARY Library is not getting freed even when user has closed it. ' m3 M# `5 M# [0 M. _! a839517 CAPTURE MACRO Macros (for place part) created on 16.2 version works differently on 16.37 o! S' |5 ~ R, _" T$ }
839749 ALLEGRO_EDITOR MANUFACT Drill entries are repeated in .drl files 2 r8 J( N8 v6 Y+ s+ T T840738 ALLEGRO_EDITOR ARTWORK Shape symbol in padstack moves when Artwork is generated - Break again after fix in 16.0 3 h5 I5 e+ l" N" [! @; T841176 CAPTURE ANNOTATE Homogenous parts are not getting packaged correctly in annotation in 16.35 G9 X! z- C: _% s, r; Q5 y
841355 SIG_EXPLORER OTHER Trace model parameter does not update when linear Range are entered. ' _! h* W7 b/ ~; s% r B841730 CONSTRAINT_MGR OTHER Allegro Crashes while working with MGs in CM ' a3 Z5 ]# R2 l2 z) O841759 F2B BOM BOM creates an incomplete output when design packages without errors 3 W' E; Q) s* y) _& J' c841928 CONCEPT_HDL CHECKPLUS CheckPlus fails when pin name contains _N in the middle of the pin name ; {4 t$ B3 S. a" S# G q841991 ALLEGRO_EDITOR PLOTTING Offset of text and line on importing a plt file9 o* Y& V7 ]& F5 y
842204 ALLEGRO_EDITOR DRC_CONSTR Arc creates false DRC on edge of Constraint Area7 q5 E, |7 p2 n7 m6 J
843114 SPECCTRA ROUTE Specctra rules file taking very long time to load 3 c* U; W# F& J" N; I. y843254 CONCEPT_HDL CONSTRAINT_MGR Unable to invoke CM from DEHDL CM Crashes with an error Olecs.exe The application has quite unexpectedly : Y8 q0 g, G8 e* m9 b3 f843518 F2B DESIGNVARI Variant with FAIL_OPEN % K# j& V- ?7 q4 ^843933 ALLEGRO_EDITOR DRC_CONSTR Cancelling drcupdate will either hang or crash Allegro % y2 x7 C/ h5 ~2 c6 m844074 APD SPECCTRA_IF Export Router fails with memory errors.9 P: v7 s2 W# l6 F
844246 ALLEGRO_EDITOR SHAPE Long Thermal_Relief connecting to XHatch shape ( ]2 |* B9 u7 `2 p2 o844355 CONCEPT_HDL COMP_BROWSER User seeing CDS_NA appear when placing component : X5 m% N/ M: Z* V; u( M. n7 l844381 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin - Pin is connected to net <netname> not reconnected. ; f' M) x& k2 r! a844662 SIG_INTEGRITY OTHER Cannot uncheck options in analysis preferences. 9 K2 d! M9 ]( n844796 SIG_INTEGRITY OTHER Get an error E- Illegal model name. Cannot add model RE_RES_0402-16570580,when doing Auto Setup during Model assignment9 J/ v" P1 O, k1 a: n% n
846172 APD OTHER Cannot generate the dxf file from this database 2 T6 A# ~& q$ T2 B& Y. U- ~846270 SPECCTRA GUI SIGNAL_15 layer missing from the color pallete in Specctra . u' L" p( k5 T/ Y/ l846352 ALLEGRO_EDITOR DRC_CONSTR Route connect does not select the pin-pair width for routing. 3 G8 I, ?. ?- T% v0 O; W846420 F2B DESIGNSYNC Design Sync failes due to FUNC_VIEW_FILE missing messages % M, _1 D0 D2 e5 k3 p846918 ALLEGRO_EDITOR PADS_IN Pads_in crashes when importing ASCII file, Runtime Error5 R, J5 ~; l8 G$ ^7 m7 _0 y
847079 ALLEGRO_EDITOR DATABASE Allegro Crash while trying to unlock the board file% K* A% v' q, `8 N2 _* a( O0 h
848143 F2B DDBPI Adding part crashes DEHDL8 K `% }8 c$ `9 n6 m, B3 E
848415 CAPTURE STABILITY Crash on Mirror Horizontally E: h# Y% F( l7 L
8 r% J$ I1 J5 TDATE: 11-11-2010 HOTFIX VERSION: 0208 W7 B4 e& Q; B) W2 |
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CCRID PRODUCT PRODUCTLEVEL2 TITLE9 X$ j5 r) o/ E& v6 `$ D, @
=================================================================================================================================== 9 }" [2 w7 D% h9 J5 n* K s7 ~501606 CAPTURE OTHER Descend Hierachy does not open first page& N; Y$ v7 P6 K8 w3 M! m/ Y
764482 SPECCTRA CHECK Allegro router same net checking different then PCB Editor.: i' n9 E, H8 s1 Q
809055 APD EDIT_ETCH Shove Preferred changes trace widths of shoved traces during routing 5 v1 H0 @( X5 i' g# O816920 ALLEGRO_EDITOR PLACEMENT Update symbols causing Allegro to crash4 Z0 \8 a$ M: U, k4 _9 X
826762 SIG_EXPLORER OTHER The rotation of element are different between pre 16.2 and 16.3.1 Q; x7 N2 @! u: v
827769 CIS FOOTPRINT_VIEW 3D footrpint viewer doesn't shows circular geometry on footprints8 g1 [# G( U5 ]2 e- `
828830 F2B DDBPI LRM does not update Parts which have a ALT_SYMBOLS value Added) |! r0 D! z2 }+ ^- A7 u
830319 SIG_INTEGRITY SIGWAVE Sigwave load errors out with "Requested resource was not available" after large bus simulation 2 G9 o( h; z' b0 a% l4 a/ Y2 l& s830359 CAPTURE GENERAL Crash on link Database Part ) y/ u( L2 x4 b) d2 Z4 y& d830627 ALLEGRO_EDITOR DRC_CONSTR Incorrect thru pin to shape SPACING error8 A9 C l* B+ ^- s* E! r8 O; A
830716 CAPTURE PRINT/PLOT/OUTPU Capture crashes while printing a Capture CIS Standard BoM with ISR s0017. ) A1 a, }9 j0 @, v/ V! f830791 SIP_LAYOUT LEFDEF_IF Improve the LEF Library Manager to import passivation layers3 R6 U) t) l5 B7 g# Z
831210 CAPTURE OTHER Users get an error message everytime While running Update Cache with V16.3 and V16.2 with latest ISR " O6 w4 }* s0 m# s831231 PSPICE SCHEMATICS pspice com wrapper error 5 ]+ _9 W5 z3 g5 B! L+ x831692 ALLEGRO_EDITOR PLACEMENT Application becomes sluggish to nonresponsive when trying to place mechanical symbol " A7 _# H5 M; c5 U831704 CONCEPT_HDL CORE ASA stuck in an error condition. $ @3 F! Y! c- t6 z833116 PCB_LIBRARIAN IMPORT_EXPORT Getting LMF-02018 Error while Importing Capture Parts $ r) a1 s) U! i; q( F3 \( `# O, d6 |833433 ALLEGRO_EDITOR TECHFILE techfile in/out round-off a value of Conductivity(Xsection). 1 V$ c, N( G) g( o; m833921 ALLEGRO_EDITOR ARTWORK Gerber filled lines stick out from filled area on Fillets: ?+ t" W0 a7 a1 A- i
833950 ALLEGRO_EDITOR ARTWORK Artwork process create recrementitious circle for AutoSilk data.6 K' n9 @- `4 D
833975 SIP_LAYOUT DATABASE pad not on subclass " h3 ]3 G, a/ X5 \834152 APD EDIT_ETCH Route Slide of a Diff_pair section moves all of the cline instead of just the segment that you want.& Q( y! N W3 D5 h9 k+ ^
834861 APD OTHER package integrity runs for hours. results in no more room in database % b7 R! L5 @8 N, r# l% L# M835367 CONCEPT_HDL SECTION Packager-XL reverses the pin numbers of connectors. W1 J7 g5 m W) W5 h# m
837805 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes Allegro when routing from a cline (not on a net) through a region. 5 I* u3 F% i* h) N838057 CONCEPT_HDL CHECKPLUS CheckPlus crashes with long parameter.; j# N! C& i# m1 I/ V W# o5 u6 Z
838356 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops / e: g5 v2 }2 Z5 \; m9 M# J: `838521 APD MANUFACTURING When creating pbar some clines are gone. - q( v& L/ l, z- x a6 R838766 ALLEGRO_EDITOR EDIT_ETCH Sliding with arcs making sharp corners instead of arcs.7 ~) \" ]) a/ z; q _, G
838830 SIP_LAYOUT ASSY_RULE_CHECK Assembly rule check flagging a DRC for item not near edge border6 U( c% U% g) t
838836 ALLEGRO_EDITOR SKILL Pb to check license with skill core function v0 g; L) M+ V$ l* Z4 Y1 D' r
839218 APD 3D_VIEWER 3D view of this mcm file is not getting rendered and the 3D GUI screen shows up blank in APD& O/ v& E- T" X( ` N0 Y0 F
839362 ALLEGRO_EDITOR EDIT_ETCH trying to slide a bbVia crashes Allegro - l! Q+ z H% e" p839984 ALLEGRO_EDITOR ARTWORK Some pinholes were made in the artwork file.7 H; e! F! G1 ?; s4 G
840016 CONSTRAINT_MGR INTERACTIV Cannot manually create pin pair for unspec pins of Xnet./ v4 h$ h9 \1 {* {# q' Y4 j |
840455 ALLEGRO_EDITOR INTERFACES IDF exported/imported from symbol have no drill information for pad.4 j* ?# h8 N' d9 ]& U( x4 [/ R
841431 CAPTURE NETLIST_ALLEGRO Upgrading from Capture V16.2 to V16.3 some nets get shorted on the schematic page.1 ~+ |% p) u* {
j- t5 W( }; z- rDATE: 10-20-2010 HOTFIX VERSION: 0196 Z8 W$ T' ]1 u& d/ y/ a
=================================================================================================================================== " p6 j$ l* n! RCCRID PRODUCT PRODUCTLEVEL2 TITLE 8 n9 P9 I" X# `3 N===================================================================================================================================) H9 J: a8 x8 s! @: ?( f
717365 SCM SCHGEN Option for Schematic Block to have the defined Sheet symbol/Page Border. N& t7 j/ Q2 {9 ~ J
751477 ADW COMPONENT_BROWSE UCB in DB mode does not read local worklib for block symbols U% e- I2 a: G
792545 APD PADSTACK_EDITOR Can not rename user defined Mask Layer in APD/SiP. ( @0 d, U$ }9 N( p! O7 f813436 SCM OTHER Option to have a directive in the cpm file to distinguish an SCM project from a DE HDL Project . ^9 o' o% k' i+ y" ]$ K0 o& j820640 SIG_EXPLORER OTHER SigXP Crash after doing Transform For Constraint Manager 3 F0 ?# G, Q/ V824527 CAPTURE PRINT/PLOT/OUTPU Part ref-des resets when trying to take variant print from Part Manager 2 I0 ^5 e: |* }6 F6 H) k; Z% s824688 SIG_INTEGRITY GEOMETRY_EXTRACT PCB-SI crashes when running more than 2 simulations # J! \( B* @$ ?1 M n p5 c826571 CONSTRAINT_MGR OTHER Import of .dcf crashes in 16.2 but not 16.3 : _/ \' r, {/ h! T826626 CONSTRAINT_MGR OTHER Creating a Netclass from a custom worksheet breaks the Netclass object upon the next invocation of Constraint Manager.6 \+ U- N: J! h* x& V
826799 SIG_EXPLORER SETUP_ADV can not close Analysis Preferences form when Advanced Setting button is opened and closed once 7 R0 M/ _) w' z8 e827375 ALLEGRO_EDITOR DATABASE Need to check why Net class assigned on the Net are not visible in CM # \" Q6 a% ?, F) M( r( A827521 CONSTRAINT_MGR OTHER Allegro crashes when trying to open Constraint Manager. 8 e* K* X* \; C! h: Q$ ~2 |7 Y+ H827713 SIG_EXPLORER INTERACTIV Cannot move object by click and drag after RMB>Note.* B/ u9 Y( y' p/ r; U8 f# J6 |
828803 CIS UPDATE_PART_STAT Crash on update part status from Part Manager; b$ l$ E4 M$ C. ^4 J4 i
829005 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with EMS2D.7 l# l) N8 w6 A. X6 W# j9 k8 G' S1 }
829008 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with BEM2D. 0 f/ u' w/ e% t# ]$ h* H9 u4 h, x829233 CONSTRAINT_MGR UI_FORMS Physical Csets applied on a diffpair is not followed while routing, though visible in CM.. m7 Q3 A5 ^0 {. }' a' t! [; V/ i
829340 CAPTURE LIBRARY_EDITOR propertries are shifting after being placed 5 ^ w% E; u3 u) K829747 SIP_LAYOUT DIE_EDITOR Move pin incremental coordinate2 k0 b$ V: A" Y }/ o# N6 J
829991 SIP_LAYOUT OTHER The "axlAddAutoAssignNetAlgorithm" function is missing from the Allegro SKILL documentation.( z# C/ q$ \/ c0 k. h7 n/ M7 K
830509 APD ARTWORK The measured airgap aren't between features in the design aren't consistent in Import > Artwork. 3 \' Z7 d1 N3 M ?830809 ALLEGRO_EDITOR TESTPREP In the testprep report the Pin type is getting appended with net name9 e1 z2 p# H* D. h& O# V+ z3 P7 c
830907 SIP_LAYOUT DIE_GENERATOR SiP will crash when adding a Standard DIE using the Die Generator.5 u2 W5 M( [) L
831176 ALLEGRO_EDITOR MANUFACT Testprep Resequence crashes this design.7 a9 ~0 p* G2 W: c2 E! ~; d
831199 SIG_EXPLORER OTHER error in _sxUtilGetAllegroPart message was displayed.# y" H5 M+ O6 R
831610 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present % J5 z+ E3 W+ _+ G831946 ALLEGRO_EDITOR OTHER Cannot re-open Command Browser if it was closed by Undo.' P! F8 j2 ?* l4 R z% k' i) A
831998 ALLEGRO_EDITOR SHAPE Allegro crash when user execute shape vertex add command. 3 X8 p* @9 t4 J, o7 d+ j* `7 l832059 APD SHAPE Shape does not keep Shape-Via(w/ Fillet) spacing. + j: e0 e7 U: f8 J3 {832169 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present - o& D1 m! d0 b y832197 ALLEGRO_EDITOR EDIT_ETCH Sliding diffpair slides adjacent segment3 ^& b2 a" O5 S
832613 ALLEGRO_EDITOR EDIT_ETCH Adding microvia and bbvia crashes allegro at location where overlapping shapes exist on other layer # T* n( y( z4 C- [832922 ALLEGRO_EDITOR PARTITION Import partition board crashes Allegro. + [% R5 [1 U: {! s3 Z833127 ALLEGRO_EDITOR SYMBOL With 'unused pads suppression' the padstack (clearance) does not get rotated in the internal layer ' m x' r% y3 G833251 ALLEGRO_EDITOR SCHEM_FTB Power planes on Layer E3 and E18 change to dummy net after Refresh Module. r, {. y/ t" M7 w8 s! X: b! g833586 ALLEGRO_EDITOR PLACEMENT Allegro crashes while placing jumper; T0 C/ m8 M$ r6 w) ~# z
# G' L0 D: O" W. f) l
DATE: 10-7-2010 HOTFIX VERSION: 018 1 e; w, v/ G, W===================================================================================================================================: E0 e! X V0 L4 m$ H4 @, y% q
CCRID PRODUCT PRODUCTLEVEL2 TITLE5 m) h8 L$ n7 S, g0 N" e) V
=================================================================================================================================== ! a( m0 E# Q. L3 Z* C398114 ALLEGRO_EDITOR INTERACTIV Need to differentiate between tracks and shapes on an etch layer.# K+ m8 N- d+ T% f8 Z
530659 ALLEGRO_EDITOR UI_FORMS Allegro Place Manually and Update Symbols GUI missing checkboxes on Windows Vista: d+ z h4 O) ^) ]& \" Q7 F
770576 ALLEGRO_EDITOR INTERACTIV Design Partition - Place replication not working correctly + ^& t$ k+ w% J" {' i O1 l777925 CAPTURE OTHER Capture crash immediately after invoking2 B8 V4 r; T: f; d4 q3 j
807089 FLOORPLANNER INTERACTIV Logic > Net Logic hangs tool in Linux T% [5 P& w6 D4 u6 u. K809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs - R6 ~0 B- {0 O6 Q0 Q812046 CAPTURE NETLIST_ALLEGRO Design not getting netlisted in V16.3 due to illegal characters in pin nmaes 4 V. m6 C7 }* D. y' V/ s814607 SIP_LAYOUT IO_PLANNER update genfeed to add options to dumbp all chips files from design) ~- y2 R3 O: u \6 }* v" h8 G) y
814750 ALLEGRO_EDITOR DRC_CONSTR BBvia and Microvia overlap DRC issue 4 D& s" ~6 f- `9 t. b" s815621 SCM OTHER Enhance time shown in session log to support DST ^$ Q: Q" Q( `) E) p: I$ _/ U815681 CONCEPT_HDL CORE The TOC symbol shows multiple entries for the pages% j; I2 q8 @; R! R' b" t% U4 M& }
817380 ALLEGRO_EDITOR DRC_CONSTR Incorrect or bogus line to line DRC errors are appearing between the nets of a diffpair 2 x% f1 Y. @( g' M817881 APD ETCH_BACK Create Etch Back Mask failed) M5 z# J, U4 R# o! v: \. N
820771 ALLEGRO_EDITOR PLOTTING axlLayerPrioritySet does not provide the same capability than the 15.7 Color Priority system 8 ]6 U) i& [/ j b; ?820773 ALLEGRO_EDITOR INTERFACES Import 3rd Party Logic $SCHEDULE removes visible ratsnest from database when using T-Points' w& F; t6 D5 u% D) x7 s
820792 ALLEGRO_EDITOR INTERFACES Import $Schedule command is returning illegal loop error for pin-pair based rules ; O% j. | W3 ]" w* W5 e821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format 4 P* \7 B; f/ h$ A821504 MODEL_INTEGRIT TRANSLATION dmlcheck failed when .dml translated from .mod was opened by MI.5 @( ^- o+ q8 d+ U" Z7 d
821827 ALLEGRO_EDITOR EDIT_ETCH Allegro Crash on routing Diff Pairs4 b8 r. {$ }/ ?! t: R, Q9 d9 n
821836 CONSTRAINT_MGR OTHER Why the min/max propagation delay analysis is failing for one of the pin pair in this design! 7 p# r: H% h7 s822090 CONCEPT_HDL CONSTRAINT_MGR Crashed the Constriant Manager and SigXplorer from DE HDL6 u& B# y A2 @2 l/ p
822744 CONSTRAINT_MGR DATABASE Xnet lost after DCF file imported into Constraint Manager % T& \: N) n. P3 x, O5 A) q$ e* e822827 PSPICE SIMULATOR Simsrvr crash upon running simulation& _% ?2 b" |! |$ F
822844 ALLEGRO_EDITOR SCHEM_FTB Constraints are not updated in the brd file when working with Library defined diff pairs7 P6 \; @4 Y4 W, c. ?; c
822942 F2B DESIGNVARI Variant view does not show DNI on functions 7 `. L' o c0 a* \823177 SCM BROWSER PPT_OPTIONSET_PATH defined using environment variable is not recognized by ASA ; n- y/ J$ h8 i) l; t. T, R823200 ALLEGRO_EDITOR OTHER Import Logic hangs when dynamic phase control set ( m! N& Y: I! k P823589 CONCEPT_HDL CORE The operation could not be performed because no object on the drawing was selected; z" J/ s3 H% P4 o- N
823821 ALLEGRO_EDITOR MANUFACT Allegro crash when trying to Gloss - $ p, n2 P! b1 |, E823833 CONCEPT_HDL CORE show vectors command( b8 W1 _) A" M
824902 ALLEGRO_EDITOR DATABASE Lose connectivity when copied via and cline structure* J. m/ r5 P) x9 s2 ~1 Z3 Q: I
825289 ALLEGRO_EDITOR DRC_CONSTR duplicated drc and waive drc , A3 p$ j1 d3 Y825969 CAPTURE SCHEMATIC_EDITOR Refdes are getting reset after doing a replace cache/update cache for a generated pat" A5 U0 {9 e3 c1 i
826068 ALLEGRO_EDITOR MANUFACT Adding Thieving on the negative plane layer doesn't show up/ b+ j+ v8 ]: {: j. {7 y7 |
826266 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro in Linux) H6 _# a& O8 d9 U
827032 SIP_LAYOUT ASSY_RULE_CHECK SiP Layout crashes when running Assembly Rules checks ; H# P7 R: U( H827494 CAPTURE GEN_BOM Include file is overwritten for the STD Capture BOM if .txt file used as include file0 c0 p$ c3 S5 [; O( ]
827575 CONCEPT_HDL CONSTRAINT_MGR PINUSE ( l5 Z9 s7 K& t$ `( h1 p827708 APD 3D_VIEWER 3D viewer assign black color for all layer 9 v' [/ W& w0 j$ O- P+ v828263 APD DXF_IF When the DXF out is executed, offset of the padstack is not correct.9 `/ j! {" o' N( C# m& D) a/ l
828788 ALLEGRO_EDITOR DRC_CONSTR Soldermask Waived DRCs reappear in 16.3 4 c8 c. I: A7 X# v7 ? [829046 APD MANUFACTURING create plating bar makes net name changed to dummy net! N! i6 r1 N, [$ f, |
829331 SIP_LAYOUT PLATING_BAR Create Plating Bar is deleting existing fillets. ) Y( J% n6 B# i9 M r2 t- y% x829336 APD OTHER Request the ability to merge two nets together into a new net. 3 K+ T" _8 b1 P% Y 4 i( E+ |5 b) x! y @6 a, ADATE: 09-23-2010 HOTFIX VERSION: 017 $ _, K: M0 l) K: V7 K* g8 Q! @=================================================================================================================================== ) @9 @/ @9 |5 d- S$ \& wCCRID PRODUCT PRODUCTLEVEL2 TITLE* F% U' o6 f2 d! A0 w, G7 K
===================================================================================================================================, O6 G# {9 k1 n" N$ L
676210 CAPTURE PRINT/PLOT/OUTPU Enhancement for correlate lower level pages with H blockes in PDF. C; i9 |5 X$ n; B4 I" C
736942 ALLEGRO_EDITOR INTERACTIV Autosave is not working with every application mode.0 S; U9 }8 }# S
746256 CAPTURE ANNOTATE Intersheet refernces change their position in V16.3 even on unchecking ‘reset position’.8 o5 e O0 c' b6 k
785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error, g. D6 Y1 ^4 s0 l9 R. h/ t1 ^
791549 PSPICE PROBE PSpice cursor does not remember value outside zoom area- M2 T1 j* y% q- J& `" f4 ~
802639 F2B DESIGNSYNC BOMHDL crashes if colon is used as a sub design suffix separator ' w' E5 |1 H# B6 q804475 CONCEPT_HDL OTHER RMB+MMW doesn't zoom in/out anymore with ISR012( U/ s/ @3 l1 v2 _
807025 PSPICE PROBE Loading dat file slower in 16.3 as compared to 16.2 0 W) h8 m) q2 H: R5 p808550 CONCEPT_HDL OTHER On Linux Import design does not obey umask or setgid settings! c- x' F. F: l. @% o
810568 ALLEGRO_EDITOR PADS_IN Can PowerPCB 9.2 - Basic file be converted to Allegro? - c" T( w/ }% r5 J812089 CONCEPT_HDL OTHER The colors on the Options form dont seem to match the colors displayed on the schematic canvas 7 p. Z4 }# {- c/ t; z: v5 K812475 ALLEGRO_EDITOR INTERACTIV Saving .mdd always results in working directory' s. n, @$ }: s! M& W* y
812836 CONSTRAINT_MGR DATABASE CM Custom Fomula -Handling of Pin_Delay is inconsistent in Analyze : q5 V4 A# V) ~ g. ~7 f812994 SPECCTRA ROUTE Max_total_vias constraint not working correctly when wiring option is set to "starburst".& B- `, b1 l8 ~1 K* K0 [
816561 CONCEPT_HDL CONSTRAINT_MGR OLECS.exe Runtime Error occures when attempting to launch SigXP from a net in CM : P n! a0 M' i9 W816879 SIG_INTEGRITY SIGNOISE Program has encountered a problem and must exit in 16.3 S014(v16-3-85AT). , W9 j8 K1 F! S8 w4 c9 d% n817006 SCM UI SCM copy signal changes existing signal names ; \8 I- i8 r; ]817896 APD ETCH_BACK Etch back - improper use model1 n G2 l1 t( M0 k
818242 ALLEGRO_EDITOR SHAPE Thermal relief connections not orthoganal and creating acute angles.* B" c1 U/ I4 {* k
818429 ALLEGRO_EDITOR PLOTTING Pins created from shapes do not plot solid. 4 q. Y2 C! I5 l ^: ?818513 F2B BOM Alphanumeric BOM not placing REF DES in proper order 6 U+ r/ v, I& _818818 ALLEGRO_EDITOR INTERACTIV Place replication does not recognize mixed case characters in file path6 o7 o7 m v6 k$ H \* v
818910 CAPTURE FPGA NC simulation flow is not working with 16.3 release0 m, d6 x4 p3 C& G+ M
819108 SIP_LAYOUT DATABASE Wirebond profile constraints lost after saving and re-open sip+ r! A. y6 V- X d7 L4 p6 M1 p* O* Z
819151 SIP_LAYOUT ASSY_RULE_CHECK ADRC is showing X-D DRC markers on good Soldermask Shapes when doing a min. shape check. 4 @! \# B2 t; N0 D5 l% x& {- G4 [819183 ALLEGRO_EDITOR MANUFACT NC Drill file generated for Backdrill layers show wrong Quantity of the drills % F1 V2 Q1 l& Y819269 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops - Y2 w* h$ |2 _819463 ALLEGRO_EDITOR DATABASE VIA has illegal connections.3 S( p. O/ @6 j6 S) v+ V
819842 ALLEGRO_EDITOR INTERFACES File Import Logic fails on syntax check when following documentation for $schedule command6 Q* `* S8 K0 j6 X- L
820177 CONSTRAINT_MGR CONCEPT_HDL Net_class objects that are changed in CM at Front End are missing after Import Logic# [# O* G8 C9 {! V) H
820231 ALLEGRO_EDITOR DRC_CONSTR Allegro hangs when multi thread DRC is performed after updating padstacks 2 h$ E3 Y1 P! T# a# k8 V820373 SIP_LAYOUT OTHER Update symbol flags the "edited pins" error but still updates the symbol and then crashes." a" w4 \3 F$ s. o4 k
820381 SIP_LAYOUT WIREBOND When opening a new design, with a design already open, the tool will use the first designs profile settiings, y- `& u0 V( q) a" x, f, j
820634 CONSTRAINT_MGR OTHER Netrev fails without any useful message when importing ECO netlist 7 q! Y# C7 a) u820665 ALLEGRO_EDITOR REFRESH Qvupdate is not working in 16.3 7 A! e5 U5 F8 U1 }6 E4 ^$ L" b! P. X0 h820849 ALLEGRO_EDITOR MANUFACT NC Drill has wrong quantity and also a drill is missing ' \4 c5 h. _+ N6 B9 x$ G% u# f9 e9 V821154 CONSTRAINT_MGR CONCEPT_HDL DE-HDL CM Import Analysis Results fails without any feedback & P) R4 |$ L) d5 z& [+ q+ Z$ d9 i821195 CAPTURE OTHER Updating Cache generates errors including CAP0027 on Capture DE CIS with ISR s0014 and onwards.( Y: J! ]$ a3 K! |8 Z
821856 APD MANUFACTURING Create Bond finger Solder Mask issue 3 [2 y4 p0 T& w( ^$ S0 ^0 s, F821936 SIP_LAYOUT COLOR Can not clear custom color of bondwire profiles' j9 V/ C( t3 ?# p1 _. y, o2 H! D6 N! D
822841 ALLEGRO_EDITOR ARTWORK An issue about Gerber6X00 " B4 T+ s% r1 p8 E822842 SIG_INTEGRITY OTHER CM and Show element report different lengths; n8 M2 t, Y2 T" Z. z0 o
823559 SIP_LAYOUT BGA_EDITOR When doing an Edit > BGA the tool will shift the BGA's position when at 90 or 270 rotation. $ z, Y0 t9 Z0 T. D' s823688 SCM SCHGEN Schgen changing the physicals bus name in the preserve mode for some of the bus2 P' G0 E+ V; j
823792 CIS OTHER Capture CIS performance over WAN for bulk operations are slow & U0 r" C& r8 r2 Q. I8 ]/ N1 q. }2 W0 n1 f
DATE: 09-10-2010 HOTFIX VERSION: 0162 X! ?# ~9 P0 t. d% F4 o; v9 `0 Y
=================================================================================================================================== & ], {$ T: q7 j% H! U2 KCCRID PRODUCT PRODUCTLEVEL2 TITLE" s. s) r" K1 Y! k" }' c
===================================================================================================================================* m# N7 d( t+ M) b' r
604662 VLS-L VIA When changing Rows/Columns values in Edit Via Properties form, different value are assigned.' g4 q4 S! Z% N% g
747191 PSPICE AA_SENS Pspice crashes when starting Advance Analysis . e s6 A; O! \+ A$ B7 i. M9 ]756103 CONCEPT_HDL ARCHIVER Archiver does not include all the Parts when design blocks are copied from one location to another 3 q5 E q9 y* S" v7 X! l% g% n" H758487 APD 3D_VIEWER package substrate (BGA) outline should be on a separate layer, not on bottom conductor layer.$ d( k. v' o. N
764417 APD EDIT_ETCH Routing with Diagonal entry (45 degree) to Constraint Regions does not work% c2 H) {5 q# i" H2 q& p5 T0 V
766409 PSPICE PROBE Copy to Clipboard changes the label text colors " R" I' v: R6 ? {/ j+ m' X784577 CONCEPT_HDL COMP_BROWSER SingleclickAdd 'true' places does not pick the correct version3 R2 B& ^7 K2 W, n
784814 SIP_LAYOUT ASSY_RULE_CHECK accuracy of acute angle DRC0 s" k1 w8 h9 {+ |& W4 y, D8 i( q& J
792039 CONSTRAINT_MGR OTHER Doing a File->Import->Worksheet Customization from Constraint Manager will change the working directory.7 i" B3 x- u0 O v4 S2 r7 z
796517 CONCEPT_HDL COMP_BROWSER Component Browser showing wrong symbol" B! J D" P% ~4 Y% _: R: g
801944 SCM UI SCM dropping terminators and pull-ups when renaming signals (copy - paste special) 4 Z2 l+ A* h0 i* m0 D8 j+ J9 W804627 PSPICE PROBE Printet text labels have wrong location & t4 Q( ~3 {5 _5 F6 Z9 l810479 FSP DESIGN_SETTINGS Not able to connect some peripheral signals to FPGA manually 5 @5 ^. y4 }6 I8 `, Y810814 CONSTRAINT_MGR OTHER T-point does not create when import DCF file. 9 H9 s, s% K+ a811032 ALLEGRO_EDITOR EDIT_ETCH Enable enhanced pad entry to support pads as shapes% h* h S# s" e" s2 f3 H7 ^. f
812643 SIP_FLOW CONSTRAINT_MGR Physical Constraint values disappear after entering constraint mode3 _ \( S/ }4 i5 g4 t
812835 CONSTRAINT_MGR INTERACTIV CM Custom Fomula - "Analyze" on the header of Actual does not analyze pinpairs! M4 n# k' n9 @. A- d
813435 SIP_LAYOUT DIE_ABSTRACT_IF Invalid parameter passed to ICP utility API& d: ]1 p9 R0 {6 O, W2 M
814060 CONCEPT_HDL CORE Read only library becomes writeable when updated* T6 r. w3 ~& T' ]3 h
814347 ALLEGRO_EDITOR ARTWORK It seems like not work ”detailed text checking” on 16.3.( T) y5 O& ?) h. i/ O3 J
814451 ALLEGRO_EDITOR DATABASE Allegro get crash when run dbdoctor 4 e; F0 b4 }" ^/ g! N8 w/ P814496 CAPTURE ANNOTATE Lower level part refdes resets to ? : r1 |. F! h' U4 ?9 R7 N; p815150 SIP_RF OTHER sip layout export chips output is not correct 7 u8 G' d Y& E2 O( p/ }816034 ALLEGRO_EDITOR MANUFACT Backdrill Passes not work from bottom# d* q5 C# s7 h" [* z. C' U
816065 APD DATABASE Export Libraries with no library dependencies selected creates package symbol without pins." F% T' }( t% I: R* l
816426 ALLEGRO_EDITOR SHAPE Dynamic shape not updated when component is unplaced , Y$ ~; H1 q6 @$ w$ I, H816616 SCM SYSTEM_OBJECT codesign incorrectly maps primary and secondary codesign object' f: n' C; z4 y1 s- c1 w
816686 ALLEGRO_EDITOR TESTPREP Probe Spacing rounds off 3 place decimal to 2 places : p8 I0 K, O- k: K8 d3 N% ] c816917 SIG_INTEGRITY LIBRARY Issue for loading interconn.iml: ]( B9 o0 j V4 e
816986 ALLEGRO_EDITOR MANUFACT Mfg>NC>Backdrill analysis with passes set at Bottom layer is automatically switching to top, hence failing!- @6 Z7 O- @9 R3 O- t
817473 CAPTURE NETLIST_ALLEGRO Backslash (\) is considered as illegal character for netname but it was allow in SPB 16.30.0107 V. P5 }. ~1 D, u/ E" i4 @
817606 SIP_LAYOUT WIREBOND When moving Bondfingers the Via's are sliding too when they should not. ! t$ G" `9 S8 w+ X4 X" F8 z! M' R: z, b2 A8 T$ O5 W% l
DATE: 08-27-2010 HOTFIX VERSION: 015 ' D9 L1 y7 Q4 G6 W( j" e) b+ m, s=================================================================================================================================== 6 }9 b. {4 n/ o. W$ }2 u: wCCRID PRODUCT PRODUCTLEVEL2 TITLE 6 V: D( U: i/ g) p. `5 _! f7 e===================================================================================================================================( P; l) t f4 [3 v% ~5 u
664821 CAPTURE NETLIST_ALLEGRO Improve error messages when netlister finds illegal characters in the pin names( H5 M! v9 o7 `4 x1 o H4 j: K) H
753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another- P; H- h1 L F
777559 CAPTURE OTHER Why the Reference designators get lost in project with external references.! Y* `6 o. ?* [: l
777657 CAPTURE PROJECT_MANAGER Archive Project causing Capture to crash/ z1 {1 j: a3 f' O
785748 SIG_INTEGRITY OTHER 16.3 SI model library path directives behave inconsistently if the ~pcbenv/env file is present , R. ]1 n: G+ f% h" k$ L H789529 ALLEGRO_EDITOR EDIT_ETCH Neck Gap changed to Primary Gap when executing Delay Tune command. 8 H, @* x& _; ]' R2 M) v791853 SIP_LAYOUT EDIT_ETCH via slide clips to 45 angles near BGA( T7 V6 L( L" W5 E, D
796604 MODEL_INTEGRIT TRANSLATION ibis2signoise replace V_fixture_min with V_fixture_max based on the value. ( T; j7 f7 }; |797657 CONSTRAINT_MGR CONCEPT_HDL constraints from the brd file are not passed on to the schematic. 3 b4 T; h& c0 |& Z7 v: P$ d802760 ALLEGRO_EDITOR NC nc route not generating the circle correctly+ ]) ^% a/ E3 i% n" c
803572 MODEL_INTEGRIT TRANSLATION quad2signoise fail if MODEL name include backquote. 5 A+ \* Q7 U3 Y803869 SIG_EXPLORER OTHER Trace parameters form does not update with correct stackup data ) i* _/ B R& D804070 ALLEGRO_EDITOR SKILL The skill setting objects not match to all items in CM.1 w! d( T. s; v
805641 ALLEGRO_EDITOR COLOR Clear all nets fails to remove the custom color on the Color Dialog form 0 q, F4 q$ g1 x5 n3 j7 p/ i9 _806115 PSPICE MODELEDITOR Cannot generate a Capture symbol from Model Editor because no Capture license. ; n; L$ Y2 J5 E806196 CONSTRAINT_MGR OTHER Netrev fails with warnings.$ U U7 ^# E& V9 } p9 H9 B' q, b7 I
806864 CONSTRAINT_MGR CONCEPT_HDL "Selected nets/xnets only" option in CM connected to DE-HDL$ Z, o0 q1 x) u7 j
807960 ALLEGRO_EDITOR COLOR Click OK to Color Dialog box and Shadow Mode ON/OFF setting will be lost.$ u3 F/ J7 T7 l1 d0 `
808155 F2B DESIGNVARI Variant Editor variant.lst and BOMCompare not the showing the same data 9 G6 g- S# w0 d3 B808392 SIG_INTEGRITY OTHER Cross section impedence not calculating for SPB 16.3 with single license for OrCAD PCB Editor6 Y, i; m% j, x9 n
808978 CAPTURE STABILITY Unable to Place > OLE object > Visio drawing file. Capture crashes as well- q' g& Y8 _1 K
809163 SCM PACKAGER scm crashing when running export physical$ D; X& y/ l2 X% x7 `0 i8 Y2 Q
809526 ALLEGRO_EDITOR DRC_CONSTR multi-thread DRC hangs when replacing padstacks0 E9 q# h% T" R) c
809587 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crashes during Text Cut/Paste operation in Symbol Editor . N( V& m" Y2 i& j# j7 e809636 ALLEGRO_EDITOR DRC_CONSTR drc update reports incorrect DRC count when run after deleting unused region in constraint manager. 8 S% l, o- p% K+ }5 d% h1 g809847 PCB_LIBRARIAN CORE "Auto add SWAP_INFO to chips" problem 4 ^. c# h! j% o5 H' o/ p2 ~810024 ALLEGRO_EDITOR SKILL axlGRPDrwText does not work for left justification ! z! D3 {8 n! ^) r( Y5 T7 d810530 ALLEGRO_EDITOR EDIT_ETCH Sliding vias on differential pair is not selecting both nets ( Z) n5 i# ~+ q! V9 h& ^810860 ALLEGRO_EDITOR DRC_CONSTR Improve Update DRC efficiency1 T: K9 I, d' d2 V" L( N
811506 CIS ICA Using Capture V16.3 ISR0013 “Save Schematic Part” option is missing in "New Database Part Wizard". / D, d. Q, E: I: T* [. v1 Z+ t# r812259 ALLEGRO_EDITOR SCHEM_FTB scm crashing when running export physical- AGAIN : H `& ~4 w5 }8 J812269 APD WIREBOND Wire diameter and wire profile automatically is changed when executing wirebond add command 4 O( {! g- Y2 {( t7 |4 d1 x812597 PSPICE SIMULATOR Pspice crash. * f" v, ]5 T: t812655 SIP_LAYOUT IMPORT_DATA Importing Stream data multiple times into a .dra will have inconsistent results, each import is different.% Y& O- v. H. y6 A+ x
813253 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro( v6 g% U* g; M, x/ M, N
813265 APD WIREBOND Wire Bond Report fails with wires present that were added with the "Add/Edit Non standard" option.6 l6 k. e: H$ v5 v. V+ a) l" Z
6 ?( z1 W) A6 f0 W( \DATE: 08-13-2010 HOTFIX VERSION: 014 6 H1 e% D$ J. `5 }7 ]# t4 s===================================================================================================================================; ^& q! ^, `, u% q
CCRID PRODUCT PRODUCTLEVEL2 TITLE & F$ U/ l2 X6 E5 a2 |4 V4 i0 ~=================================================================================================================================== + T g O0 o' z9 Q( r1 j5 R. O792354 CONCEPT_HDL CONSTRAINT_MGR Viewing a second net in SigXP from Design Entry HDL constraint manager generates an error % n* d! k# p5 |5 E1 R: e; f800336 GRE CORE GRE's Plan Spatial crashes Allegro. " D7 n) j0 v3 t$ S3 |801116 SIP_LAYOUT WIREBOND Wirebond -> change characteristics with only wires selected should not modify connected fingers' placement at all. 9 ]( A! ?4 A/ N/ X, k) e8 T6 v" T801463 ALLEGRO_EDITOR EDIT_ETCH The Allegro axlShoveItems SKILL function behaves differently in 16.3 than it does in 16.2.8 S- y# _ x) C1 `2 H
803049 MODEL_INTEGRIT TRANSLATION quad2signoise cannot translate OpenDrain Model correctly. " y! B! v% i; i* K9 B( Y% P803878 ALLEGRO_EDITOR DRC_CONSTR 'Via_At_Smd_Fit' not working correctly when the via fully covers the pin. & u5 d7 B) O, w+ u804273 ALLEGRO_EDITOR DATABASE Running update DRC gives different number of DRC. ) q& B! M W) B! C804330 F2B PACKAGERXL Packager is changing the refdes in preserve mode for components in hierarchical block 2 J" I8 C9 I; A9 ?# m5 P805335 F2B PACKAGERXL Packager fails reporting empty location values when the location values do exist' u, F7 C5 Q8 S% H/ k
805676 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic ( y3 Y# E0 r* {% w/ Y" t$ ~805747 SIP_LAYOUT EXTRACT Extracta crashes with this testcase and command file.' _' L$ X: j1 o, _) X" Z$ a
806028 ALLEGRO_EDITOR TESTPREP Allegro testprep parameters causes crash ) b, N+ X9 v" @3 \6 G) A7 D3 }+ h806120 PSPICE NETLISTER “Enable PSpice AA Support for legacy" option results to undefined errors : N+ F7 g, c& |806182 ALLEGRO_EDITOR SKILL axlPolyFromDB will crash if object is a pin on an unplaced component + a! U3 U0 }7 j/ l4 e' J& j& ~807543 ALLEGRO_EDITOR DRC_CONSTR Via at SMD Thru DRC not working correctly in Solaris ^$ I& g9 k1 p
808047 SCM SETUP scm not loading all parts from pcb after running brd2asa 8 [' ]0 c/ ]' N808831 ALLEGRO_EDITOR DRAFTING "Oops" command(in dimension angular command) crashes Allegro.' M! Y5 y; h0 {( Z
+ i1 ]! W' b/ s' HDATE: 07-31-2010 HOTFIX VERSION: 013 & q6 v/ A6 W3 A=================================================================================================================================== 7 x+ m) z. l x+ p- f+ s# ?; ECCRID PRODUCT PRODUCTLEVEL2 TITLE9 q- J T9 W& f. f7 q3 E8 Y6 Z
===================================================================================================================================5 S: p" a: ^1 N) Z
576133 CAPTURE ANNOTATE Annotations in the design getting reset to ?: e+ x0 Q7 I1 a0 w
688692 CONCEPT_HDL GLOBALCHANGE Global Change does not respond to RMB> Done: C! m* n8 [4 v! A- B9 w3 \& \; `) V. |
731045 CIS EXPLORER Double click in CIS explorer places two components ! v9 [8 D% K0 u' M e* _: k6 _763550 CONCEPT_HDL SKILL nconcepthdl in 16.3 no longer recognizes skill functions that worked in 16.2 ! W! H+ [: u/ F; ~# e/ f |764130 CONSTRAINT_MGR OTHER Export Excel from CM hangs/crashes Allegro on attached design ' K. N* S* x+ N3 Z' Z: c; S766750 ALLEGRO_EDITOR INTERACTIV Request to enable datatips when constraint manager is open and a command is active : `- a4 {' a+ Y" C" n774466 CAPTURE CORRUPT_DESIGN DSM0008 - Unable to open design in 16.3 4 k6 v- k4 k# f. S# o2 |* K! m777862 CIS PLACE_DATABASE_P Absolute path in field Schematic_Path causing incorrect display property 7 F& x- ^6 m( @' b" ~4 C( _782370 CONCEPT_HDL OTHER CreferHDL $XR hyperlinks do not work in PDF Publisher - they did in SPB16.2) N+ C" [* M* G; B; F
783036 SIG_INTEGRITY SIGNOISE Problem for Waveform saving with -w option in signoise command. 9 D9 A2 J" R. }! L4 N- v1 e# u0 t784205 CONCEPT_HDL CORE Schematic block generated from SCM needs to have DIFFERENTIAL_PAIR property on the ports5 B, B/ J( a& s7 Y0 G% f% h
786387 CAPTURE OTHER Update cache does not update the parts on schematic . P* g9 y: S9 r0 l( g) i% i786560 CAPTURE NETLISTS Sqare bracket [] is not allowed in PADS netlist.) r( `$ I8 u. K6 P) R
786808 SIG_EXPLORER OTHER RMB > Via_Model_Name doesn't display the generation param of the via.; _6 l* W6 L; J, @) ~2 n
787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet.3 c. U4 O+ G+ N- E2 M
791965 CONCEPT_HDL CORE group move should not snap to center of group / R1 |& r m% s( c792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets & V8 q: W! i. a. T9 T3 J794900 CAPTURE NETLISTS Attached design is not getting netlisted in V16.3. It works fine in V16.2* S0 b7 S% j6 ?3 E& n& [
795914 PSPICE SIMULATOR Getting RPC Server Unavailable Error ; `( A v$ ^# A- _795997 ALLEGRO_EDITOR TECHFILE crash when importing dcf file $ v' a0 W! Q6 D# G8 m3 h796124 CONCEPT_HDL CORE Messages overflow console6 r& K! d3 h0 }9 u f: |2 C: J
796168 CONSTRAINT_MGR CONCEPT_HDL Create ECSet in DEHDL CM moves focus to DEHDL $ W3 H4 R' s9 ^796378 ALLEGRO_EDITOR PADS_IN Pads_in has error while translating PADS 2007 asc file$ H# ~2 S: F2 \- {3 y
796658 APD OTHER Allegro can not import the property section of 3rd party netlist correctly.* `2 _6 z0 S( N
796926 CONSTRAINT_MGR OTHER Importing Custom Worksheet file does not overwrite the Description field.# M8 a! z( v. F
797387 SCM SCHGEN Increasing the grid units from 25 to 100 breaks the bus into bits on the generated schematic. ! X$ G! r; o# E0 h797529 SIP_LAYOUT IMPORT_DATA import BRD to SIP fails if database has partitions. even if only silkscreen and documentation exist & w/ h& V' m. Y n5 K797634 SIP_LAYOUT DIE_EDITOR rat control buttons in edit die mode are invisible until user selects an action3 E3 B- s4 S- ?& J! Z( r' j
797663 SIG_EXPLORER OTHER Current probe could not get from sigxp left symbol panel.! t% }# R' X' L9 }
798118 SCM REPORTS SCM report not resolved with CCR 697709 @# s) k1 ~6 O2 r; R/ f4 y798464 ALLEGRO_EDITOR SKILL axlDetailLoad not filling shapes in 16.3 s10' p. t/ E. P/ O& A7 N* X' x
798980 ALLEGRO_EDITOR DATABASE Unable to open board file as it fails with a error message Found bad data pointer, run dbdoctor.% S' Z4 U$ S' I* h( n
799445 PSPICE MAG_DESIGNER Magnetic Parts Editor crashes while saving newly created Magnetic component 5 v7 y$ I4 J9 b; g3 F799539 CONCEPT_HDL COMP_BROWSER PPT Options settings lost when cancel done in PPT Options form% J1 v/ g5 c8 ?) X0 I5 f
799957 CAPTURE CORRUPT_DESIGN Capture crashes while doing save as in 16.3 % Y9 h0 l, V$ y800280 SIP_LAYOUT WIREBOND Swappoing Dies in the die Stack will cause the bondfingers to move and create DRCs 0 A+ A8 F6 D% v" r' |800542 POWER_INTEGRIT SIMULATION Multi Node Simulation does show actuall waveform 9 Z5 Z# N T( Z1 m+ l% S7 Q' I9 E H800695 CONCEPT_HDL CORE Genview changed behavior in 16.3 HF 11 breaking the design hierarchy ) M' `( W9 a4 S C) G+ ~! B800751 ALLEGRO_EDITOR DFA DFA placement does not understand package keepout " R0 w' g; ~- {8 a7 j801017 ALLEGRO_EDITOR REPORTS APD Crash when creating Unused BB Via Report R/ B0 { O: S! D$ z9 v; H7 L# F
801043 SIG_INTEGRITY OTHER SigNoise Case Update seems to check ActiveDesignLink value incorrectly. 2 V- A. q2 C: V1 P801433 ALLEGRO_EDITOR MODULES selected figures do not end up in the module 6 a R# {& ~. c/ b* G A; w801705 ALLEGRO_EDITOR SYMBOL Shape symbol was specified with RegularPAD of the PAD stack become "Null". ( p+ R7 m$ B W) U" C802319 ALLEGRO_EDITOR SHAPE Shape status cannot be changed to smooth using suppress pads.7 N( ?2 c; s, n& B+ e
802474 CONCEPT_HDL LWB-HDL Testbench generator not working in Linux t& Y' r7 c" `/ k3 X1 N2 Z802887 ALLEGRO_EDITOR OTHER Adding the No_Shape_Connect property to via causes the application to crash. # ~! m$ y$ d; z6 }, C+ x: Y803393 SIP_LAYOUT DXF_IF Cannot generate a dxf file# F- b8 W: N$ A+ ]0 z F
7 x5 J3 U* D, K2 S5 {0 p% f
DATE: 07-16-2010 HOTFIX VERSION: 012; {8 Q. }; B3 G: r c( F- ~9 D
===================================================================================================================================, p; L( `$ a! p: O" s. S
CCRID PRODUCT PRODUCTLEVEL2 TITLE + x! V' o, i8 D, a===================================================================================================================================& h c* p2 N5 A6 a
757157 CONCEPT_HDL CORE Zoom (using SHIFT + mouse wheel) to work such that the tool zooms based on cursor location- c* t }# l: k0 _) C/ q. U
766639 ALLEGRO_EDITOR EDIT_ETCH via structure disappearing after selecting place manual hide icon.3 J: j. n$ A5 m9 ]
770910 PSPICE PROBE Printing from probe yields text label with too small size 5 W5 f: m' m* z' j+ D. V* |773603 SIG_INTEGRITY SIMULATION The characteristic of S-parameter model is different.3 n! M; G9 `& j! _0 v6 e+ k
774363 CONCEPT_HDL CORE hier_write didn't report error./ B0 X, f! B0 L
776991 CONCEPT_HDL CORE The Wire> Bus Name command does not use the Net Name font setting! a1 @$ x( Y5 ], F9 a$ ?3 p
781965 PSPICE PROBE Unable to add trace expression with small letters3 C! o8 z$ R4 x0 ?
782847 SCM PACKAGER PKG-10002 - Cannot associate a logical part from chips.prt% O% E+ s( ?' y7 ]3 I4 d- r
783245 SIG_EXPLORER EXTRACTTOP extracting net with trace on plane layer giving unconnected topology 2 ?. Y9 R8 [6 }4 a785320 LAYOUT TRANSLATORS L2A translation fails with error "output directory is not writable". : w8 R9 Y( k2 h& A. f) ^$ V1 e8 L785401 SIG_INTEGRITY OTHER The "View Geometry" or sigxsect command is not working in SQ 16.2 # A8 s5 ^. s* j/ ^! I785715 ALLEGRO_EDITOR PADS_IN PADS_IN fails to convert some components on Bottom Layer and adds two components at same location : \8 ~$ E8 \2 ^! C: m& |785868 SIG_INTEGRITY OTHER Unable to generate Parallelism report as the report seems to have hung the SQ Session.1 n* P( _; f4 i% \( D4 a3 x! c; C
788523 CONCEPT_HDL CORE selecting QuickPick toolbar button should not reset canvas zoom . _" X( j3 S A+ D! J$ g' }789333 CONCEPT_HDL CORE Font colors not being used as set in the SITE .cpm file4 ?* ?& A9 j' ^% e0 L
789348 ALLEGRO_EDITOR EDIT_ETCH Via Structures removed from database when switching to any App mode from Placement App mode4 p9 C& V3 t7 a4 C
789473 SIG_INTEGRITY OTHER Via delay is not included when t-point is at the via9 j( O& V/ B7 K+ M g/ U
789744 ALLEGRO_EDITOR SHAPE Update Symbol with cline at symbol level do not connect clines properly7 @0 U3 b1 j. @) j: l6 H' i0 c
790170 F2B DESIGNVARI Function of Variant Editor and Annotate schematics / l- o- X* K( \( M" J5 c L790811 APD ARTWORK Some Void shifts by the artwork output. # Q7 W6 N H8 \& D+ i- w7 i, \791371 ALLEGRO_EDITOR REPORTS Dangling line with cpoint not reported in the dangling lines report. 1 H/ t, p6 P- K+ `791486 CAPTURE PLUGIN_INTFACE Unable to open a PSpice Project by double clicking the .opj file, if Capture is already open; @3 c3 \' k g2 \# P, {
791663 CIS RELATIONAL_DB Relational view doesn't appear when capture opens second time' h/ p: |- ?/ k8 j2 w, \
791690 ALLEGRO_EDITOR EDIT_ETCH etch editing/routing in placement mode, allegro looks for all libraries adding delay in routing.* w3 l/ }% m3 u% J5 x
791720 ALLEGRO_EDITOR DATABASE Color Net param file does not have some nets with special characters in the Net name.5 f- i& J" `* W9 w8 _
791987 ALLEGRO_EDITOR PADS_IN PADS Translation fails with no error message! K9 U1 q# H* F& @. F$ B* q
792232 ALLEGRO_VIEWER OTHER Import parameters not bringing in plane colors in allegro viewer1 d) B" b( _/ r$ c7 b5 {) Y% m
792559 ALLEGRO_EDITOR DATABASE Error when executing refresh symbol command- W R& x+ i/ P8 X/ _( D! S/ ^
792923 ALLEGRO_EDITOR OTHER sted fails Can't open STED stroke file ~pcbenv/allegro.strokes7 U: R; E. A V4 z
793358 SPECCTRA PARSER When I try to invoke Allegro PCB Router it fails to invoke with errors.5 Q" z: E$ Q8 }0 u/ S! r N! L0 f% `
793605 CONSTRAINT_MGR OTHER Importing custom consmgr.wcf file crashes Allegro.! F) ^1 E/ T0 X6 G
793955 ALLEGRO_EDITOR DRC_CONSTR add connect launch signoise even so electrical drc are all at off 9 P9 G _' g; G5 I v794748 LAYOUT TRANSLATORS import fails with message not valid Allegro subcls 1 y6 [( J! _/ [2 \% ]" Z794775 ALLEGRO_EDITOR SCHEM_FTB Import logic runs forever or get a netrev error without any explanation / s# S/ ?1 C# Z6 n% ]795261 CAPTURE NETLISTS Create netlist hangs in SPB16.3& e+ J# v0 e! l. u% S( | _) E
795364 CONSTRAINT_MGR OTHER bookmarks are not getting saved in CM# g# |. ~ }+ ` Y) t( d
795410 APD BGA_EDITOR Using the Edit > BGA tool I cannot get it to modify the pin numbering of a BGA : l" N9 z' F0 J' v6 H795501 PSPICE PROBE Unable to see the Multiple Mark-Labels in Probe7 L% U9 ~, h" W5 y! v5 |
795761 ALLEGRO_EDITOR DRC_CONSTR Design is crashing while executing Tools > Update DRC5 m! j/ L& x z U2 I- t: M: Q
795770 ALLEGRO_EDITOR DATABASE void moves when upreving from 15.7 to 16.3( l; f9 @. X% ~& N" n! R
796026 CONCEPT_HDL CHECKPLUS CheckPlus reports text overlaps inccorectly on Linux8 ~' q o. i: F9 S: G/ `
796092 MODEL_INTEGRIT TRANSLATION ibis2signoise crash if Submodel section exist next to Component section.) s2 Q* J8 Z! m. X* |
796361 SIG_EXPLORER OTHER When dml file is loaded "Illegal format in device file" is outputted.5 I5 ^0 a3 C5 F, t- {% O
796366 CONCEPT_HDL CORE UI windows in DEHDL are scattered ( g- F: Y, s( i9 J) }; f796590 APD DRC_CONSTRAINTS CM Hole Spacing rule always set to 1905 in a new design. 9 H5 Y1 m& I1 ~1 c796858 ALLEGRO_EDITOR DATABASE Deleting layers that has only vias moves etch from other layer on it and prevents the layer from being deleted. Q: q6 T E- V$ K; _
8 R6 |' |2 z9 j- F
DATE: 06-25-2010 HOTFIX VERSION: 0110 O0 p3 ?6 }0 @& L- W! q
=================================================================================================================================== 1 h f |% y0 ?. W5 u' OCCRID PRODUCT PRODUCTLEVEL2 TITLE 0 j- }' C7 x5 ~/ w+ C=================================================================================================================================== 3 k+ i+ p+ m! w% }# ~/ r% t0 N W7 K644128 ALLEGRO_EDITOR MANUFACT Enhance Backdrill for HDI Buried Vias( f# T2 o6 g" d7 R: [7 a
743746 ALLEGRO_EDITOR MANUFACT Sub-laminate back drilling -Arbitrary from-to layer drill capability needed 6 z5 b% s0 z6 K, E773066 CAPTURE EDIF PinSwap information written in EDIF does not back to Capture schematic! ]0 J; d; j3 k: ~9 O& \
775690 CAPTURE STABILITY Design is not properly translated in 16.3 ) n8 Z6 D( x% z+ w782854 ALLEGRO_EDITOR COLOR Component Keep Out for the Top & Bottom layers not showin in the Color Dialog box, only ALL shows./ ? t7 p6 L6 [2 z0 o
784439 SIG_INTEGRITY OTHER CM of 16.2 recognizes the differential pair nets as Xnet.1 G, O) H: p4 x2 m) D* m
785135 CONCEPT_HDL CONSTRAINT_MGR Applying an ECSet to a diff pair crashes Constraint Manager& v; e, L" H/ ~) E1 p* Z9 P' O
785179 SCM OTHER Changing a differential interface signal to local corrupts the con file and ASA is not able to load# U4 i. p( ]7 k" [; P, A) ]
785332 SIP_LAYOUT LEFDEF_IF unable to def in to sip layout; x. y- @/ o/ [+ E- T
785423 SCM SCHGEN Schematic having incorrect connectivity' c* A: U% e$ @2 C) U! w7 [) y* X w
786858 SIG_INTEGRITY SIGWAVE want to select license at launching sigwave4 }) N6 B# F% W: a7 P
786871 ALLEGRO_EDITOR SHAPE Allegro dynamic shape not updating* C/ t% k6 ?3 l k
786957 CAPTURE MACRO If an off page connector is renamed using macro the net name attached to it is not getting changed" `( v) x3 A/ i5 q) ^, p3 t
787003 CONCEPT_HDL CONSTRAINT_MGR olecs crash in CM when rename librray defined diffpairs on this design.' }5 z( q& q/ @+ ?2 Y, H7 k0 ?
787087 ALLEGRO_EDITOR DRC_CONSTR Diff pair Static Phase tolerance Error/ {& ]/ g x# c! W) n# F
787174 ALLEGRO_EDITOR MANUFACT Reading filmsetup.txt file crashes Allegro P L+ H' X6 x( l3 I
788521 ALLEGRO_EDITOR DRC_CONSTR There is a difference of DRC between SPB16.2 and SPB16.3.6 o( h1 U% u- r3 L1 x
788652 F2B DESIGNVARI Variant Editor cross highlights incorrectly to Concept : W, ]0 q+ l4 F- X7 `/ A" i* Y788658 CAPTURE NETLIST_OTHER OrIntegra.dll netlist has inconsistent behavior 5 E. y# K* b1 \, v788718 ALLEGRO_EDITOR DATABASE Board crashes upon deleting Cline segments within BGA using Allegro PCB Design XL License. 8 M8 g }1 e. q" `789206 ALLEGRO_EDITOR SYMBOL Merge shape option causes attached *.dra file to crash ) G o0 K: X* w789324 CONCEPT_HDL CHECKPLUS CheckPlus output producing wrong values * \) `9 w( @+ W790049 SIP_LAYOUT EXPORT_DATA Offset wire tack points disables wire in AIF Output ; L+ x4 T) ?' o5 h$ M9 U5 h. f790503 ALLEGRO_EDITOR SHAPE Shape Void not correct ; d0 |0 D- w9 ` z* j) ^( |790567 SIP_LAYOUT TILING unable to run the ndw tile die generator9 ^ _( v7 s6 `
790622 ALLEGRO_EDITOR SKILL line width of internal segments within hatched shapes not correct when created using SKILL ' i, m1 B9 _$ l, R$ V# ~* A791075 SIP_LAYOUT EXPORT_DATA The shape that connects Merged Bond Fingers is missing in the DXF output. $ i8 \2 ^4 k8 K: ? ( s% s1 N: N6 X* g, \; GDATE: 06-11-2010 HOTFIX VERSION: 0101 w! t# e( k% ^+ f
=================================================================================================================================== 6 ]+ Z8 {: E0 }; S( q$ g* XCCRID PRODUCT PRODUCTLEVEL2 TITLE * ^. t' ^+ J* J9 o; U2 i: c=================================================================================================================================== 1 B2 z; h7 K1 t6 q' q701724 CONCEPT_HDL CORE Page Down (PgDn key) Key is unresponsive 0 e: t- g i8 c' B, P r722773 ALLEGRO_EDITOR DATABASE How can i add DUMMY NETS to a Net Class ?! f' H+ r' }, C9 E5 g& g1 ?1 o
767874 ALLEGRO_EDITOR OTHER Component Geometry/Pin number not imported. ! F3 @; x' Z+ ~* V! O9 E0 ~, i, S769644 ALLEGRO_EDITOR SCRIPTS Why Command line script in non graphical mode prints everything to the screen when working with Windows?" {2 {' }; g7 U
778086 SIG_INTEGRITY SIMULATION extracted net yields unrealistic resuts +/- 100v swings # e8 P2 Q9 T0 o# q0 i) [6 J778915 ALLEGRO_EDITOR OTHER Export library dumps symbols with mechanical pins instead of connect pins 4 ] Q. g* P9 b; f779119 PSPICE ENVIRONMENT MC Analysis does not seem to honor Custom Distribution - L ~( |' Y1 _# f779161 ALLEGRO_EDITOR OTHER Getting error-"illegal arguments passed to a dba routine" when connecting CLine to via: N7 t" |2 B, R6 @$ E, P9 ?
779335 SIG_INTEGRITY SIMULATION HSPICE sim from PCB SI caused netlist error.4 n; H1 K, ~6 R( }
780314 SCM UI ASA crashes on paste special.* a; Q1 Q# y( x* }
780345 CONCEPT_HDL CORE Pins look garbled when part is vertically mirrored+ W, `5 [( }/ {4 R$ L" X. B
780811 ALLEGRO_EDITOR SKILL Request 1k limit of SKILL API be removed.3 k) p. X9 J8 r
781111 SIP_LAYOUT IMPORT_DATA Import Brd to SiP failed * Y# \, y4 ] g+ v% T6 q781259 CONSTRAINT_MGR TECHFILE Import tech file crashes Allegro 2 [# g! V; [5 _% n# z781287 ALLEGRO_EDITOR DATABASE dbdoctor removes tespoints from odd angle clines leaving V/L drc6 z# ? r" J% t9 e) N5 w& S
781331 ALLEGRO_EDITOR SCRIPTS Script executed by command redirection operators is giving different o/p for v16.01 and 16.3 9 h/ A4 U5 F8 f" ]+ t* P1 I781647 ALLEGRO_EDITOR MENTOR mbs2brd is defining extra additional testpoint that is not present in Mentor database+ s$ G: }! x: z" S! {5 |
781650 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic phase tolerance added from the logic import & M4 ~: D4 d/ h/ A$ M- e" B! q781665 PSPICE DEHDL_NETLISTER Error simulating delay component " C- Z+ A3 u& W5 [+ e- O781688 CONSTRAINT_MGR ANALYSIS Application hangs on Solaris when executing DRC update* q. Z! o2 W, \7 ?/ Q! W9 S$ {/ L
781799 ALLEGRO_EDITOR OTHER Unexpected results when exporting and importing text parameters: g* f/ c9 L9 _4 D. T- [
781922 ALLEGRO_EDITOR SHAPE Pin doesn't connect as a thermal.& y* G0 W$ C( m
782124 CAPTURE PLUGIN_INTFACE Bias point display not getting updated for projects on network( H# a9 j/ x, Q; d
782415 SPIF OTHER File > Export > Router takes 5 hours to create a .dsn in windows....1.25 hours in Linux. 1 M+ x) O9 ~# a% o782566 ALLEGRO_EDITOR PLOTTING It seems like not work PLOT parameter "Auto Center" on tight paper size.) B B4 m- G4 B6 P! m" [7 \( k
782628 SCM NETLISTER Connection change not updated in the Verilog Netlist3 y8 ]- I0 X( y5 q' Q5 K
783059 ALLEGRO_EDITOR DRAFTING Create Detail with "filled pads disabled" doesn't work with irregular shape pad./ e8 f" U' G1 h1 U" r( j
783142 SIP_LAYOUT IMPORT_DATA import bga text in on connector crashing sip layout ( z# {6 x6 { O* C783222 FLOWS PROJMGR Edit Physical and Spacing constraints) Y% E4 N; Y% z! u6 a
783241 ALLEGRO_EDITOR PAD_EDITOR Pad Designer hangs when attempting to save to file.7 T- @ j p+ K" V/ O; _
783283 SCM IMPORTS scm crashing with import physical: g$ {+ J( ^) ^1 r
783301 SIP_LAYOUT WIREBOND All Bondfingers not sliding along path./ j& K3 a" v( h8 y
783496 ALLEGRO_EDITOR MODULES Problem of module placement. 1 x" ?' k1 c( _* n) ^0 P |5 Z783813 SIP_LAYOUT BGA_GENERATOR Request to add new JEDEC BGA sizes to the BGA wizards standard JEDEC pulldown menu.0 F# |- \) `+ G
784441 APD OTHER Users cannot delete layer even everything was deleted / W/ E4 [6 j4 }- ~& j6 V784639 ALLEGRO_EDITOR DATABASE both dbdoctor and allegro are crashing while opening this database ; U3 f+ q" X4 Z785100 CONCEPT_HDL CREFER Cross Referencer must not call Unix command on Windows platform # T/ f( s2 T1 V785385 ALLEGRO_EDITOR MANUFACT Allegro Crashes when using Datum Dim with Shapes./ H' q7 ?3 O' N, v/ i
( a4 w4 J. i4 }/ u8 ^2 K
DATE: 05-28-2010 HOTFIX VERSION: 009 1 _( ?, R# h, T, h; |=================================================================================================================================== * [$ b* D4 W5 j4 K, R bCCRID PRODUCT PRODUCTLEVEL2 TITLE : F" C9 x2 }. U6 O5 w- R! [ n=================================================================================================================================== ; S& q; a: \" D$ H# o758913 APD OTHER uncheck default check buttons through options/preferences5 ?% k f5 B* G9 }& _
763566 PCB_LIBRARIAN PTF_EDITOR The ptf command in batch mode always returns "abort" " a! |- S. q0 G* n* _. k763662 ALLEGRO_EDITOR INTERACTIV Place replicate update creates numerous DRC on win platform ' R" H+ @& t8 n771088 CONCEPT_HDL COMP_BROWSER QuickPick adds incorrect property value when ppt optionset file is used 6 b ?5 j% k9 L" N4 s772285 MODEL_INTEGRIT GUI Model contains recursive calls fater port rename reorder funtion is performed on it.; f) E' N9 S7 U7 F, G
774070 ALLEGRO_EDITOR DRC_CONSTR Allegro crash when sliding connections.* ^$ h! {5 m, K) D2 y4 ?
774880 ALLEGRO_EDITOR INTERACTIV Place replicate stops with No available buffer identifiers.# w6 R9 h, I& h. f
775443 APD EDIT_ETCH The routing of DIff Pairs when transitioning from a region needs to be smoother.6 d' ]6 F; _( @, f T" L: ?
776022 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we use Ctrl+Click in Etch Edit mode for selecting a Cline Segment in Allegro PCB Design L 8 I2 j F" l. y- V776151 ALLEGRO_EDITOR REPORTS Shape report incorrectly lists thermal connections for SMD,Via and Through all as Through. 9 `2 I# A1 P% f1 h" J& C776190 ALLEGRO_EDITOR INTERACTIV place replicate crash; select polygon zoom points " j5 Z1 r8 V, K) j( G- f+ r) w776284 PSPICE STABILITY 16.3 design crash while simulating the design 3 n! F, r3 e1 V2 r' J! U6 Y1 S777556 SPECCTRA CHECK interlayer clearance output drc even so layers are separated by a power layer : Q, [: F! s9 x I9 d5 \777689 ALLEGRO_EDITOR SHAPE Shape do not void if Curved Fillets are used) n3 K1 E$ F4 `/ e9 B: ]
777698 CIS RELATIONAL_DB CIS 16.3 ISR s007 - Relational feature doesn't work6 j" p( m8 z* W* @
778042 CAPTURE PRINT/PLOT/OUTPU Some text are not searchable in Capture generated pdf * N# u; @4 O% \2 ^% a, s778350 ALLEGRO_EDITOR SHAPE Multiple Drill on pad gets round void instead of rectangular( {+ W$ F" t3 }, w
778356 ALLEGRO_EDITOR SKILL Duplicate Vias with axlDBCreateModuleDef+ u1 a# d* g5 `, v8 b5 q2 k
778782 ALLEGRO_EDITOR OTHER Display-measure and axlAirGap incorrectly report no air gap for multiple drill pin7 E- S8 }# K. I# N( f
779146 ALLEGRO_EDITOR OTHER Moving component crashes Allegro 8 `# i+ ?8 v$ D4 o& {; J780213 ALLEGRO_EDITOR DATABASE Design saved in GXL when opened in XL gives misleading message.# Y$ r: c4 o$ r2 M& U
780773 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge , ?. s. R; y$ ] l& |. k- a4 A' A' k' T9 y8 m* n; [
DATE: 05-14-2010 HOTFIX VERSION: 008 " F/ I1 c8 f# Y# v===================================================================================================================================! A$ a' g7 B% x& y
CCRID PRODUCT PRODUCTLEVEL2 TITLE + n9 Y9 w& u) {# d4 g=================================================================================================================================== . H4 z7 B2 D4 c/ s8 v9 v697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line “defparam <instance number>.SIZE1 \+ T" q h9 T- A
734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace. # _7 _0 b7 M Y5 f' J! V0 y738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom 2 d3 }: l% |- U/ o8 @$ S+ A744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen ; ~% e8 O7 b% x750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace- g7 H& \0 J2 ?) K& F4 `- \
757024 CAPTURE STABILITY Capture crashes while exporting to EDIF$ J/ W L! S1 }" x
759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design. ( V3 }- O* t3 \1 b$ N+ X1 F760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd 8 Z5 D# N, ?9 o761391 SIG_EXPLORER OTHER Incorrect rise time 4 [4 u3 B, Q: \& {- T% @# r1 K! r762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken. 2 I# }% l' ]# S762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance4 B9 Z' g p$ H$ J9 w
763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67 . v: y3 p8 I9 \% R5 v763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape. + o) k$ z. ]$ x' u# ]764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor.2 e+ u$ w& d; E- J; }
764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine, z1 M+ D L' D7 @) x9 |9 K) h
765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption.0 ~& r8 |: X. k: _
766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias 6 K( g/ f& M* a: Z- t' z766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information7 h1 |- T* @# ^# E( t4 v
766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area Z5 \) }1 O6 n5 ^- i. s0 Q767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid 8 f+ Q7 T5 P, P. y7 J8 f7 Z7 W767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3 1 D! ~0 d5 Z0 a' q767526 FLOWS PROJMGR Project Manager customization does not work" O, I. A1 ]/ a1 N
767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database. 1 J! ?( J; E9 t! a# c767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name + {9 o( W# v& }768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation+ r3 ]3 K# M: M' t! l
768207 CAPTURE STABILITY Capture crash while editing properties' @: C2 ~' w9 L( T& n
768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet.9 J( {3 R5 c) q0 J
768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time./ e: ]- v* c- x% J7 F! P0 U
768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2 3 \2 F! E) F& g: m @7 ]. R$ X769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running5 T3 i6 |( _6 [# r s" P
769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd q+ l0 n0 w! q) F0 P- V* l% G769326 CONSTRAINT_MGR DATABASE Length by Layer crashing: v3 B: v$ O$ z; x$ h) Z
769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses. $ p' Q) ?* R1 W4 |769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper' Q7 S; q" L; d! u: k$ t8 U
769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule.8 H9 j" g9 i( Y2 k
769934 SIP_LAYOUT WIREBOND Duplicate Finger Name.. _& i9 j7 s; N2 ^" T6 c. g, }: a
770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol. ) g `3 a3 n/ Q8 j8 g5 F- G# t" Z770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas2 i6 V- k I' T9 o7 X4 P+ D
770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board 1 M5 z8 f7 O( z& |. `5 f7 i+ S: K$ ~770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property.5 z" G2 b' o N$ B9 H6 i3 `
770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended.! D" J* H* E( n! f$ o1 O4 K* D
770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties / e! f; Z+ n+ S4 M770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell.. _3 P5 y& i4 C2 w) G$ T9 q
770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message/ ~! r& l2 Z7 q0 N6 `4 ]
770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well$ t! l; `/ _& v6 Z" X& h
771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006: b8 n0 `1 F8 A
771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them. % {. ]9 O9 S$ E. E5 u& }771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes 6 `" M! v8 g( C c771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program.) N9 r( K5 H8 l9 |- F
771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys: c g0 C o0 n: n6 L
771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license. 3 G ^: T5 m$ w7 S$ r771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol 5 x, y* W q6 r771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database. ; C1 A1 U( |% q3 W/ O& l771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP) Q! q4 j1 t/ E6 M
773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile- F) |( Z$ ]( m6 Q9 G
773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined" ( n$ O# o" F ~773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer.% N: z0 I% N: m1 b/ o, b
773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS ! a# Z7 H9 x, J- t* C0 H773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon. 9 L" Q0 |8 d3 |" Z" j; l* s) Y) r773483 ALLEGRO_EDITOR MODULES place module problem8 G) {2 U0 G' t
774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command' q! y l; n% F1 a3 e3 B+ H
774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails3 F; z D+ h6 R* u) W
774602 SCM OTHER ASA crash while working with hierarchy # o2 D, l- L' ^( C4 [$ b5 w5 ?774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes 0 X9 B9 p! i1 U7 z; i5 R9 D0 s775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands/ w/ {+ r1 c. |
775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog7 i/ v& t) }. }- E9 s
775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design" S8 |6 {; l: K
775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0 # g3 t- S; v' b: p8 U4 m! x3 T% ?5 s$ w
DATE: 04-23-2010 HOTFIX VERSION: 007 & A: w) S5 m3 o! F8 P+ c6 S, J=================================================================================================================================== - v* E6 B4 O6 y2 ?: W' |7 jCCRID PRODUCT PRODUCTLEVEL2 TITLE & v! O* H$ A$ p5 w1 P0 K5 j===================================================================================================================================8 h3 X+ P1 T3 U/ _4 d3 Z0 K
721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why? + P# J7 a3 u9 A" [$ c740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp 9 b% }6 d3 T" L+ q$ l; G( G744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools . }/ T: H- R- O, P! `2 Q6 N* Y747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0. ! V+ D0 v! [4 C& D/ q5 I6 b' |$ J747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash.* K) o$ E4 Q! {
751372 CAPTURE OTHER Copy / Paste Issue in capture 16.35 U* t5 L v! Y2 @
757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit.% E' c9 [4 y; w5 }% D8 [: w+ H
759906 CIS PART_MANAGER Property copy from one to several parts doesn't work $ R% J* {6 F3 g% v( R, p- |760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result$ ^( ?) C5 u5 d# v
761177 CIS OTHER Error Message - Memory exhausted 4 ]) Q2 R$ i/ b! E$ e+ K762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location. . `. _1 F+ ^# k/ X2 R' U763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed.' c% C+ q' ^8 a/ v. Y. ^( \/ Q
763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created. 0 l. S; H6 u& L: A763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager? 9 {+ o3 |' e" I E! `764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3 ! c4 U# G1 k7 ]2 [764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle. & Y7 j6 m4 Y+ ] N% |764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad : K7 F: l! Y: Q. [8 y7 m9 b) f1 B764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3 8 H4 l% k0 z' A# C- `765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro2 l p! ?" `( n* R- r1 ~
765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question # w* N3 e3 ]4 `: d s8 c# L765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape. ; L/ y5 L& U% a1 x- `766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle & V: m" W, O# q! {766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design* o2 v: W- [0 f a
766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.31 S: Z+ o9 W7 K7 i% q
766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit! p, s" E( j. ~3 s! f" c" O0 {( K
767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version.4 e: a, s& n: ~. i- a
767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step.2 m9 l& S: `# }! ? J
767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs. 7 v1 @0 `- T. H0 s- F- ~4 H$ \# n: f* Q0 Z767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly- Y9 d9 v- t- G# r; }* U
768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy. 4 _( E. F' S; S, K% ~2 [769150 CIS PART_MANAGER Update All part Status on a group changes “Do Not Stuff” status to “Stuffed” in V61.3_ISR_5. S" B2 k& o" n" x
3 n3 r3 Q4 q* i' w$ J: \
DATE: 04-09-2010 HOTFIX VERSION: 006 : D% y P2 K2 K0 c# U# c/ `4 O=================================================================================================================================== Z) i- L1 p3 C6 z( o
CCRID PRODUCT PRODUCTLEVEL2 TITLE7 w) c2 {8 ^! a' @0 w+ }: N% `' @' n
=================================================================================================================================== * Q, c6 M* t: n3 V# d. H2 w" N; t5 V745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC.6 y* K+ U/ w' l/ Z% |8 G! ?
752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux. , ]9 w' V( u- U H2 {8 o6 K$ c" L753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol4 c, {5 P% b5 e% U& G. |8 G, C
753894 CAPTURE OTHER Case sensitive version control S/W h; W8 a1 Q9 Q4 l: S6 w6 M8 L
754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues?9 z y3 D8 L. b/ N* v* c. E5 i T7 B
758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application.1 a+ `+ W8 J& V9 p; c
758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project% f: A. y2 Z$ T3 I+ L5 O
759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes.. r) x4 {8 J+ y" i; X1 Y
759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets5 ^. J1 `' k4 a9 h
760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing2 z7 C. }: K& O) D
760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid + y9 \5 i4 A6 B7 u; {( Y# f7 P760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity 4 w. ^4 [1 B" [2 F3 j/ C& u760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database.& _# q# S2 e5 N6 H, F
760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2 ! n0 \- K+ \' W760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs) }( J) n+ S. w3 v; E
761114 PSPICE PROBE Refresh issue in Display > Cursor window 4 g- R' ]$ z; F* \4 L761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks.! c1 y8 _9 T1 z4 V
761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items. 8 K" B5 ~ | \7 C. a4 @8 Y761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ? 2 Y' g# P6 }: a' T1 H761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines# z Y; H# _! J5 ~
761492 ALLEGRO_EDITOR SKILL about axlTransformObject function. _0 r9 C A+ @ X; d: Y
761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual ' F U! Y, _' \) U& [* E761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file 3 A+ e' t+ N3 x! |6 g6 n762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs., O+ K0 F! _! a/ C- J) F
762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files3 h% c7 {$ h& A7 D. P( t
762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file 7 t/ d8 ~8 z' S2 F4 h' ^7 Z! N762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3% I# P% {/ } m! h4 e
763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself + N! n+ B! Q1 N* S% \763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values.+ r) n4 Y, c1 A5 O; ~4 \; }' k
763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0. S2 r9 Z4 ?1 I2 q" A F: k3 b* `9 G763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM 5 p$ m+ ~0 F+ v# P: G763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper. \7 I4 I; [7 Z1 \+ b5 O
763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205) 0 @9 w3 r" i* ?4 D# I3 K& I/ v g763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator0 p! }7 c1 D3 o
763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro.% e0 a( V. }" R/ G, e# ]' ~7 L: U
763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill: D8 ^! ]7 W1 R, q( T+ ?% S; i! E
763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets. 0 k+ v2 n, X/ Z. V( G' U( k763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM8 x9 z3 @8 q8 U# P+ c, R0 v8 I, m
764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin. , }# Z- ^' ^; c* u4 q5 [5 ~! c5 h8 y& a( B, m
DATE: 03-26-2010 HOTFIX VERSION: 0059 K9 w7 m+ U2 O6 ~! O+ Y
=================================================================================================================================== ! f% J" [6 {# g1 RCCRID PRODUCT PRODUCTLEVEL2 TITLE " Q% e+ b( I+ x. C=================================================================================================================================== 2 b+ c6 p4 z( G/ c' {5 v, @599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer - \# M1 K7 @9 _" _( ]735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type% n; d* d, }5 S6 c1 _( A0 a: [
743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist.- l5 p( W# A1 N7 O
746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting* T% ~0 H$ t, u
746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module.* Y% f5 [( [9 G# Z
746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory% v3 P i% t6 k, K" L
750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390)7 E7 B' _2 F% f) i( ]: z! @
750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check 0 o- h4 [, l5 I9 J8 [! a! f7 ]751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation4 i* L# A9 Q+ b! m/ L$ s
753834 CIS LINK_DATABASE_PA unable to link multiple database part }6 B8 M, t ]9 i3 S+ V2 S; w: ~
753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3 ' e V6 B" I3 P" |754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix! ~3 o+ s* V+ V6 G I
754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group2 }0 b1 M4 u7 J$ f2 [, m* P
755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3.( f7 Y# D$ U8 m L3 K" y$ q
756131 PSPICE SIMULATOR Capture crashes while re-running simulation - A2 {& }8 A& P: O5 k756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163 + h' F# L2 j' [2 S756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat ; _* u+ B5 I7 g; ^ \7 i; m! g756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window. ( H+ M9 ~5 o2 |- t756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed 9 W9 f3 ]" B6 G! {! q" ^: ^1 M/ W756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities?' M( J5 @3 O. z6 j' U7 R
756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool; N- H4 P% Y- t7 Z/ r2 d1 ~
756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.36 h" J8 j6 s9 _3 Z) E1 S
756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number . Q: ?5 `! q1 @8 e9 Z9 Z% U756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3 8 s, m+ g) I7 Q757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created6 v$ |. o" u" R4 U
757406 APD OTHER Implement Segment over void features in APD L 6 E" t' Y6 U! _- W' g: @7 k" l! X757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology- U( E7 i; T9 f, r8 h
757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad ; ^% l1 c$ s2 U3 l1 P8 [758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another. v# k. P$ t, u# g6 H
758022 CAPTURE DRC Capture crash while running DRC with “Run Physical Rules” checkbox." F1 b2 X- q- l% b8 N3 b
758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design: W# E1 e; k# q0 Z: b q6 s
758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor * ^2 _! l; G0 k9 ?1 ?+ |# q758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values. 7 R9 ~1 B0 B' j2 u8 K758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2 8 c0 Y2 Z9 C! h4 S. p5 I$ d758498 CAPTURE NETLISTS PCB Editor netlister hangs % @7 v# \ {8 ?5 ?( P, X758584 APD SHAPE Shape not voiding all elements' ~4 D5 N r& j. j7 r$ y
758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report ) Q( D9 Z5 ^ ^) a& F$ p) _( S9 v759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version.) ?& y9 N* W* x, X& e
759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x. 3 J+ v [" ]0 R) O4 \3 T759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message / r' V4 i$ P' I! E7 K( ]# ]& o759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM : k1 F1 J& n7 i. t# s759947 APD OTHER Need an a way to convert Lines into Clines% v: S$ l1 f& F
760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen 3 P2 s5 l1 K/ z* N7 R- t760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import. k' m0 t9 J- R B0 W( ~" ?) P6 W8 o
760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ". ' H' h* b) ]2 k8 l- f! d" w760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl2 ]8 {- O/ k+ C$ q4 w5 H
761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT- g- `- C: Z9 W8 r+ g9 h
1 I( k$ n! Z7 Y) l- i# L& d
DATE: 03-12-2010 HOTFIX VERSION: 0042 B9 {, r( T h$ p3 M$ K9 f( c
===================================================================================================================================' V1 a" H5 e5 s& J. t* k+ B9 ?
CCRID PRODUCT PRODUCTLEVEL2 TITLE( v+ v3 V; C; @+ A) {7 T
=================================================================================================================================== 0 J* q$ t5 o, m" v9 N689495 ALLEGRO_EDITOR DATABASE corrupt database 4 S( y) Y+ q- C725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands( x X$ B' D' {8 ]
732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements.0 K2 J/ }7 w& {- }7 u7 c$ x9 X
740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results( @2 h4 o, C( L# d6 w W! f
744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse0 V. O2 A. m# t4 [
745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.71 ?, {/ l" Z( p% L5 P h( h
745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block ( I% g# V& M+ [: O5 c747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save; X* A3 O" h8 @2 a: C8 Q& a7 e
747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture 3 z+ L6 Q" ?0 k: m1 \( Z- x750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints8 l" n. M* d7 z; C8 _6 M$ j
750777 SIG_INTEGRITY OTHER Trace impedance showing wrong / u$ x L+ S, s3 y% z751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout s5 F$ I5 T( e0 z7 H
751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool & T6 [/ a' F/ ^* k0 U' a752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment - D7 _. t% T, I3 b) ]6 X- J" a752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers.( X1 F6 W1 K+ [8 x/ @
752581 PSPICE PROBE Pspice probe window crash 7 R( O/ o9 I; I1 T; L752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block , h5 ?, @- Z k; ^* a752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer; {2 T+ o6 D$ y' ^6 c3 ?) o. [
753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options / V6 [) d; u7 h3 O( A6 S0 Y753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir . i0 R1 E k$ ]/ g* Z753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad. 9 z) q+ L* H+ Y7 D! f% m2 w753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes2 q( E, U1 E8 v3 S' T
753866 SIG_INTEGRITY OTHER about Select by Polygon after move command, I6 X$ k [1 ?7 t( ]
753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN. ) i& I6 c u8 j8 Y& _754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible* R4 D( a! \5 I+ M- T; R1 H% l
754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number % O) ~) r# b, T$ I8 D+ U, |" R754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired.# E# s! ~/ T& W' U, j' x1 V. A
754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication * s; H) r+ `1 Q6 y1 }3 f# k754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill 4 |1 o2 d0 x& E- V1 i Q754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves, Z4 k6 ?, g( v: V5 a% E
755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file & b( B# I$ ?4 |9 t. e# `% [755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3 7 S9 ?7 O4 b% Y: Y: ^6 b755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border 0 d; n1 ]0 t( C5 ~9 C755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command . X8 r" A& S, Q. w755881 ALLEGRO_EDITOR DATABASE Swap component crashes application6 @8 k8 i/ ?7 K; J6 o$ b8 `
756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits ; h! G( ?/ i6 S( j& E $ d) W# p2 A: U! DDATE: 02-23-2010 HOTFIX VERSION: 003 2 y& Y0 F* N) B! v=================================================================================================================================== N5 t; h. q% a& P {
CCRID PRODUCT PRODUCTLEVEL2 TITLE. {& m2 `( `, G* S
===================================================================================================================================# @$ B2 L+ ~. c6 P# N' ^$ D/ H
263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design ; B" Q# _) q7 a/ K) Y0 c$ ^' Z0 u726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results ( c: S: v1 b$ `5 b730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash ' i% R$ r0 u* S# q9 k: \1 b735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in ‘Zoom to all’ view in V16.2. 5 C. N# Q5 |5 C737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models 5 Z7 R0 a4 B: [& R740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol 0 L* o0 O; n0 P/ o8 C; Q7 o/ S744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement2 U; c. i. l- l. P
744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature : j3 a. V$ g4 C# A l746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra.2 M0 V6 ?3 f- H# x
746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave.3 Y2 s% E" s; l; A$ m* @. x/ ^9 g, d9 l
747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles2 @) W5 _; ^3 s. ?0 L
747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail.4 t9 q# Q2 |0 C9 P; H. i
747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file# S# A3 G, K+ s6 L4 H9 w- A& d
748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle ) v9 u9 y ?3 b$ m% u# B748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly0 y. h4 i' V1 X0 R: i" U
748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash+ f7 Z# c! z$ c3 R5 m2 @
748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC # V/ N O' @1 i; M5 Q1 ~748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open$ d4 A: A7 u( K( F) ^2 K R2 V p& Z
749009 APD WIREBOND a part of function of the finger alinement doesn't work- H* E6 A+ w) c. F! o% O
749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel 6 j- P: d5 I* b) i8 C* b2 `749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write" d7 Q. L1 \7 j% l# u t8 |
749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3% J0 [3 ]- \* \' p* d
749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design.+ V4 i: r" ~, T, {
749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions 8 V8 P3 @" J. @ @6 _749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001). + U. y$ c+ w% ^! A- j! v750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 12 V$ ^: r* m! {' }$ C
750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values.8 M/ T6 @4 H q
750888 SPECCTRA ROUTE specctra is crashing while routing' u1 v" S: X# f+ X/ j
751204 F2B DESIGNVARI Design difference crashes while reading funcview 1 | T( a6 _9 Q+ \6 u* t7 B8 c751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline 8 N5 t$ D# \0 g751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion9 P+ B$ F# h/ X+ r* E* h
7 v6 e6 d/ D2 X$ i* k& \- ?DATE: 02-09-2010 HOTFIX VERSION: 002) o, `# M7 ]) f9 ?( w y
===================================================================================================================================4 E! Q I& R; N% e4 H7 Z4 F) Y; J
CCRID PRODUCT PRODUCTLEVEL2 TITLE ! p5 b0 H! A. ]' g1 l+ ~0 T=================================================================================================================================== # @. i6 V: \; \8 ]0 y1 l527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop w n4 Q5 K* }$ e! x
623678 PCB_LIBRARIAN CORE PDV freezes when changing grid1 D2 M- |- r; J7 Z. |* U4 |0 X% X
672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added; r9 C3 B1 q; `; `
688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols)( j% e n% E0 ^. H$ }% t- _
710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed. 2 F& x$ d, q D) O! }# P710174 SIG_INTEGRITY IRDROP Audit function for IR Drop. & ], Y$ _. n% p726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice: {; G2 L! M2 C) q& P6 \% \
730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up , J8 j7 \' k( r& ?- x& h731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run5 j! I) U- F( P( w7 ^" I
732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist- c8 J$ @- H5 k" D o2 M
740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files6 w, o' _2 [" p
740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design : e- b0 g8 N$ e7 }740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3) P1 b# H2 I5 K. o
741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash' q% e2 ]4 [ R) [
742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route$ c- @: o- ~: q. Y9 a0 v
743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun 5 o3 j% I" W- Z3 J8 c7 P8 g743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks7 U1 g m: l, x# t
744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report.$ ~" M1 y4 ^- g1 U0 z3 w
745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section @; `. g! _* }# d745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer( r& h' \# @: ^
745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component 1 b" W' X/ P+ [745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in", e3 i) t1 W. ?: n. ^, ^
745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates/ q1 V3 J$ h- P4 V
745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked. ' d }/ J1 K( k% T7 b746002 CONCEPT_HDL CREFER Could not find pc.db in the root design $ P; q U. L$ m+ N9 Z# U746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in ) J# V1 ^" U% a7 S* @9 S746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software4 T+ i* I( x' T) u3 v. c
746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes% ^4 q2 b& M/ _' X
746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design0 z, w; x3 x: n4 R' K0 g
746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition. : r0 X. ^3 E+ G4 d746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification , g5 m& k1 ?0 Q, N. Q+ g+ T0 g n& I746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all.; b( z/ B) I6 x$ H% q7 |3 H9 Q. g4 Y
747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file4 Z) r- g7 c# f- L* D) p
7 U* ?; {- l% H F c' n; c" n9 B* W. p
DATE: 01-31-2010 HOTFIX VERSION: 001 * Y) o, A' k$ d7 J0 y# W+ T=================================================================================================================================== ! y/ n9 x* n8 {8 \- x8 hCCRID PRODUCT PRODUCTLEVEL2 TITLE 4 V5 p. X# A4 s$ M" Z i===================================================================================================================================2 u6 `& z* c( N( O4 R" R9 L
491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute 8 H, M2 h+ {$ H" h2 a$ k* m496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation/ [+ b: o" K2 [$ m( }( s
558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files?2 C( W- d o6 f
643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache $ X3 p" C3 `. z" |$ m4 p% D' f654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2 $ {* A0 i3 m X- m# B) m) e7 e662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset 8 I7 h7 o' Q- \& d2 u5 F9 `672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt . p T( l0 n/ r" r" B676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots9 l; a; U$ x3 R' k* f* F9 R. m
678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM 4 W9 ^' s5 Q; d( _690618 F2B BOM Write protected template.bom fails to write callouts4 `. g) X7 M P8 m
700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS8 ]; u0 w3 U$ k4 o# v* D
705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview. - h) {& K: G- {9 R0 Y7 h708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.2$ L& ]/ D, r4 `4 W$ _. G. x
708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor. ( }- V" ~" e* _709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols( I! d3 C* ]' R$ I/ X
713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run% D% O" C! T' @7 W
718119 F2B BOM Exclude the callout file name from the template.bom file 0 @9 `7 i m1 h2 A' t% O718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart. h" c. H6 g' S: p2 s
721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list + {8 X/ p% m% n' k6 N721788 SCM OTHER SCM unresponsive while closing out a Block without Saving* Z) W3 l: J% L* |. j( e& K
721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design1 K y0 n4 t) _8 p
722653 F2B PACKAGERXL Packaging does not complete ! ]& j) k7 L1 i. R725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script. 5 z& t6 H D& }725719 CONCEPT_HDL CORE wire pettern of Publish PDF 2 ]2 C7 |0 [: ]5 H727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view . w" E. a H% ^0 F$ t$ ~727194 CAPTURE CORRUPT_DESIGN Random Capture crash ( k1 H& p1 P: J6 |$ ~1 `' ]% t727704 SCM PACKAGER ASA to PCB getting out of sync: P# b2 r3 _) C* J
728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used7 |4 U- m9 Z6 W4 V2 o" y7 S/ Q1 A# C
729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash. X0 O" f1 ~- ]1 O) a) {
730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly 2 h- P- B# w# B# H1 w731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29)/ g% o+ d! F L# z* c* K& s# Y
732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape6 }/ ^6 {5 y. d! S
732138 CONCEPT_HDL CORE Cannot change SI model assignments4 L& W- F( i6 j2 n
732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file + R, B# h- p6 b/ f# ~4 J& g732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only., U x6 C4 k9 |) {6 P
732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes 1 I7 L- m' j( @$ t733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment2 Y, {( p2 }# B8 w! b( n# u/ f1 ?
733773 CONCEPT_HDL OTHER Syntax issues in DEHDL0 n S( ?7 V- A8 O( Q$ j S
734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off. : U+ ]% i7 S' _# y1 I# a' u: p' h734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA8 [6 G- H& s* j
734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints 3 C; D9 B4 o* x5 B- w' A735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues. , w9 {( P. S$ N- |5 _; V) m735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties: s8 Z, c: ]2 D: g4 x; P. E
735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message % O0 w/ j" ^2 D7 k- b" D2 g. b736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch. 8 @+ X6 A* C D0 @/ Z D$ m& W3 Y736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout"- O- M6 M; V6 C# z( n+ H3 F5 I
736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser , v. M/ w6 { Z- s" O736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge- @$ y5 Z& P! t' N: @3 p9 }
738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version.( `- \( K% R" ?. L9 Z9 d& j
738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license4 _+ j F5 {( X$ [) q3 q" m$ g* P
738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3+ R N8 q' e( J7 A4 u a
738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly 1 E+ J- C0 B& A- `% O8 N* N8 a: U738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing& y! I8 Q7 e' d) u
738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux 7 P. R- N' P) a# L8 ^+ y) x738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE " b$ b* }9 o* \; [- u$ K0 R( g739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched. ! j) Z+ Y& U8 T# X1 H, q- x739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option 9 `: a4 J" Y/ G0 j3 B739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic) x; C. n4 E1 v- y2 y" ?
739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro. - P( I" i* w5 j+ ^ B739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X4 r3 c* k7 b. n0 q" ?
739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax.8 p% N q* U$ M! b, r
739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3* P) M0 w T& Q
739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model 2 O7 r5 }7 \2 |9 P: ^739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models2 o1 `8 u1 m1 x; F# I9 L9 N
739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy ( g' Y: [1 w E9 U740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever.1 }) H7 e, E' F5 T) ^: _6 M
740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared& O5 y3 U9 `& l
740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design.5 K9 c# M4 k% C" N( w1 O' y
740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.29 d# H9 E* j* I7 \
741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message ( j; g2 h2 i- q o( \! j741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro, M- o0 ~* G) R N
741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.33 C$ r8 W& I& V1 d* s0 ?* {
741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog 4 t, g& Y; j. Z. c y# _* W741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd! X _ t/ X# S1 ~8 r0 t- Y3 _
741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs. + F6 w" x5 r& A741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias. % Z3 U/ X `" d. \; M4 @742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill. 9 C N/ w* d) `3 V' U- ]1 n743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file. + v W! x; @5 y/ o. Q2 X3 W743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate.( B- z. [$ w* s4 u& s
743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly3 i+ w4 w( W2 D5 B! i7 d
743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads# r p. X2 k3 [6 }3 l
743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update 2 Y1 I4 B' e# w743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM# m& q5 S8 W3 N; N 作者: elm99 时间: 2012-1-12 20:31
谢谢lz分享！作者: 志在超越 时间: 2012-1-12 21:11
谢谢 ！作者: weilaiqiangren 时间: 2012-1-12 22:25
我装了，但没有破解成功作者: MentorUser 时间: 2012-1-12 22:37
Thank you kingt001 for your sharing !!!!!!!!!!!!!!!!!!作者: pckiller0308 时间: 2012-1-13 01:27
Thanks for your great sharing!!作者: yiki9292 时间: 2012-1-13 09:53
谢谢分享！作者: leonqin 时间: 2012-1-13 09:58
谢谢分享！作者: jacob.ning 时间: 2012-1-13 13:01
谢谢分享作者: panadol 时间: 2012-1-13 13:27
Thanks for you shares! . m5 o: ^7 ~9 {% s4 [5 b. @作者: linsky2000 时间: 2012-1-16 13:34
谢谢分享呀作者: wab_up 时间: 2012-1-17 17:02
谢谢分享。。。。作者: marblej 时间: 2012-1-18 08:51
xie. xie.作者: suiwinder 时间: 2012-1-18 13:02
cool : R( I. `* U1 G% {1 ^: J/ S xso good6 U9 m% K: h5 S& E y9 d
thanks a lot作者: koncc 时间: 2012-1-19 08:54
感謝分享{:soso_e100:}作者: sxmemail 时间: 2012-1-19 10:30
下来用一下，先谢谢啦！！作者: 武紫旭 时间: 2012-1-24 17:46
多谢共享，这更新实在是比较快作者: sissi 时间: 2012-2-16 14:10
谢谢作者: clk 时间: 2012-3-6 09:12
9 U4 u3 ?7 h3 D1 c, I
谢谢 ！作者: zyjun1987 时间: 2012-3-6 21:21
请问这个文件是补丁还是已经打好补丁的完整安装包呢？0 j& u# x! F9 y$ U! B3 S
安装的时候直接覆盖原来的直接安装还是的重新安装啊？？ 6 C% N Q" h" K多谢多谢了！！
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