! @8 _; l% S* U& w0 w/ X! q+ [. c4 y " U% [' e7 I- j( Q8 n5 qJeff L. Sonntag % C' `5 \. b, p, l ]3 d2 b+ m
For leadership in the development of new Lucent Microelectronics businesses by advancing and applying the state-of-the-art in baseband communications architecture and analog circuit design. * O1 R: R/ h) g9 m2 A* O6 q t: G1 G/ J
Jeff Sonntag has shown remarkable depth in the areas of baseband communications, analog and digital circuit design for integrated circuits, production test methodology, and business development.# x5 Q) Z/ }5 j1 D; i& ]
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His technical leadership of the read-channel product line has spanned the past eight years, and has resulted in over $900 million in sales. It is based on signal processing, computer modelling of communication system architectures, and analog and digital circuit design. He also formed critical relationships with managers and engineers at Quantum Corp., the lead customer for this product line. 7 x) Z, q$ W( [( c& j& l' l& v" C- D8 k7 z( R& |. K
In addition to Sonntag's creation of the read channel product line, he proposed and modelled the physical layer signaling adopted for the100base VG Ethernet standard. 4 q( E0 k+ A8 `2 z5 e3 L$ P 7 W9 A; K G4 T* T$ b" XHe also contributed to the design of some early modem chips, sigma-delta modulators, T1 interface integrated circuits, timing recovery circuits for 10 Mbit local area network interfaces, and the 100base VG transceiver.6 [0 a/ Q+ p0 N, R# b3 T
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Sonntag received his bachelor's degree in electrical engineering from Carnegie Mellon University in 1982, and joined Bell Labs under the one-year-on-campus program. He received his master's in electrical engineering from Cornell University in 1983.4 m, I( s$ L" P w8 P# t2 r/ u
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昨晚跟一设计SerDes的人一起吃饭,席间他说起让他佩服得五体投地的Jeff Sonntag,当时他这么说”全世界所有的Semiconductor教授加起来都比不上他“,并介绍了迄今为止,在所有性能上都无法超越的Sontag 设计的SerDes。 $ v1 n6 _6 N- L: S 5 l* _! F7 f O3 d$ q2 j7 R7 QCDR for Gigabits.pdf(438.93 KB, 下载次数: 1256)
5 A% A. x- R' R) K( @牛!作者: stupid 时间: 2012-6-30 08:28 本帖最后由 stupid 于 2012-6-30 08:34 编辑 - y: ^* z% R- \( K4 [$ _+ U: y& T0 L: P, f* S# e) T5 s) b; f
关于此公的后续,他目前就职于Si Labs,Si Labs这两年在硅振荡器以及CDR上非常激进。+ p8 @. L0 H0 Q) {% R
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Si5040 10 Gbps XFP transceiver8 u+ I; r% y9 A0 G/ N9 l0 b) O" @
The Si5040 is a high-performance, protocol-agnostic 10 Gbps XFP transceiver featuring integrated jitter attenuating capability based on Silicon Labs' proven DSPLL technology. The Si5040 provides industry-leading jitter performance for all telecom and datacom protocols between 9.9 and 11.4 Gbps, including OC-192/STM-64, 10GE, 10G Fiber Channel and their associated forward error correction (FEC) data rates. ! c9 d- ]7 j* T5 \The device, is packaged in a 5 x 5 mm LGA package and only consumes 575 mW typ. It is designed to perform reshaping, reamplifying and retiming of the bidirectional 10 Gbps serial data by integrating two independent Clock and Data Recovery units (CDRs), two DSPLL-based Clock Multiplier Units (CMUs), and data retimers in both transmit and receive directions." ` ?1 U1 j: h0 P) r6 Y
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