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标题:
基于FPGA的单稳态脉冲展宽电路的设计问题！
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作者:
marshal403006
时间:
2008-6-1 23:30
标题:
基于FPGA的单稳态脉冲展宽电路的设计问题！
请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
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计数器（控制展宽电路的宽度）部分：
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity counter is
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port(reset,en,clk: in std_logic;
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N1,N2,N3,N4: in std_logic;
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feed_out: out std_logic);
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end counter;
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architecture Behavioral of counter is
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signal temp: integer range 0 to 15:=0;
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signal k:integer:=0;
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begin
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process(N1,N2,N3,N4,k,clk) is
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begin
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if(N1='1') then temp<=temp+1;
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elsif(N2='1') then temp<=temp+2;
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elsif(N3='1') then temp<=temp+4;
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elsif(N4='1') then temp<=temp+8;
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else null;
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end if;
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if (clk'event and clk='1') then
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if (reset='1') then
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k<=0;
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feed_out<='0';
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elsif (en='1') then
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if (k=temp-1) then
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feed_out<='1';
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k<=temp-1;
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else k<=k+1;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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D触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity D_trigger is
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port(D,clear: in std_logic;
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clk: in std_logic;
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Q: out std_logic);
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end D_trigger;
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architecture Behavioral of D_trigger is
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begin
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process(D,clear,clk) is
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begin
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if (clear='1') then
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Q<='0';
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elsif (clk'event and clk='1') then
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Q<=D;
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end if;
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end process;
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end Behavioral;
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外部综合部分：
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity pulse_expand is
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port(pulse_in,D_in: in std_logic;
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clk_in: in std_logic;
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n1,n2,n3,n4: in std_logic;
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pulsewidth_out: out std_logic);
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end pulse_expand;
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architecture Behavioral of pulse_expand is
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signal a1,a2,a3: std_logic;
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component counter is
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port(reset,en,clk: in std_logic;
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N1,N2,N3,N4: in std_logic;
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feed_out: out std_logic);
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end component counter;
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component D_trigger is
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port(D,clear: in std_logic;
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clk: in std_logic;
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Q: out std_logic);
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end component D_trigger;
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begin
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P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
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a3<= not a2;
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P2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
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N1=>n1,N2=>n2,N3=>n3,N4=>n4);
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pulsewidth_out<=a2;
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end Behavioral;
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本帖最后由 marshal403006 于 2008-6-2 09:38 编辑
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