标题: SPI程序问题 [打印本页] 作者: jiaohuang2004 时间: 2011-3-19 05:12 标题: SPI程序问题 library IEEE; ( X" O# N8 |8 E4 \+ w. B6 ruse IEEE.STD_LOGIC_1164.ALL; * ]. S2 z+ H& x/ C4 j: `( ~use IEEE.STD_LOGIC_ARITH.ALL;: ^( S" V, [4 G
use IEEE.STD_LOGIC_UNSIGNED.ALL;! H( j8 [1 M& j4 E( w8 o% _
entity spi is 8 a2 E8 m. }2 n7 g L
port 0 s2 @: i' r+ a- d- [6 U
( ' N/ G2 y5 R! W# r1 Y$ d8 t reset : in std_logic; --global reset signal( V& r/ U* D4 |% s9 t
sysclk : in std_logic; -- systerm clock 5 {2 w @! R# M4 a! p* z# a data_in : in std_logic_vector(13 downto 0); * P7 C; N% r! |/ S1 U: o spi_o : out std_logic; 7 H( h0 q( T7 d9 E sck_out : out std_logic; 0 q1 d2 N5 s/ `6 ~% |8 A+ T# p ss_n : out std_logic_vector(1 downto 0) 2 r7 |% x; n$ u; S6 D1 z ); z" Q+ ?. O. I- e- B
end spi; 3 ]- f0 E/ `3 u) r" carchitecture b of spi is * F' j, k+ {/ I6 b3 ?) h+ e type state_type is (idle,shift,stop); -- data type define : D4 E, t; U- `2 `/ E signal state : state_type;3 x- O/ a6 @8 t, K
signal out_reg : std_logic_vector(13 downto 0):=(others=>'0');' B) d$ q5 H- a) O: H+ f- h
signal clkdiv_cnt : std_logic_vector(3 downto 0) :=(others=>'0');. ]0 j: j _" f3 z. W! O
signal bit_cnt : std_logic_vector(3 downto 0) :=(others=>'0'); + E7 t% f2 ?" X# d8 M4 l8 H signal sck_o : std_logic; 2 ^$ I+ f: ^4 p9 N, p+ [; W/ s signal full : std_logic; 6 q3 {; C8 W) ?2 \, | " e1 U4 H7 |+ y* bbegin, e* d+ l0 [1 }& @, n
sck_out <= sck_o; 3 Q; M' j3 s7 K" M6 Q5 a1 ~ process(sysclk) 8 V, E2 a: q }! o D6 q begin 5 F3 ^9 x& @5 I. p8 u if (sysclk'event and sysclk = '1') then --reset , h/ u" P( B' B+ m" L5 y if (reset = '1') then+ d# z: t( Y$ D$ h n, d% l
ss_n <= (others=>'1'); --AD5553 idle CS =1! x/ t) y- D4 x/ p; K3 G7 f
out_reg <= (others=>'0'); & e# V8 C+ Q: w' U& Z) f clkdiv_cnt <= (others=>'0'); ; N/ p2 X1 H+ M9 m bit_cnt <= (others=>'0'); 9 F, S H( v: E& @# ? spi_o <= '1'; $ i0 i/ {& C" Z8 T. B: B sck_o <= '0'; -- AD5553 SCK idle is 0$ @ g9 M- b8 z- [& B; ]
state <= idle;! b y6 p" g6 l9 N
full <= '0'; & B. W8 N: s j( U1 W2 V& A. b else 8 F& A) m2 M( [ if(full = '0') then / W! ]0 N4 w5 A) u7 O, p" r7 T out_reg <= data_in ;5 }0 f% Q& v. n
full <= '1'; ( `2 j" i! E: |/ B end if; ' X1 @1 o5 t# z* I8 x9 K+ E9 H ) Q$ z n" R) @$ O5 n
case state is ( L' ^7 W* _/ T" x/ a/ o* t7 J+ t
when idle => # W" X- L! k9 F' Y9 h 2 V( S" R0 a; X; D" Z1 J" d" e state <= shift;" i. T. w& g$ r$ x- e! Q
spi_o <= out_reg(13);; x7 l- z# u- K! E' J
out_reg <= out_reg(12 downto 0) & '0'; ! K) K' q5 Q- I$ V Q9 ?9 T sck_o <= '0'; ' a1 b; I' F, t6 f% x: `3 u; B
when shift =>" x' ~, d1 V* U. }, }
clkdiv_cnt <= clkdiv_cnt + '1'; ' U, J( g. }! X1 d if (clkdiv_cnt(2 downto 0)="111") then 1 \# Z9 U4 A- K sck_o <= not sck_o;0 V( b1 z4 z$ C0 x: K
end if; / K( V" d# ~4 ~: z+ D# B( \ 2 ~; R3 m; P9 ~ if (clkdiv_cnt = "1111") then 3 n; Z$ ]3 T( h$ p5 l1 @& R6 { spi_o <= out_reg(13);, w y1 Z7 p7 d' V. z
out_reg <= out_reg(12 downto 0) & '0';, o; m+ M; p" _
bit_cnt <= bit_cnt + '1'; 2 m& Y6 ?! _2 P1 o' U end if;; p- U. \: B" W3 j
" i1 u# a- k7 Z- l1 s' K- F7 f# s if (bit_cnt="1110" and clkdiv_cnt = "1111") then# N* H6 x/ I, a( Z1 n9 }
state <= stop;; A$ b1 i0 N l; {6 ?3 D: `0 U
sck_o <= '0'; # u8 ?+ a9 W" [5 ~" f spi_o <= '1'; ! u- C3 a0 M; o7 Q. e' g end if;1 u) a3 \! b' w, w4 t
. F. X6 w6 b, W* B when stop => # g1 m* U8 K* m- g state <= idle; 9 J5 ?: i4 n# h$ P: t9 O% _ sck_o <= '0';/ w6 T& r9 N: f) l
spi_o <= '1'; / p y! N ~! }+ z9 i8 g9 M6 k clkdiv_cnt <= (others=>'0');- {* O" `; e z3 F! r3 |
bit_cnt <= (others=>'0'); 2 a% ^% ]7 R( g2 U2 h1 J! m0 q full <= '0';( r3 k/ x& U, ?+ ^5 @" a, s
when others =>0 P* a- i7 x3 u- a; Q4 w
state <= idle; * D3 Z8 j8 b2 M% F, S0 G& Z end case;4 A1 T& s' k7 O2 C/ @0 Q5 P+ C
end if;6 M+ y' E' D+ ^! c* b
end if; W3 B7 q* U% } @( I5 {
end process; 9 D# K& O { C& t. y0 f% I3 Cend b; - f3 Q/ c" k: H `8 R, c0 g2 _& H% y- d* a# \) Q2 e
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其中out_reg 一直是0，在idle状态赋不上值，大家看是怎么回事 - E2 T! U; Q. _1 Q- _' @