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标题:
Cadence 15.7导网表突然出错了~~
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作者:
clf1985
时间:
2010-5-12 21:35
标题:
Cadence 15.7导网表突然出错了~~
本来一直好好的，元器件都布局好了。然后去ORCAD里更改了一下原理图里几个电容的封装，再更新到PCB就出错了。有人有解决办法吗？不然白忙活了。
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Allegro里的出错报告如下：
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Cadence Design Systems, Inc. netrev 15.7 Wed May 12 21:32:04 2010
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(C) Copyright 2002 Cadence Design Systems, Inc.
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------ Directives ------
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RIPUP_ETCH TRUE;
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RIPUP_SYMBOLS ALWAYS;
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MISSING SYMBOL AS ERROR FALSE;
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SCHEMATIC_DIRECTORY 'D:/CadenceWork/HongelDM642/PCB/allegro';
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BOARD_DIRECTORY '';
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OLD_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';
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NEW_BOARD_NAME 'D:/CadenceWork/HongelDM642/PCB/DM642_Core_Board.brd';
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CmdLine: netrev -$ -5 -i D:/CadenceWork/HongelDM642/PCB/allegro -x -y 1 -z D:/CadenceWork/HongelDM642/PCB/#Taaaaaa00436.tmp
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------ Preparing to read pst files ------
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Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat
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Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstchip.dat (00:00:00.04)
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Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat
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Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxprt.dat (00:00:00.01)
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Starting to read D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat
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Finished reading D:/CadenceWork/HongelDM642/PCB/allegro/pstxnet.dat (00:00:00.03)
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------ Oversights/Warnings/Errors ------
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#1 ERROR(102) Run stopped because errors were detected
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netrev run on May 12 21:32:04 2010
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DESIGN NAME : 'DM642_PRJ'
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PACKAGING ON May 28 2006 22:05:31
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COMPILE 'logic'
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CHECK_PIN_NAMES OFF
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CROSS_REFERENCE OFF
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FEEDBACK OFF
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INCREMENTAL OFF
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INTERFACE_TYPE PHYSICAL
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MAX_ERRORS 500
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MERGE_MINIMUM 5
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NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
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NET_NAME_LENGTH 24
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OVERSIGHTS ON
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REPLACE_CHECK OFF
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SINGLE_NODE_NETS ON
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SPLIT_MINIMUM 0
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SUPPRESS 20
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WARNINGS ON
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1 errors detected
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No oversight detected
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No warning detected
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cpu time 0:02:36
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elapsed time 0:00:01
作者:
clf1985
时间:
2010-5-12 21:52
哪位兄弟有用15.5版本的麻烦将 netin.exe和netrev.exe 这两个文件传一下给我吧。貌似是这个的BUG。谢谢
作者:
wzwang2000
时间:
2012-6-18 15:13
奇怪啊，allegro居然没告诉是什么错误，就说检查到了一个错误。
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