标题: PADS9.1即将催出 [打印本页] 作者: disth 时间: 2009-12-20 00:29 标题: PADS9.1即将催出 9.02有很大BUG，所以MENTOR又匆匆修改了几个补丁，然后集合催出9.1，现在9.1已经进入最后测试： * g' |) |8 c7 K7 A( T+ FPADS 9.1 Customer Beta 6 已经出来： ; r4 E( D5 f3 o3 ], f ~# N3 D/ wPADS 9.1 Customer Beta 6 ( i. p& v3 e$ E; X( s
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December 2009, Install 12587+ _. E, X1 {) y) V" W5 U+ M W7 U
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Please submit defects for products as instructed below. # s: P9 h! c/ c8 x& U$ @, t6 L----------------------------------------------------------------------------------------- # [( u6 R$ m2 l! \& A8 lDefects for PADS Layout, Logic, Router and DxDesigner should be submitted to the Beta products on SupportNet, 9 Z, C/ m% K& Y; H
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which are BETA_PADS_Layout, BETA_PADS_Router, BETA_PADS_LOGIC and Beta_PADS_DxDesigner. 1 y4 z( e3 C& a2 u n ) k: Q' w: @# u8 @: b . C* v3 l. @- N6 V+ N' w2 @***IMPORTANT*** - Known Issues and Future Changes * z/ S# e$ W+ d& V7 U6 N1 d' K-------------------------------------------------$ D4 t5 I$ M" }) Q$ S- K
1. DxDesigner and related programs from EE2007.8 are now included in this release.3 ]$ U8 A" o7 i3 n4 A
2. Archiver functionality is now available in the Tools menu of Layout, Logic and Router as well as DxDesigner. p" R8 J: f- R& u
3. During installation there is an error with the post install script "accuparts_dx_postinstall.bat".4 H7 ?& a$ U8 g# l. R' ?- F
$ l& M) T* \( {4 W& N$ RSee the reference notes below for a list of functional updates and current fixes. 2 L2 e, y( G2 v 8 Q& Z+ L! x9 B6 E' ^% ARegards, 5 V, Y) u1 u! U8 L* P6 b9 K# W" R4 R" U5 }6 X0 E6 s9 [
The PADS Beta Team/ _& ~6 a' s* y6 G6 H
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! H; T$ W9 J) s$ _; b) y) ?Setup, Licensing, Installation, and Distribution 4 }* o7 a1 G; [3 W/ u8 y------------------------------------------------2 M/ X8 _- R6 L5 r8 X4 K# [4 j( _
- Windows XP and Windows Vista Japanese are supported. : J3 S" _9 o7 z9 F
- Database formats for Layout, Logic and Router designs have changed. / P" f! F0 F$ T2 P# E, v) ^% K- You are required to have a licenses file with an exact access date of November 1, 2009 or later to run this release. To determine the Exact Access Date (EAD) of your license file go to mentor support net。 ! R# y0 {" k5 G" \$ j! v) ?5 [PADS9.1 is a completely separate installation from previous PADS releases, The Installation ; f9 A; I4 Y( f6 E( A& R
path for PADS9.1 is now C:\MentorGraphics\9.1PADS. While PADS9.1 does not overwrite 8 q1 i# G4 r4 ^5 w! A1 [5 F5 k: ?previous PADS installations, you should back up your existing PADS installation, designs and 7 d8 M7 J6 `& N6 Ulibraries prior to installing PADS9.1. ( G5 X( W. F8 ?) H, V+ L* U
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Fixes/enhancements for HyperLynx Thermal 5 M A; G: f2 C! P3 H) _- ?---------------------------------------- 9 V5 H1 K6 v0 r/ hnone * Z9 t( e( b2 k/ j, F* s( r2 e/ f: y: W, j. ? g
Fixes/enhancements for HyperLynx Analog) L' C2 ]6 g5 F& I- h H
--------------------------------------- * ]# N0 ]/ L$ }4 ~% m6 c6 vdts0100634577 Apex Engine doesn't complete simulation for Digital Models , j- U/ L7 E- [) n% [4 }3 i) g7 Odts0100636111 Infohub Help & Manual Scope incorrectly says "Analysis - Simulation and Signal Integrity with HyperLynx Analog0 t6 L% K3 Z0 `0 R! Y- X3 z. B
dts0100634078 Eldo MC78xx models are incorrect and do not simulate correctly/ c( ]& m% Q. F% g [% c: [, n
dts0100636035 The SPICE model libraries do not load when useing Eldo with PADS ' C& U$ ?3 G0 A$ e' l, f( L# i- ndts0100608146 Exclude Component not shown in Japanese menu/ p6 t0 w" ]" x! A& z5 F# C
dts0100608582 [Simulation Control dialog] :"DC Sweep Parameters" page --> "Add' doesn't behave correctly.) u0 b9 h/ p- ~; T# T b
dts0100616119 .option tuning will override user value for eps * m. w5 A6 x. a9 rdts0100631676 Incorrect netlist from distribution dialog9 n% i- w* y, w* O9 _0 Y+ R
dts0100608021 Exclusion should work hierarchically ' o2 i8 |% H& W+ g/ w" i: Ldts0100614981 Eldo behaves different than the other netlist formats9 e. M5 {0 W4 c' t, Y/ J
dts0100615983 The VHDL Netlister should handle the (Read-in output) by creating an intermediate signal 7 p: r& B, j* P7 Cdts0100615994 Wrong netlist when symbol pin number is greater than model port number 2 b$ S* b; k D1 H& }) ~6 rdts0100618238 VHDL netlister does not handle ports properly) U. o0 _, D, ~( W7 j4 O( J0 g
dts0100620878 Wrong VHDL code with component array * t; o) [! _: N! b# z: x) m3 kdts0100622857 [Netlister] Netlist error in ports connection with buses . ?/ i: S1 [7 Z- k0 Gdts0100630659 [Netlister] VHDL netlist generated for the attached project is incorrect4 E- P4 j7 f/ Q" U
dts0100632875 [Netlister] Output port is not mapped correctly to the bus connected to it6 y3 x1 P P+ b
dts0100632876 [Netlister] When Port name is same as bus name, the buffer name will be incorrect ~: c* A* R! h- r1 gdts0100633267 When switching simulator between ELDO and HLA, dxnetlister.ini lost [SpiceHeader] information7 W$ u8 k, b. I* d- X0 n2 [$ c6 o$ n" S$ b
+ E# b1 R# z8 ^& c ) [; F' `2 Q; F7 [5 a Y" |2 S% c# {Fixes/enhancements for HyperLynx . R! e& S: Z( ~( v; K* E
-------------------------------- 3 n9 m( U2 Y" B2 j% `/ k9 c4 cdts0100629862 HyperLynx BoardSIM export from PADS Layout places plane areas within signal net definition 2 G9 G. n# o# @0 g( }4 t" y( w8 Q# |6 L5 ^! m
. Z! U) O- @/ `) H- u$ e. [) UFixes/Enhancements for PADS 3D Viewing (Note: 3D Viewer 2.0 is included in PADS 9.1)+ r9 D3 N# q" c; z# @4 G \
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dts0100605690 Layer 20 (footprint courtyard) is used when generating the 3D view. This causes problems with the new 3D viewer ' \ C, e5 g; ]# I+ t6 ydts0100635846 Component heights are incorrect # k, h6 o: ?# R$ {# X. i5 j: a- {3 @0 n b& J
! V; o9 c$ ?( `8 j3 D. bFixes/enhancements for PADS Layout $ i2 ]. b: J6 j0 ^; Q3 F7 c----------------------------------# Z9 _5 S& z! W+ N: _# W
dts0100592339 Netlist from DxD is wrongly loaded into Layout if Unit attribute in DxD is set to Metric. & H) c1 Z/ ]3 i' a4 z' M8 Udts0100621636 PADSLayout hangs when you want to substitutes part with Decal that has 'increaded Layer mode' 7 P5 A9 b$ R* z0 h } r; x- m4 j# }dts0100601402 Time stamp for Part Type on pcb design is not updated when you modify attributes. . \* d5 S. w/ n4 x Jdts0100631451 Change label in HYP Export dialog box @) \& F, w0 j# k7 I1 j+ r2 O- N# p e# J
dts0100544158 Poor outline information sent to 3D Viewer - Beta 3 9 H# G6 v9 _6 T, {, Bdts0100547218 Gerber preview shows short in the design. But there is no errors if we run clearance check.1 H3 e, L) h" p0 D
dts0100593049 PADSPCB_Decal Wizard - RMB opens main window popup if cursor is over a data line or title line (Defect for 9.1) : Y) j% b% @- hdts0100593100 PADSPCB_Decal Wizard - Default layers for outlines in the decal wizard options should be Silkscreen Top, Assembly Top and Layer_20 * h! l+ o. n4 [dts0100593106 PADSPCB_Decal Wizard - Selection pop-up on cells is appearing in the grid controls of decal wizard and decal wizard options dialogs.; \- Y. _, E6 u$ O, c$ v
dts0100593107 PADSPCB_Decal Wizard - Decal Wizard: Create crosshair as two "L"'s (instead of two crossing segments). 6 _$ i) i0 S0 Q# b" l' Rdts0100593110 PADSPCB_Decal Wizard - Decal Wizard dialog: Default button should put some values for component dimensions in the "Land Pattern Calculator" group. 4 ?3 @. I, H5 D6 F) A' cdts0100622131 Pads definition on solder mask is incorect for through hole device type generated by IPC decal wizard( C" q, z3 `1 ?, a2 m" I
dts0100622230 Incorect dimention name in the grid & l1 d- P* v2 Fdts0100622475 Placement outline is shifted for generated decal ! a( |/ y) Q# ]dts0100622697 Preview window displays colors incorectly h! E" n( k* z; _, @
dts0100623701 Notch for assembly outline should have separate control checkbox+ `$ u0 v" ?# t# S) B" Q2 l
dts0100623736 Rounded corner radius is incorect for pads on solder and paste layers if mask expansion is used p( J, ~% r: N0 ~
dts0100623783 Generated decal is collapsed for those specific parameters # z) Q# n7 ]- R+ c' U* C% {& Gdts0100623797 Tab order works incorectly for wizard dialog : u, R5 ?) r1 P; m/ [/ N# Odts0100624535 False pad to pad clearance error is indicated 4 S+ l4 T y) c9 x0 {dts0100628883 Distance between pads and silkscreen is incorrect for quad decal& B0 Z: {) x; v2 [
dts0100629011 Some pads are not rotated for Polar decal/ ^8 o/ c) @ i
dts0100629304 Preview window blinks after pressing default button in BGA tab 7 H2 V3 J& \; ddts0100632350 Units groups in the decal wizard and wizard options dialogs are NOT in synch with unit setting in the Tools->Options dialog s6 w, S- P! g# j+ Edts0100633384 When a configuration file is missing used gets a misinforming message' u b H$ i, l8 ^6 |
dts0100629345 Polar tab does not respect the silkscreen line width parameter 4 Q+ c& s8 q1 H0 mdts0100582679 When the "Remove unused pads" feature is used, pads within "copper pour and plane area" keepouts are not removed., Z+ q" N( h, `9 e$ @1 v6 V% S" B7 _
dts0100620173 Runtime error while doing Forward to PCB. / x2 v6 _) v& N' G. Idts0100634090 Runtime error viewdrawlink on update PCB # [8 G; S5 b) P6 r/ P Mdts0100472613 Not possible to change parttype with PCB-Decals with different number of terminals E4 _. Y' s/ W2 Kdts0100480393 Pour Manager does not consider board - Copper Clearance Rules 8 C, f2 O* f) \. Z( Idts0100570786 Bad flood data creates short across 4 nets which Verify Design did not catch ' ]/ h& ~, _4 J/ ^dts0100605615 Boldface not used correctly on "PADS Layout GUI Reference > Options Dialog Box, Grids Tab" help page , r1 l2 x' } S9 U% v: E1 hdts0100633511 Change the help menu item to point to a different book4 \& I/ x1 Z# N+ G
dts0100632059 Altium Designer 2006 file will translate in V2005 translator but crashes at 75% in V9.0.2 translator 5 W! F7 e6 Q& l6 g8 p1 jdts0100593860 DXF and IPC export generate Fatal error occurred while exporting design - operation aborted5 K! ^4 W) n, k
dts0100473144 Length minimize during move will not work when connection is established to partial route or via. - I1 P4 ?* d8 u6 U- Hdts0100629626 MACRO - When I run the attached macros, the result dialog box doesn't appear. In previous versions a window would popup listing the number of errors found. . d, F$ c! u3 Y: `dts0100627987 When modeless commond "zc" is used, PADSLayout is freezing.* v" u& ]3 l6 @7 P4 _3 V+ `
dts0100633930 Too crashes when we export ODB++ for preview.pcb ; C4 R: @* z& ]/ ?" }dts0100636557 ODB++ Output error (Fatal error: layer -1 not exported!)* R X7 e! K7 {
dts0100527420 Tool allows to create 'Thermals' for SMD Test Points, which leads to series of issues. ! M3 N$ Y" U8 z$ W! u3 u/ U tdts0100630528 Create PDF - Graphical error in copper (Beta 3) ) B5 J7 W8 i! f; e( T9 tdts0100631593 Create PDF - Some Ref Des are rotated (Beta 3)4 z5 g) D3 P: J( J
dts0100631669 In PDF User defined Untipads are not added on CAM Plane layer ! I/ Y$ `! W6 ^8 H( ldts0100631920 Create PDF - Remove Bookmarks for components not included in PDF file (Beta 3) 7 d# \2 i6 l9 @8 I ]& ~ @2 q7 G0 Adts0100635884 Creat PDF process request hundred times for component that does not exist in library% a' z( k* C% J
dts0100496801 Reuse Copy loses Flood Priority, resets all to 0- K0 y2 T$ E+ |& ~6 t3 A
dts0100419975 Remove unused pad does not work for nested planes where the outer plane net was used in the inner planes * X% j( E1 ~' T% }8 ndts0100636198 Crash when removing via from routing via list" f" h3 w$ }- {! f
dts0100637331 Pads disappear when zooming in/out q4 W0 q4 B/ S# O' U
dts0100635066 "Fatal Data Base Error Number 2012" and crash during opening a design in non licensed mode " r6 W& X- p- P, m0 x& j5 z6 Xdts0100600676 Picture and information about UFL dialog window should be updated in FSP (or implementation should be changed) ' h; C& n7 i) Odts0100621629 Strange message appears when you perform UFL in Layout. & R6 H1 U5 X/ |dts0100634588 Update From Library creates Undo Checkpoint even if no changes are made in the PCB Database 2 U7 `9 g' z0 Y" m7 K! ?" E( E$ F7 ndts0100634589 UFL dialog: Remove Selected Items button should be ghosted when no design items are selected.3 i; C6 F6 L1 y0 t. Z" X
dts0100634608 When you import an ASCII file netlist into a new pcb database the decal and part timestamps are not included.2 b; w' t5 i6 q/ E
dts0100634609 "B. The part type section contains 6 parts that show ?Different? in the? Content column ?but only one of the six has a value in column ?see line?. Should have a line number on all 6of the items that sh..."- C/ E$ }7 j1 i) v/ ^$ i
dts0100634613 The "see line" of Part LITTLEFUSE-V18AUML2220(located at line 89) shows 195 in the "see line" column but it actually starts on line 193.% _8 M5 V1 p, ?9 ?
dts0100634615 Timestamp values are not shown in the Part Type Summary. e# F) i K3 ~dts0100634616 Line 136 should not truncate names. Wrap the text to the next line or show the entire value. 3 L8 H$ G0 s2 F8 T1 Pdts0100634620 "C. Line 644 states the Attributes in the library are 16 and the attributes in the pcb are 18. The actual decal has 18 attributes looking at the actual decal in the library file lenny.d" ; C% S# b F( p% o( T& fdts0100634622 "F. Looking at line 682 685 686 the counts are equal yet the comparison field shows not equal. Each of these should have additional lines underneath them showing the actual item that does not compare. ..."; _% g& A: A2 V$ O* p7 E
dts0100634637 "Looking at REPORT-LIB-UPD-ALL.TXT contains the following errors. (Generated from PCB File LIB-UPD.PCB). e. Line 11221, 11336 states they are not equal yet the 4 lines below that are equal."; V5 y/ j- I5 u7 h) j& a9 @1 W
dts0100634646 Even if you update all the parts using the library update to update them there are still errors when comparing the library to the pcb. Please see REPORT-PARTS-UPD.TXT5 L, J) F5 N" ^3 a
dts0100637697 Parttype timestamp in PADS Layout is not correct if "Send Netlist" is used - (Beta 5) Could be related to dts0100634641.0 |: P4 ^* S9 j4 O8 t, X
6 j6 S# q; K0 l5 v. a / S, J& y6 l% W s, z" z& qFixes/Enhancements for Logic 6 W" A" n) h/ e4 h6 @" `
---------------------------- ; G0 ^) V( s1 e. m4 U( V$ zdts0100623556 Component attributes with a value can not be emptied in Edit Part. ; r9 ^+ |2 D# T5 S3 Ldts0100629839 Global switch in options to turn on/off place holder attributes in Logic. M8 b5 \2 e: t. s3 x4 Bdts0100591808 Update Logic Sample Files ( f* O' \1 P) t3 ~0 R2 Ldts0100428973 ECO/Compare reports No Differences Found when one of the files is read only-should indicate it needs write permission4 o2 x4 Z; W5 o; M8 {
dts0100592901 0906021756_PADS_LogicCrashReport - i$ \" b U' Z3 {dts0100533663 Deleting vias in Via Definition > Via Setup does not work ) g* m" r5 d" m; @dts0100630556 Autotest detected: "PIN Decals" instead of "Pin Decals" in Update from Library dialog box( T' ~1 @, S: {; T' y: Z
dts0100623987 Fatal run-time error * D6 o! v, g. v) P) N8 z7 t- ydts0100579379 Automation method ExportNetList wasn't modified when the number of items to select had increased + N# t8 R: c/ Sdts0100619394 Regression: If you edit a part from the schematic and add an attribute the attribute is not included after returning to the schematic; ~/ S9 Z4 b/ C. Y; B
dts0100614860 Getting error message 'Fatal Runtime Error' when I try to generate File > Report > Unused G. U7 |5 o. O% K7 ?; E7 c0 L9 Xdts0100349358 Adding Classes with spaces crashes Logic4 \8 S( s" L/ W7 ^3 B& k' K
dts0100574637 More than one net is unknowingly selected in the rules after performing a specific set of steps. % ]7 {9 E; a/ b5 z O$ cdts0100537702 There should be a Select list for each Item. Right now, only the Pin Decal has an individually selectable list. 8 ?" e& v o2 t f+ h/ Rdts0100537705 "Update from Library" should be on context menu when selecting a part or parts.* o( Q( y9 s5 R7 \9 p
dts0100552427 UpdateFromLibrary cannot handle same part types with different attribute values (in report)% u. x4 H: c/ b! F3 d7 W+ c9 R
dts0100571175 UpdateReport detects hierarchical sheets as CAE-Decals - Beta 9 6 s# H. |/ J4 i- `3 X8 M7 w$ |- g) adts0100579630 Alternate PCB-Decals still produces false differences in UpdateReport - Beta 119 t/ x A$ X) p% y! G9 T+ M
dts0100593092 PADSLogic_Update from Library - ENH: indicate library name in the report (for library decals, parts) ( M' S7 N, ?9 ^/ _" k r4 fdts0100618873 Header in PADSLogic UFL report should be updated. 8 a9 H9 b2 B7 O! P+ p # B! o; ]% v. |+ n" m3 [ b- C; M4 S0 U7 Z/ x
Fixes/Enhancements for Router 8 k, H4 I7 q/ Y, Q& F
----------------------------- & F# U2 Z8 k$ Q; k4 bdts0100628438 Saving file in pads router causes fatal error. + g9 v3 E9 v* ]. K4 ~9 ^# ^( gdts0100450331 Why can't Blazeroute.ini be populated with the new options in their default conditions, so users don't need to type everything in? " Q: y1 U; B0 u# {9 u: ~* Ydts0100531461 Incorrect parameters in Router ) Q0 m2 {' j' l7 ~+ \: a8 e. g- Zdts0100583129 Crash dump9 _0 P. Z1 b* M" o9 | @; a$ ?
dts0100635895 Design verification scheme list not work correctly. / V3 k% q9 J2 S* jdts0100493262 Default Windows dialog is displayed for some controls 1 O+ n; d2 D8 a4 I7 @; cdts0100634385 Library Not Registered errors when PADS is installed to a directory with spaces- r8 a3 C* q* u6 M. Y
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Fixes/Enhancements for Install 1 J! V2 q& I3 L$ V. A I, q/ g) s3 E------------------------------ , F; c, X. S: `2 [+ k; Mdts0100498605 Need improved handling of the "lost license" scenario in PADS - s+ p5 v$ ~3 p0 _- c. ydts0100569313 PADS "Hardware Key Utility" program to make testing keys and installing/removing drivers much easier for customers: o# p! Z, F6 T. ~! f
dts0100621527 While installing the program got error message "C:\MentorGraphics\9.1PADS\SDD_HOME\common\win32\lib\MGCLibDataGrid.ocx" failed to load for Registration. / U/ \) _2 n) s 5 h4 {6 G7 S2 W8 q, J1 ~( Y + V4 V0 a4 V+ n; wFixes/Enhancements for IO Designer9 t: d; u6 _+ B, t* g! P9 P
---------------------------------- ! w+ @% C ^& G k- D4 ?dts0100635950 Layout form Allegor is display incorectly. ( {+ g4 A [- P7 @3 `2 ddts0100635963 Missing brd and hyp filter of types in select path to layout.0 u, q3 i+ x5 U/ T h
dts0100637587 IOD display only current fpga on device view (Layout import form Allegro). 6 d0 c1 Z: L$ Q# m. _5 _6 L* O3 s; tdts0100638335 Cadence IOD8.2: Got 'Unknown flow!' error message when trying to import schematic design. $ B7 l9 B; J! X( c, m Sdts0100602206 IOD not outputting good Actel PDC file ) a+ o" H0 M3 O" A q$ Fdts0100633957 Wrong recognize diff signal form QSF file 4 I0 @; @8 q3 _dts0100625917 After import QSF some differential signal are doubled # H5 t2 t- d; _dts0100625992 It's impossible to import properly diff signals from pin file if it's use '(n)' convenction of naming diff pairs. ' I* D' p% N6 q% o5 Kdts0100616628 'configurator -uninstall' didn't remove IOD entry from menu start. a- B5 X3 I7 X0 k$ K" K: c9 o! o
dts0100621897 Poor support for IOD installed as single product. 9 ] D' \- D" z. d% g# T/ S {dts0100630357 EE 8.2: Installting IOD 8.2 alone would not register the product on Windows. - R. K9 P: A2 d* j3 kdts0100616905 IOD does not dump tcl command while import signals from spreadsheet is performed.! _2 Z. I! ~- u5 a; R6 Q& W
dts0100636590 Iod deleted all project files. ' s& g% _2 \1 w- t. [/ Fdts0100629434 IOD is not responding for over 13 minutes after selecting GND signal. / m* n. G! Z, {' u9 Z' Y, X; k- o" B/ Mdts0100633035 Cross probing : highlighted wrong signal in IOD while selecting net in DxD 8 W7 }* m& Q# K9 g- fdts0100625292 Pin swaps are not imported 1 h7 X! e5 b6 Z I G Ndts0100616652 IOD hangs after minimize die size is run in specific case. " @3 X/ O* Z5 L1 G9 ndts0100615802 Documentation for IOD8.1 should be improve.: O# \+ O% @( A0 U ~ |4 G
dts0100632600 Documentation incorrect in regard to Symbol Wizard. # P8 Y% R: S/ _! tdts0100614543 Write to Local PDB file is not remembered $ i6 F3 N- r) Vdts0100617368 PADS9.0.2 The builtin 'sym\bi.1' cannot be exported. The path doesnot exist. " A$ s8 ]4 E) W* Idts0100619265 PKG_TYPE and SIGNAL attributes are not exported to ICE in pads flow 1 g7 e6 b+ q* n adts0100619614 Differential buses are not connected on the IOD generated schematic.) g* N) z/ ~" L: m3 ~6 R; q- H
dts0100630977 Remove design doesn't work.2 R; Q5 h4 q7 Y) X8 m
dts0100632139 EE IOD8.2: IOD showed a fatal error when running run.tcl. 4 w: e1 W' l7 ]# p' udts0100636406 EE IOD8.2: IOD crashed after export_all_schematics command was issued. : J, n" j* Q" k( K% H! Mdts0100625329 Importing assignment for diff signals from dxd project does not work$ C( B0 n( @ x) P4 ^* d0 f
dts0100632195 Schematic Update is removing and not adding any power, ground and/or config pins defined as signals and/or added to the PCB symbols in the DxD schematic. 7 N5 E( O! k( c/ k' Z/ t: rdts0100615847 NSE seemed to crash on the 'exit' TCL command on Linux only. 6 _$ L) i3 N: i' u5 r1 k. \dts0100617458 De-scoped I/O Designer for PADS Suite 5 D* v, w, |' D5 V- b6 \. wdts0100620002 ANALOGVCC is migrated incorrectly : C( t$ b4 p% Y9 f# ldts0100620440 Inconsistent behaviour in creating differential signal name7 r' D9 x9 }5 ]% O3 X( h
dts0100624825 Spread functionality of Types Compatibility options for HDL signals # Q6 l' u% e5 h9 C+ `dts0100624857 "Project could not be saved" because design name has space character. ! n9 V* t+ H4 f) d6 S7 ~dts0100626736 Environment variable in .prj file not supported0 ^( c: X5 ^. ~( J m2 O& k# @
dts0100632352 Llicense dialog - empty license options in 'PADS I/O Designer'- p, u3 m5 k% U3 ^* K% {% x
dts0100633373 SSO value is calculated wrong for differential signals. $ c' Y" w# v6 Rdts0100635946 Migration of old database should be improved. & s" Y( ?2 b- @dts0100620449 Duplicated signals after importing from HDL and QSF 7 G. a4 U% t- G& Adts0100636022 Crash of IOD while importing vhdl entity. ; k! r/ _6 L6 U) d0 Y' \dts0100616013 Wrong HDL created/exported* }/ a4 |1 V, I- I
dts0100617953 Space character in design name makes problem for IOD. Error: Top level must be set.( [/ U! ]" d& c/ \/ I
dts0100633055 Import PCB Design Wizard: Whole signal is unassigned when one pin type is not compatible with signal type 7 d! P0 n# q, Rdts0100597469 [BSXE] Importing swap in lpc database results in broken connectivity if component database is not synchronized before* O2 _3 c7 F! {. F6 @. }+ N
dts0100616740 Background on Layout view is always black on Vista 64 1 e" \% C3 D6 g) sdts0100621328 Unravel on my design with diff signals causes error messages during applying scenario' A3 ^% {& s) m3 [0 c
dts0100630751 Library parser failure while importing schematic into layout database.* Q) C5 G. ^4 {- S
dts0100633294 Partition name is not displayed on Layout Setup window 0 w8 Y! A- f' ]0 n0 h/ z4 T1 z$ {dts0100633924 Signal names disappear on connectivity window after importing pcb layout5 z+ j5 A5 a3 @
dts0100615858 IOD8.1: IOD crashed on the TCL file. ) h$ d- T G6 H, wdts0100616812 IOD8.1: TCL command, exportsymbol, resulted in an error.5 u4 ^# M- o* }( ~
dts0100618901 Improving TCL script recorder - C2 ?* ~3 ~# ^5 M, [( F: ddts0100623194 IOD8.1: TCL command selectsignals A<15:9> caused IOD to crash.1 g* {% [$ X4 K$ [6 {
dts0100631902 License dialog is empty on linux after running IOD (refresh problem)6 H4 r% V3 \) M* l$ f
dts0100632077 EE IOD8.2: Available license options were not shown for the full version IOD. & r9 A: s7 K5 H: K; y5 ?9 j: Ldts0100632627 Some option related to die database are redundantly displayed in Tools menu for other databases.; t* i" G6 [( H. T" m% H7 ?# N
dts0100633752 EE IOD8.2: IOD crashed on running the TCL file on Linux" S' U! R5 P, d5 Y
dts0100634470 EE IOD8.2: IOD crashed when I tried to use TCL commands to select signals after running a Dx VBS script. ( P+ ^, {# B2 t: n. m5 m* _dts0100635370 EE IOD8.2: IOD crashed with C++ Runtime Library error when adding a new FPGA design.0 E$ d5 I6 ]/ d4 R
dts0100638815 IOD crashes while openning customer's database on Linux. ; e$ d( E' k2 v1 hdts0100597062 Export to AIF from package db is not required after applying swap on layout db 3 V' A' P; C0 m( r0 x6 \dts0100607448 Import package cell preserving assignments where possible ( j$ E( f2 c! Z. V! A, S. bdts0100628060 Error message after reimporting cell into package database with diff signals& Y1 U2 p# {6 N( R2 Y$ A @9 a* `
dts0100629676 Unassign all => cannot unassign signal 'diff_test' - signal diff_test doesn't exist . I5 f, c V3 h6 u+ `9 p4 G! gdts0100605036 Types Compatybility does not support an assignment exception# d# e4 P' N( }# b/ @5 S$ b
dts0100619916 There is no possibility to assign differential signal to pins 8 and 9 in Altera's device.$ ]1 u1 T" i* X! j4 u
dts0100624059 IOD is not responding while assigning pcb signal with Shift pressed. # P6 j/ ~: e$ O- ?dts0100632373 Error while import Netlist file (Spreadsheet): .csv, when signal type charakter are small) d$ L( `; `( a; K
dts0100632383 No assing differential signal (but no DIFF type) after Import Netlist Spreadsheet file: .csv `, T- O G2 c/ q* p! Xdts0100632619 Cannot assign output IO signal( I1 b: a, L2 q2 Z
dts0100623389 'View pins from other devices' doesn't show common pins. Pins list is empty. " o7 ^0 x* e. B5 D2 s- [$ gdts0100635506 IOD is repositioning windows constantly depending on cursor position what looks like IOD is blinking. : B1 S9 W% W4 ?8 L! T7 h. ldts0100621902 Database Settings not prompted when loading FPC. 0 D# D# d) Z, |" b, n7 R) n0 i) Mdts0100631933 Creating net-list project ends with error) J" C9 D2 E( w# I% W
dts0100633129 EE IOD8.2: Got an error on Linux: vmwlm: [11:14:40] error VMWLM0301: License server not found. : ~1 ~) k4 S6 A6 E& f. ]: }dts0100633480 EE IOD8.2: IOD failed to create a new project on Solaris.5 F& R1 T ]9 f7 f( ]) Q
dts0100626020 Rule engine operators have incorrect English+ d. l6 U) L1 A' i
dts0100635228 Input pad with INPUT TERMINATION has to be at least 1 LAB away from differential pad./ C$ x! \6 H: r) Y Q
dts0100635867 Rule: Single-ended output and differential signals assignment" work unproperly. 5 P7 P9 L7 D. g8 e) @2 `dts0100619597 Unplaced tab improperly shows connectivity problems in some case. 0 L! q3 i- U2 L( y& d) y8 z {' qdts0100619601 Symbol Wizard does not place all signals on PCB symbols in specific case.( W6 Q% R' G) D+ n! _* i
dts0100619941 Wrong information of selected differential signals.0 A3 r8 r% X! C
dts0100620427 Corrupted database structure ' C- _6 Z4 l0 o/ Ndts0100619606 After splitting bus signals symbols become broken. 8 j# i: C8 T* S' Fdts0100619852 It is not possible to exit from mode of adding items (like arc, circle) with ESC key.2 a3 V* C+ A4 m9 b& g/ ?* D
dts0100632577 IOD writes to transcript some redundant information while symbol edition.* X/ a! r7 R* X" o) K' S
dts0100618530 IOD crashes after manipulating signals in the last step of symbol wizard. 4 Y2 `: L$ t" ldts0100619946 Symbol wizard doen't generate symbols with differential signals in specific case. Refresh problem.# {$ h! Z% r" l5 S4 i4 X" a( s
dts0100619965 'create bank power symbols' is not set up after rerunning symbol wizard.8 a8 b, b+ v D! Y* _4 B( D
dts0100626048 Sym Wizard assigning incorrect power signals to pins. ! F0 m4 s* I7 n9 c& }dts0100628170 Broken PCB symbols after updating. $ j- S+ h' t( u# } f! v- wdts0100629352 Symbol Wizard settings 'split only pcb symbols' were not stored in fpc.( y" r" c; C9 W# X1 b" ^, T" W ]7 E" u
dts0100632906 Design tool selection dialog is redundant because it is determined before project creation. - b! F5 G5 ]! T& ddts0100635477 IOD crashes while Symbol Wizard performs symbol update5 ?/ [3 j% |+ D
dts0100548702 Synchronization wizard in relation to Export cell from die should be corrected., o; m8 _- _+ X' |& L/ B8 d- j
dts0100596151 Synchronization needs to be less sensible. Moving non-IOD symbol shouldn't request import necessity etc. 8 j# Y8 s% a( i4 w- A% ydts0100599155 [Synch. wizard]Export Connectivity table is not available on Synch. Wizard7 ~+ a4 g' f$ Y# \/ g. c5 Y
dts0100606842 Everything is matched, however SW indicates, that synchronization is needed. : j g4 v# [0 i0 o% ?dts0100614895 Gray synchronization indicator sometimes blinks! g6 h" c; I* a9 |( a" c- ~
dts0100617886 IOD does not request updating symbols after unraveling (some assigned pins are not placed on PCB symbols) ' \ z1 y: y4 {) B. K* hdts0100617937 Synchronization bubbles are yellow while no tracked file export/import is needed. 1 q; X3 E9 x( P5 v, T, q: }$ t( ydts0100619881 "Document needs import " during exporting schematic for all components; T+ g1 H4 X1 ^7 C+ J
dts0100624493 [Synch. Wizard] Tracking check box does not work properly on Files View for DCDV files. H/ a) E1 ^+ j# o H
dts0100628627 Incorrect export sequence: CES and schematic, but should be opposite. Lost constraints.9 n4 x* n4 K0 E& L0 y- t& y& n
dts0100628925 [Synch. Wizard] Connectivity Table checkbox is sorted and causes CES disappears! z \) U, Y! q
dts0100631718 [Synch. Wizard]Import schematic is not required on new layout database * `' ^$ b6 ^3 y% V2 F8 qdts0100632062 Synchronization wizard contains not added files just after creation fpga database- S6 V5 E/ e/ l9 g$ C8 ^
dts0100633995 Lack of 'update graphics' in Synch. Wizard for Schematic Design import.0 t. k4 b$ ^$ X2 E5 G& r
dts0100635491 Import schematic is not requested in synchronization wizard after it is packaged (refdes changed)* P8 R6 J' F6 [6 c7 A0 l6 ^
dts0100620177 Poor results of unraveling for attached testcase. % t" R9 D+ G+ }" p) D) u6 d# Gdts0100629113 Unravel of crossover nets is broken. Immediate fix needed.0 V0 L8 S/ k* i# M# `# M
dts0100631688 Unravel on layout database does not work 2 q' |3 L/ A: H. O# Ldts0100491672 IOD crashes with PROLOG SYSTEM ERROR when unraveling nets in device view 7 I0 R( t* V0 u8 \; |- C) V3 Sdts0100636192 Broken connectivity in Device View - Synchronization Wizard suggest no action. Database corrupted. [ @9 Z% X6 o& J( W' a9 \dts0100632012 Incorrect warning message during export to UCF file.# P5 r, H. x1 g8 A! P% }
dts0100633340 Change default bus brackets for Xilinx UCF. - ]4 s3 `! }3 cdts0100614926 Please add support for ISE 11.2 library.! Z" S/ f. B2 Y5 u. Q/ P4 m
dts0100616172 IOD needs to support the Spartan 6 devices.8 t0 \* I: M) S$ @, M* ~! U
dts0100368440 IO standard has not been removed from ucf.; k" n- D" K# ]/ s4 D
dts0100622444 Redundant signal is imported from ucf: mcb3_dram_dq. / k8 H- W& f) K3 O/ O5 S8 [dts0100622447 IOD should not remove from ucf: TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 2.5 ns HIGH 50 %; ) X4 _, |, T. T9 q& m! ]8 H6 b% C: p! k2 I
# r/ l9 I( G, a2 _ / o4 @* Z, m3 J" i7 B: hFixes/Enhancements for DxDesigner from EE2007.89 q2 S- B; D; z p9 ?% a N+ r8 ?
-----------------------------------------------; h! e' k5 @' M. u. X2 o& A8 @
dts0100586982 ict viewer has a menu pick for slice and dice, but no documentation for this function. * _4 ~- I9 P) o" L$ Ddts0100566586 Icon for deisgn path for additional symbol translation in Translation result dialog is wrong / d+ H' C# i/ D9 @dts0100567745 Cadstar pin types are translated incorectly; X% d# N* ^: A! q
dts0100592920 CCZ output: Text has wrong orientation in CCZ file for symbols that have been rotated 180 degs or flipped ( a' R" ?% o! z* \% m6 N( ~" Tdts0100633799 Verify: drc-201 reports an error when there is none." n! {' b7 N0 q" P4 f
dts0100595040 Diffpair Restrict Layer Changes does not BA by existing ECO file' i5 N$ w, \: G' `3 Y: y
dts0100619515 It is impossible perform BA using DxDesignerLink & n/ @, _8 k( c3 k* F) n; pdts0100633269 DxArchiver is completely not usable for big designs7 G% F4 L5 `: Y0 q! v4 C- a2 Y
dts0100627152 The selected component pin object can't be got. 5 s6 P' C' n0 A) ]dts0100636979 DxDesigner crashes when quit command is invoked and DxDiagnostics is running * ^4 h7 _0 x3 l8 Idts0100637220 DxDesigner crushed when attribute is added by Automation Comp.AddOats / Comp.AddAttribute. - U: t( ?6 @0 u" @dts0100631832 Launching Dx resulted in an error of missing prop_reuse_gui.vbs. / d0 v& ^& n1 D' d& cdts0100626155 While crossprobing pins in Expedition, DxD crash. Scott was in DxD as well in the page that was being crossprobed to at the time.! Y: i0 I( ^# }
dts0100631134 Documentation incorrectly refers users to circle object if they want to create an ellipse% M K4 }7 j5 `$ a% r4 Z
dts0100614450 Live Verify fails when using the option "Use symbol data from Central Library". This appears to be a regression from EE2007.6. : N, g# A! a t& Cdts0100614912 ListBoxes to create query on dxdb grid display always all values from specific column during query creation.# R, Q" T" o5 N% K |
dts0100615165 Japanese menu problem: In the pull-down which selects the slot of DxDB, displays of "Slot" translated into Japanese are not all displayed.- m: L: c2 U" @/ g- ^
dts0100616337 "Part Number: invalid identifier" error during verification with oracle database when "Use symbol data from Central Library" option is set. L8 ]7 a2 Q3 p/ @ `9 g1 E
dts0100616340 "Query is too complex" error during verification with some central libraries and "Use symbol data from Central Library" option set. 3 h& J" f; r( v, H) @2 \dts0100616953 Closing and opening DxDataBook may cause disappearing icons on CL view tab." m8 @2 y' S5 P1 X( j+ h$ ]) q$ N; l
dts0100616993 "Query", "Criteria" and "!" buttons are disabled after loading component. 8 B1 ?4 d- f4 V p; Q3 P& t" }1 Y, Mdts0100617241 Export symbol(s) works differently if run from DxDataBook pop-up menu and NSE File menu option 9 t6 L+ a: k! d; L6 k; d' T0 odts0100617992 There is a error after selecting tables joined horizontally. , X, d- R3 N) M' m) b+ Rdts0100618179 When placing components from DxDatabook it don not change "," comma to a "." dot as it do in 9.0PADS, this result in error when doing netlist. 5 @, d' L V9 Q0 B4 `# b! Cdts0100629771 The query can not be created on the grid after selecting <ALL> library. 9 w, E! ]( v# o" A# Z4 ?& mdts0100629777 The verification buttons in databook can be enabled with Interconnectivity Table in one case and it can cause errors.9 s" ^- K$ p5 ]% }7 ?9 v
dts0100632306 In a Netlist Flow Project we cannot Select multiple Symbols in Symbol Tab of CL view of DxDataBook. ^, A; w6 u6 s( g1 L
dts0100632348 A message error is displayed during query creation on the grid for ALL library in some conditions. ( g1 ?( W4 _3 n$ w/ x, r* ?dts0100632402 "Clear the Current Search" option does not clear a grid displayed for <ALL> library. 7 L% J/ v$ l; |- i+ }dts0100632407 Button 'Enter user / password' is truncated on Japanese WinXP. a; D7 C$ J& @6 E
dts0100632412 "Remove Condition" does not work in <ALL> library. 6 e& F3 Q2 p+ `# Gdts0100632708 Verification in DxDatabook crashes viewdraw(regression to 2007.7)+ X: f6 `* t3 W0 d# R5 K9 @
dts0100634366 Crash library wizard during creating horizontal table for expedition flow. / W1 O& e" w6 t% \: y6 D: Z! a- Wdts0100637275 Crash during hierarchical verification on specific project. ' N4 r- V8 y- odts0100372438 DxPDF EXP2005.1 generates smal dots instaed of text on Solaris 8 and 9 : h+ @+ I5 T+ M3 C7 ydts0100541964 DxPDF pager order does not work based on the scout SHEET order property. Please reference DR 541962.4 R# n3 X% G* F/ X5 b
dts0100631034 DxPDF crashes if "Schematic Sheet Order Property" is used # T* J' b) {" gdts0100633031 Please correct the message 'Genration ICTs to PDF document (with conversion ICTs to schematics).' 2 J4 y* v5 y3 Y- `( j; Fdts0100602277 Pin number will not be displayed if Pin Label are either lower or mix case.9 c: d4 b' ~& Y: y2 w, P/ C/ \3 R
dts0100603902 "Add Missing ports" on an IO Designer generated schematic for DxDesigner the ports are placed outside the schematics. . Q5 C! {( R% V9 Q% n% k& mdts0100608356 Cannot read correct coordinates of scaled symbols in DxDesigner/ Z# r# @" e7 W" T6 V1 s7 g* |; h
dts0100611157 Part View place with slot fails with lowercase pin names1 A' k7 D4 E! k/ }. e' s) B+ n" E
dts0100615128 In the "Find and Replace Text"dialog, the "Select properties only" option is not translated into Japanese. 0 J x/ ^- h7 \' c" O; }, K6 R fdts0100615499 Japanese menu problem: "Select object > RMB > Pop-up menu" dialog has some issues of a Japanese translation. * U4 o4 i2 T; K* {9 Cdts0100616656 Problem with move schematic& l1 @, z* ^* v' i. g7 d" s
dts0100616682 Multiple Signal properties are lost when importing ExpeditionPCB netlist design to ExpeditionPCB iCDB integrated flow $ E$ _3 L, _ p6 m" U; udts0100616955 Symbol is not updated on schematic when editing it in NSE ( X$ h$ i5 g3 z( f _$ ?dts0100617637 DxDesigner must support metric symbol format" E& `1 U! Y8 ^3 w" S) t" X
dts0100618285 Properties addin does not show a name of a net ripped from a bus.5 {! u: U2 \" {& n9 q5 p' d, d
dts0100619905 Clear Backups should be inactive for a read only schematic.+ b$ w4 e6 I/ m
dts0100619942 iCDB error when placing an updated symbol8 V+ {4 q2 j. K& c% {
dts0100620246 Escape does not apply to Rip Net command8 h" E; J* R8 B0 i0 }7 X# J! b
dts0100621606 Update bus signals removes one of the bus names; E, s% \9 g! m `& U+ @/ r$ L
dts0100621892 unnamed bus segment created after renaming a bus8 G" J' v8 O; f4 k4 c7 w( d
dts0100622476 Push Schematic does not reflect sheet order : U9 T- h* w' }5 o2 E, m/ Cdts0100622848 DxD Diagnostics reports invalid net errors after moving a component! {) v- E ?+ \9 p
dts0100623038 It si not possible to add ICE Reuse Block to schematic5 W9 J' N3 z @, C4 w
dts0100623061 Enhance Add Properties Dialog; T7 a6 j8 s2 W7 [+ E
dts0100623427 [Linux, Solaris] Show Strokes option doesn't work properly4 Y8 y: u9 R* U" _) q
dts0100624036 'DxDesigner application has encountered a problem and needs to close' is not closed when restart is chosen. & d6 m$ K! ]0 \2 ]) @+ Tdts0100624188 add special component; [esc] does not work # n4 J- X7 s) G# x$ H4 g3 a. _) gdts0100624193 Change the message issued when a user types an illegal regular expression ]6 D# m3 \6 a* O6 U Z/ idts0100624578 Endless bus created when connecting to an off grid component9 h8 C. i: p) U' Z: @* K; a
dts0100624782 Symbol of the array component contains block name. , b" t4 U9 @/ T* j- X% L! R7 Ndts0100624866 Invalid global net created 2 v5 z# l+ t$ e' _8 Y8 @, u: I9 wdts0100624886 DxDesigner diagnostics fails to correct errors in an imported design. # {7 x8 \' H3 w* K+ _dts0100626698 While crossprobing in CES, DxD crash.: I7 M: s" ?1 }( W" u8 S
dts0100628557 viewdraw crashes when there is no write access to WDIR" n2 h" Y+ U6 O4 L( ~8 u
dts0100628735 Error 1287 when trying to delete bus segment. Diagnostics results in schematic that cannot be opened in schematic or block view. / E- M1 f0 t# K: O1 s8 Z' _& wdts0100628911 Modify delete sheet message when this option is chosen from the Navigator8 M! ^ T$ G6 s( ]0 q1 w
dts0100629037 'Error 1287: iCDB database update error: Invalid parameter' when updating bus signals $ M8 s& S' h) ~; h2 t# o- vdts0100629072 Select all symbols on a sheet and deleting the Ref Designator property values, wrongly adds Ref Designator property to symbols that didn't have it previously., d3 f( _& M, \; _$ [6 h$ v
dts0100629389 DX2PADS changed interface - update in DxDesigner is needed.+ N: A. k9 N0 }
dts0100629746 DxDesigner Diagnostics large memory allocation on this testcase) M. n: d1 ~0 }
dts0100629772 Buses and bus rippers disassociation when moving a circuitry around8 [1 i( ^4 z/ i, C: g: r
dts0100629789 Connectivity errors in a design created from the scratch. 5 u8 Y! j; Q/ E0 J' `0 Ddts0100630095 Shorted nets after renaming a bus 1 B7 R$ Z7 \8 O8 t$ y5 O. Cdts0100630174 [Linux] DxDesigner crash when I press Undo: ]* s" B$ l/ P
dts0100630197 Diagnostics error after changing bus ripper connection using 'Net is being connected to bus' dialog.7 F4 I# `+ F; W: K
dts0100630199 I get Commit iCDB database transaction rejected. Reloading project when I choose rollback X7 y* v2 L0 _4 }6 X+ V* A
dts0100630678 Wrong connection with GND and diagnostic errors after schematic modification: o! X! H* C" m ~
dts0100630683 I get GPF when I press Undo: W x6 A: ?5 ~+ y. d) W
dts0100630691 Incorrect global net name after merging two nets5 c3 L) {$ u7 o/ Z" ^( \
dts0100630706 Wrong connection has been created after updating bus signals in the project ) |6 ^- e/ M; H+ L- j2 j) Odts0100630958 "Push to schematic" does not work after using "extract schematic" during placing new block (regression to 2007.8.12157)- t2 p2 Z; U# ~; L' ^+ H1 V
dts0100630973 Problem with DxDataBook window when I change expedition project in to netlist $ e2 @8 N+ S& R, L4 ldts0100631052 viewdraw crashes when in a text being added to the schematic Unix like end of line characters are used (0A): a# x }9 F+ M8 e; l. C9 X# J' Y
dts0100631270 I got error: "Can't open symbol definition for schematic block!"$ ~3 V' R% b7 D1 a( ^
dts0100631630 I get Error: Schematic block 'Schematic1.1' has elements with duplicate IDs needed for Backup/Rollback and copying0 w* W0 x& g! x. C
dts0100631663 Renaming a hierarchical connector connected to a global net might create an invalid global net. $ c* k: f6 @: B. L( pdts0100631721 Navigator shows incorrect connections for hierarchical bus bundles7 \; j1 y, t% n
dts0100631730 Placing a composite with Add Nets and Add Net Names adds a net for a pin using bus bundle name.& T2 f, ~" m' {3 y# V# t
dts0100631935 iCDB transaction rejected - project was reloaded when three users were pasting sheets at the same time L, S1 G+ _4 o7 x% b- i: J
dts0100631973 I get GPF when I choose Undo option 8 g* U4 g% O# G: c; kdts0100632623 New Project dialog -> Advanced does not set paths to the cns and cfg files. " T: r) e! g- j3 Y; G. l7 Y0 ddts0100632639 Rollback option does not work properly( {7 y G7 J( Q# z5 f3 Z
dts0100632669 Rollback not save correct design state after backup fixed by DxDiagnostic schematic6 |( t2 Q$ x9 ~! `' [ n" D
dts0100632681 "Commit iCDB database transaction rejected" and eventually DxDesigner hangs when running packager and pasting sheet at the same time 6 a* d2 U; X; n( Idts0100632963 [Concurrent mode] DxDesigner crashed when first user was deleting some sheets and other user attempted to delete one sheet right after he opened the design ' |; a; n4 D9 h: E$ R5 Qdts0100633301 Cannot package design just after migration - regression7 w( V; b1 b8 G- K, Y
dts0100633970 DxD Diagnostics reports connectivity errors after undoing nets renaming, |) b; ^4 f( R. x" f) L
dts0100634006 viewdraw crashes when exporting connectivity from ICT 5 M$ P9 [9 r7 zdts0100634010 When viewdraw is restarted automatically via the crash handler ('Restart the application and open the recent project') it consumes 100% CPU and is unusable: |/ h3 O& B* C
dts0100634021 I get GPF when I choose Flip for ripper symbol # a; S S3 v/ ]# Vdts0100634256 crash dialog has some issues on Windows XP Japanese " u5 p/ |. Y" {! U8 t' Mdts0100634305 Issues with a DxD Diagnostics 'Test: Top Level Name Consistency'( t! \& J" d) i0 y: V
dts0100634332 Incorrect connections detected by DxD Diagnostics after copy-paste a schematic sheet4 e |* J' T* P6 e6 ~
dts0100634819 I get DxDesigner is Offline mode when I connect symbol with nets+ R; a; M2 j0 v9 j
dts0100635233 DxD Diagnostics fails to fix 'Top Level Name Consistency' error in one pass: k% ]8 S( @, o2 ~. q
dts0100635581 DxDesigner crashed after nets deletion 4 ^2 J4 `: |3 j8 fdts0100635605 I get GPF when I choose Mirror option# n; ?2 P- b1 o% A
dts0100635619 I get GPF when I choose Flip option; G$ N, K! d% u' l3 `
dts0100635865 I get Error 1287: iCDB database update error: when I press Undo ( i8 Z/ Q/ Z6 W" T8 E, ]+ f% Rdts0100635936 Problem with connection when I change size for bus; b) I3 n" T* y" z
dts0100635972 viewdraw crashes when flipping a bus ripper/ c, P8 Q3 H- i) \
dts0100636130 Japanese menu problem: RMB popup menu of component and Block.0 K- M& l1 q: w* B9 }
dts0100636316 Propagate Properties Hierarchically locks all the project sheets (locks remains after it finishes) 5 d0 s V5 U, o8 T$ t3 [1 zdts0100636336 During copy paste scenario, creating new sheet creates it in the wrong schematic.5 t! S0 N, U* A5 N6 ~2 A8 S" ^$ p
dts0100636675 I get Error 1287: iCDB database update error when I press Undo3 B0 C& |" d/ }" C5 M: M' `* X
dts0100569325 Copy sheet does not copy block hierarchy when copying constraints is turned off x2 ?3 w- C1 S* i0 mdts0100626105 DxDesigner does not undo and error message Error 1296: Duplicate IDs detected9 A8 {% [* z6 L
dts0100635209 New DxDesigner Crash Catcher Dialog Details button should be removed0 k( u3 x5 z) a) m- B, h) Q# P( Q
dts0100634336 DxD crashes after replace when ODBC(Text, CSV) alias doesn't exists.1 I$ i) L4 K. q, F8 Q) l
dts0100605359 HDL: the Unmap option sends vdel command " n; d" b5 r6 Y+ B# d4 ddts0100608880 HDL: Add zoom in/zoom out options to zoom inside the Waveform window. v1 R4 u- a3 Y& r& a9 j$ T5 w2 m% ], O
dts0100615226 Migrration on design with $ARRAY attribute stops without clear message what is wrong & z) Y- g. ~6 P& v# e3 Kdts0100615987 HDL: waveform stops displaying values after 100 ns- V4 a/ u$ R( w% c$ i
dts0100617492 Using Builtin ports IN and OUT in schematic gets reversed in the generated VHDL code4 S8 F3 d a: t$ ]0 p2 S2 m* R
dts0100617927 HDL: the HDL Target Library for HDL Design can be set as the Modelsim system library' Z# _1 O Z8 D: N' [9 X
dts0100620510 HDL: cannot simulate configuration for attached design5 {; K, ^2 g& |9 J
dts0100621591 HDL Simulation settings. ModelSim executable file should explicitely mention vsim.exe " S" T8 ?5 }& `3 C( M+ i/ B+ tdts0100621605 HDL: the path to the external text editor is truncated when it contains space0 A) V# b$ Q+ O% n# s2 @* D4 `: o
dts0100621903 Cumbersome handling of leaf components & a' G# o$ V# u& Wdts0100622290 External Dx-ModelSim Flow: Unable to backannotate sim values into schematic) p1 K3 a9 X7 v7 Q q% Q
dts0100625569 HDL: problem with the path to hdl file attached to component# d9 j# v( M. j, }- `
dts0100625915 Crash when setting the Modelsim executable folder ! R3 H0 G0 V% `5 v& vdts0100627635 Setting notepad++ as external text editor and then changing it causes runtime error, w9 p! m1 D+ F
dts0100627645 Changing the default external text editor has no affect until DxDesigner is restarted" ~5 U2 q6 t( Y
dts0100630111 Library is not shown in the HDL Libraries window when it has name with dash "-"6 o# K' r9 A/ ]' h
dts0100630591 HDL: signal names with signs ~, -, + and space are wrongly exported to vhdl/verilog* |1 C- ?; V% h5 `; _
dts0100631341 Inclomplete simulation macro for Modelsim1 C4 L% Z1 t9 z8 s4 K
dts0100633001 HDL files are duplicated in the Project Navigator - regression T, D* ~# w4 e
dts0100634318 Cannot set simulation top level when using ModelSim 6.3a SE as internal simulator S* s5 ?2 [/ z; u
dts0100635137 The HDL Search Paths entries are doubled each time I export vhd/verilog netlist3 l3 }( V6 a8 _$ X5 b( h
dts0100635583 Viewdraw crashes when editing hdl file, but the path to the external text editor is not filled 1 H M! l- r; n6 I! _8 idts0100629187 DxDesigner Diagnostics does not fix the attached project.: o" R4 [- `% B$ k" U4 ^, p* k' b, \- T- r
dts0100632498 MGC_REMAP_RSCM does not work with server:port format ( }6 J( ~& l" Idts0100620443 I get Error: (521) [Block fghf] Cannot change interface of symbol placed on schematic when I delete for block or net: @4 {9 H: T) {* X
dts0100625205 Reference designators for elements from fub in ICT, project explorer and Properties window are displayed incorrectly (U? R?) - W" K' M! i; e# hdts0100629327 Constraints are lost after rollback in ICE based design 6 W K/ H5 v! ]3 ^" Mdts0100629380 File->Rollback removes a design from Navigator tree4 |' r0 `5 w- B/ r! _6 D
dts0100631286 Symbol Update -> Clear All Highlights does not seem to work in ICE documents $ K4 M) I$ o+ S% H3 fdts0100631297 RMB menu 'Symbol Update' does not work in ICE based netlist projects # C+ r7 k, C" `1 qdts0100631302 It is possible edit Read Only RB in ICE 6 p* u/ O: J w. |" ddts0100592947 DA2DX did not rename the Supply Rename value0 ] S& B# N3 r: L
dts0100593885 DXD can not package if a hierarical symbol have vector pins nd the internal sheets have single ports for buss pins 5 M; k! K; O, M# p7 Ddts0100600087 few DA hierarchal blocks are translated into Blocks but not into Designs level* [6 h3 i7 E! ^, m
dts0100596003 DC2DA and DxDesigner need to support LineStyle6-LineStyle16 from Design Capture.4 B q% n: [7 p% K. ]/ g8 Q
dts0100630918 "Unable to open Central LIbrary" error message with the "Create local DxD symbols from DC schematic" option enabled * w1 L& q: o& z7 Vdts0100631073 Translation from DC to DXD causes Duplicate IDs that cannot be repaired using DxDesigner Diagnostics $ m5 F! v0 Q# d+ p+ A, t! Cdts0100615611 OrCAD Schematic to DxDesigner 2007.5 Translator should have the option to set all colors to "automatic" " X p' a, x- L7 ldts0100622712 The customer has an Orcad Capture schematic, which he converted to DxD. The schematics look fine, but when he generates the netlist and opens PADS Layout he finds a wrong connection (short-circuit).; }4 w' g0 |8 ?) a' M7 f8 D, B
dts0100624063 Pin types migrated incorectly # ]$ q8 P* z3 B# k2 e$ Gdts0100625630 Unexpected fatal error occured when there is no path to file in Browse frame0 }1 c7 ^9 |( |2 f5 R9 S6 v
dts0100632606 Specified file is corrupted or incorrect after import ffs file into DxDesigner using LineSimLink: Q' [$ u2 h t) j* @* S
dts0100633786 Incorrect documentation - Importing from HyperLynx with LineSimLink5 b6 i; r" V" o3 z
dts0100619566 Export ccz - rotated properties are incorrectly exported ' h% d# x4 ?5 K1 u! zdts0100619652 DxD Packager dialog has incorrect text- |) N/ a& C' j- C
dts0100622705 Solaris - File->Export->Analog netlist does not work9 K2 h7 g( f. p& W$ l5 b0 N' T
dts0100624832 [Linux] Viewdraw crashes after Replace part when data source is ODBC compatible. ' p6 m$ T# W9 X$ i6 L! Edts0100624912 Add hierarchical property propagation script to the install7 c. f, m! c5 ~9 u# o* F
dts0100625050 Schematic sheet cannot be opened after updating EE2007.3 project to EE2007.5, EE2007.6 OR EE2007.7 4 p5 o) d& I6 }. L2 x6 r- C8 p3 u, ]& ddts0100626477 <install_location>/2007.8EE/docs/data/DxWDIR.zip design not working/ Y u0 X' x7 ]/ k9 w
dts0100626672 pdbslot crashes DxDesigner( z. k2 g+ F t
dts0100627156 IOD cannot create Design. vipc: Error 1347: Unable to connect to VNSD in vipcInit(). r& |5 m; i: w) G9 g8 z$ c
dts0100629663 Crash after double-click on schematic component in Variant View.8 E3 a6 z2 J! P
dts0100630994 "Cannot generate Schematic view. Finish or cancel previous operation" message from VM when reuse block is included in Schematic : `; h9 @! M3 D+ z2 b2 ?) Ydts0100632331 Rename "Propagate Hierarchically" command into "Propagate Properties Hierarchically" + }+ x# G0 n2 s* n4 V5 }dts0100632334 Change default properties in Propagate Properties Hierarchically script 7 `4 H4 f! B6 a4 a `- Idts0100632337 Propagate properties Hierarchically icon is not available in the toolbar % i* d! o! M3 X7 J& q; A @dts0100632404 Duplicate IDs detected on opening th design. DxDesigner Diagnostics does not fix the problem permamently.- W/ Q2 p& [: P( b% I8 I
dts0100632710 Viewdraw crash when generating variant view 4 }% |4 M6 D: ]* X! r/ ldts0100632857 Failed to package ICE design. ) ]7 l) ?/ d9 s) w% j1 \5 ldts0100632960 Crash on DxD exit when changes in VM Settings have been made.) n; l( h$ ]- U+ U* f" n
dts0100634277 Packager does not package new components in migrated schematic 1 `( c$ w1 x" ^, {+ @* @dts0100634650 Change default property names in prop_reuse_core.vbs script - g% k; [( ^1 Wdts0100634653 Rename command "Propagate Hierarchically" into Propagate Properties Hierarchically" 3 I E5 }3 r r' L5 `6 gdts0100635522 Remove Propagate Through Hierarchy command from Properties window $ A3 k' z( x- G1 b0 m4 udts0100637029 Dx crashed when I ran Dx diagnostic checker and FA was runnnig - m* Y. b* K$ Xdts0100637288 I can't set PropThruHier and StopPropThruHier properties in the netlist project+ |0 |* P: R! X( S" Q' a
dts0100539584 Its not possible to rename the design name in the DXD Navigator (only 1 design) , h5 Q1 s- L9 c5 ], ndts0100625769 Navigator components do not match with page location4 ?, M6 Y+ m5 g3 H+ Y
dts0100626019 Nets are visible in the Navigator window after unchecking 'display nets and buses'. , F& U1 o* p( C1 K. ]dts0100632951 Navigator shows wrong information after renaming a net6 S; k4 [" T: a
dts0100635134 Navigator shows an unnamed net after deleting a block ( a1 A, R/ A4 Sdts0100635587 Adding new sheet gives incorrect behaviours9 @$ k# L. z# f3 P# Z
dts0100635956 Navigator still shows connections after disconnecting a port( }; n* D& Q1 ]! v# a+ k
dts0100605863 PCBFWD: Customer can not use Arguments in "Customize Tools Menu"8 f7 p# v: K! f. _" u9 J E' ^
dts0100625279 In this testcase (hierarchical ICE project) pcbfwd crashes. 4 m3 I, q/ D1 z6 S2 c6 A2 L: f$ Ndts0100630594 Please add PKG_GRP property to the netlist.prp file. L0 c. F# K0 v, _
dts0100630612 Add PKG_LOCK property to netlist.prp1 J1 v0 F+ r" ~
dts0100631001 Wide pin swap does not work in DxDesigner <-> ExpeditionPCB netlist designs 8 g' Y# n& B' `7 fdts0100633309 The pcbfwd fails just after migration - regression 2 B5 j/ u2 ^" _- [, ?" n5 j. R& Adts0100629388 Packager cannot package the new PADS Flow design. f0 J: N' p" A" T# T5 C
dts0100626765 DxDiagnostic process takes too much time* P, I- O6 m R7 x
dts0100615088 Japanese menu problem: "File -> Print" daialog has some issues of a Japanese translation.7 p/ N6 |. u1 O, N- o
dts0100632470 Altering size of print preview window causes navigation buttons to disappear 8 t% l/ p$ N, bdts0100623059 Can not edit Instance Value in Properties Window) R* S% R8 A z. J8 A2 _
dts0100623081 Ref Designator value not visible in the Properties addin , h$ G$ S' G' h/ M9 `$ w; ~- Xdts0100625986 Project was reloaded and Error 1287: iCDB database update error: Invalid parameter was issued to Output dialog after a pipe character | was used in the net name 2 H) g+ |6 r2 k; v3 ]4 Vdts0100626286 Prioperties addin does not allow to use comma character needed to alias nets e.g. A|B,C! a$ m+ {' @* f5 [( j7 L( V
dts0100627194 Properties addin does not show net / instance names added by ICE (with $ character) - E0 h$ v. q$ V4 M, N3 B' cdts0100631681 [Linux, Solaris] Focus on wrong edit cell in the Properties 7 b* e% v, l8 Q) L, D& ~8 tdts0100631748 Properties addin does not show a name for a bus bit going through hierarchy3 P6 ]% M- p5 H0 {* ~; b- H
dts0100636993 Add NETNAME to Global Signal Name mapping in map.cfg file ; T9 G8 Y+ [7 h/ R2 `! t0 adts0100620072 Place Reuse Block in Schematic Hangs DxDesigner # U, v: H0 m7 _5 J5 bdts0100625913 DxDesigner crashes after change to ICT schematic with Reuse Block8 J7 A: i( _9 p4 x( f
dts0100631979 Duplicate IDs detected after place very simple Logical OnlyReuse Block 2 f' Y: o H4 m: \3 `, k+ \+ E! fdts0100633096 RF: Seg Vio when attempting to send schematic from AWR to DxD using the replace option. : Z% U( ?! T; b5 O0 J$ W9 N: Idts0100606970 CRM is leaving a net with MST topology but having from-tos, W) Q8 g# o2 C. Z$ m: M
dts0100616398 Change page title from "New Objects" to "Text". + M$ o7 O1 V+ ]4 y2 e4 vdts0100616401 Rename Nets to Nets and Buses 6 Y* a- _) _/ Y3 `; ydts0100630588 I get File not found when I choose Settings for netlist project % ^1 z6 r! B% Idts0100634268 Strange chars in the settings for vhdl/verilog ) F! [; E4 r4 S1 mdts0100495671 Strange rounding in millimeters ( p* \8 K/ Z/ @; p; {7 Qdts0100549052 Can not use Japanese font in Symbol Editor.& l3 r6 B4 l( W
dts0100631373 Unable to Save Symbol: Error UID Manager: Object not found & |% p" j0 h9 S8 hdts0100447920 Rules for Open Collector and Open Emitter always display error even if are used in good way S5 |" Y; b5 O( _+ c- f
dts0100564958 VDRC does not create vdrc.log file if there is no "Log Files" folder i project directory. 3 t5 P1 L) R; ?' v, B# m! a5 W+ `dts0100575820 DRC-201 does not work correctly/ J" r y" G$ v4 Y4 Z5 m
dts0100615921 "Un-loaded net" does not work in the case of "PIN" type symbol. 5 d8 U2 _9 f& h, f) y7 vdts0100631988 Cross probing from a drc-103 opens a wrong sheet 3 A! I1 j4 r2 Sdts0100635214 Connectivity warning drc-103 is displayed twice for bus members作者: biglin 时间: 2009-12-21 23:33
Mentor不這樣怎麼搞錢.作者: calvinxxw 时间: 2010-1-21 12:01 本帖最后由 calvinxxw 于 2010-1-21 13:40 编辑 1 ?5 H5 Z4 ~" M5 B; _8 J$ C/ k; ?0 \* _& J" }4 o5 @
2010/1/15 正式发布了9.1作者: panadol 时间: 2010-1-28 20:04
没有太大的更新哦！在功能上！作者: careywang 时间: 2010-6-13 11:58
多谢！