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标题: cadence spb16.3正式发布了 [打印本页]
作者: tqwang    时间: 2009-12-12 17:07
标题: cadence spb16.3正式发布了
CADENCE SPB/OrCAD RELEASE 16.3 README --
+ w# S6 N) {) eWindows Version  
* ^6 k" e0 p) C: t$ }Installation Guide  & c/ P9 \3 L$ z# v( e
You can find the Cadence SPB/OrCAD 16.3 Release Installation Guide for Windows, Version
+ M/ \, s4 w/ y2 _# u! L16.3 (pcbInstall.pdf) in the Documents folder of the Disk 1 folder of the Cadence Product DVD.  
4 L. x  }7 [* n+ w% ?$ P( o$ jMigration Information  
7 r! r1 `8 G) O7 r! m8 p! KImportant migration information is contained in the Migration Guide for Allegro® Platform
+ @+ s  w' F+ ^# m* I9 C  E9 J8 fProducts Release 16.3, which is available when you install this software or on Cadence Online
  v1 R  T0 U5 i# s5 zSupport (http://support.cadence.com). , v% \0 g9 x6 H) ]6 `

8 R0 R8 e7 X& [' A/ `9 b! C; a7 JNOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners 0 e# l+ ~, l) W4 n% W" U1 F+ u& M
are listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.   }3 @& c1 r+ q" d9 b0 [5 Z, ~
System Requirements  
  E- Y, p9 T7 m' F) N8 K. S9 s8 |Information about minimum and recommended system requirements can be found in the
' ?, m1 o: E9 l' ADocuments folder of the Disk 1 folder in the Allegro Platform System Requirements document ) b9 `( x" |6 o5 x: B9 ?
(pcbsystemreqs.pdf) or on Cadence Online Support (http://support.cadence.com).  7 \' }1 o& T+ E& W& l3 P
2 R+ i# l1 J8 @8 ?3 H
NOTE: OrCAD customers need to contact Cadence Channel Partners. Cadence Channel Partners
  P3 ?4 L5 D! E& o3 Q- F- v% lare listed at: http://www.cadence.com/Alliances/channel_partner/pages/default.aspx. ! ]7 t; @% d% C! Q' }" f  J
What’s New  ; R5 `, j4 ^3 ], @: I+ u
Product release notes are available at:  
7 Y' E2 X3 W! u[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi[/url]
' r1 w; Q& W( hng/spb163/prodList.html
- s- W$ I' H7 D; |+ QKPNS  8 \, w6 M/ a! D* J; t
The Known Problems and Solutions (KPNS) document is located at:  7 ^9 w0 N6 L3 Q6 X4 [( c
[url=http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=pubs;q=landi]http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=pubs;q=landi[/url]! d  _1 J' ~7 s* M
ng/spb163/kpnsList.html
  a1 A* ]; y5 n  U1 QAllegro® /SigXplorer® ABIML Libraries for Default Trace Models ) B* M* o' w  N4 ~' `0 [+ s3 v) ?
with Surface Roughness Effect " y9 |2 V2 G7 x6 {9 s9 \
The Allegro /SigXplorer ABIML Library is a free library that includes ABIML libraries for $ E. c+ `2 M& Z* d; K; j' r
SigXplorer default trace models with surface roughness effect. It is designed to provide accurate
% W# I$ |  J3 s3 i* ^# e$ E  ltrace models in Allegro /SigXplorer without time consuming EMS2D solver runs. The libraries 1 }$ w5 z6 Y1 J5 o
can be found at: # K6 `$ h9 f! d& t( C
http://www.cadence.com/products/pcb/pages/Downloads.aspx
$ Q) k9 w; D1 p1 X" U6 O  J& ?This ABIML library is provided free of charge for use with Allegro and SigXplorer. The library ) C! k; |5 D8 D$ L) t6 R
is provided as a zipped archive, with installation instructions included. # r+ [4 |  n+ j
Custom Environments
6 b4 e/ I& T) P  n) D; RCustomers using custom batch files or scripts to set up their environments must add the following
6 A( {9 A* p+ r* a+ Z4 Q# Z( tto their path. There is the potential that some Allegro products may not launch without this # R; N2 c( a7 r1 U: @* S7 @! ]" H* }
setting. 6 v3 _" s! q, t( O" q
%CDSROOT%\OpenAccess\bin\win32\opt Downloading and installing SPB Software 3 h4 k5 F3 ]4 s9 k& v; R: N. ^! B
Cadence software can be downloaded from:
& N1 u* H. Q4 `. i/ x) y* d- E1 h% D) chttp://downloads.cadence.com
3 e' h: Y' v' S( o7 r3 r
- H( O8 m7 H3 wNOTE: OrCAD customers can contact Cadence Channel Partners to obtain their software.
- S& q/ q8 n; k: m$ eCadence Channel Partners are listed at: $ ]5 T% {' x) @, c
http://www.cadence.com/Alliances/channel_partner/pages/default.aspx.
' w- m" ^$ v! |& ?; Q$ j
! F7 I* x0 c- |& aDownload Disks 1 through 3 and then extract the zip files into a temporary directory such as : U4 h3 X0 Y' Z9 R; T- k
cdnstemp. This will leave you with a directory structure that looks like:  
# y. K8 ]& _5 X. G) a4 D" p 0 a+ R% v; K! j" _9 d% G
Disk1 folder 7 M! T; T6 V$ M6 K
Disk2 folder
6 ?, u4 B8 N' v8 `; VDisk3 folder
8 T$ ^* V0 C- U0 oautorun.inf , ^1 m& }& s* m" v' @; W
setup.exe 0 y' n; S, t- d+ i4 u
setup.ini 7 b9 {- {9 X  O; @

, F! V* Z4 Y: [: m# u- b0 D- |Complete the installation by running setup.exe from the temporary directory or consult
3 W  ]* b# R" T/ X% Q9 O9 ~# ^+ Zthe installation guide for more detailed information.  ' E9 h% }7 z7 Z; `  W  y  h

  b* [# ?, f2 b$ v: H5 f: tWARNING: The installer will automatically add the programs in this release to the Windows : _2 v& o$ l! J! a8 p; P
Firewall Exceptions list for Windows XP and Service Pack 2 at the end of the installation
; J1 `0 b' {9 b6 xprocess. If you do NOT want the installer to do this, you must run setup.exe from a DOS
. c: V' G$ l+ U) e- k: gcommand prompt window with the following switch:  - v* _4 h! A6 Z  c
  A4 ?" W& t% ^+ [3 W8 v
setup.exe -nofirewallexceptions  
8 t, C8 K7 R: I
1 A  m3 D9 S* X4 J! jWhen the license manager installation is complete, continue by installing the Cadence 0 H. J( D0 U4 C& \+ Y# s
products.  
: i: r& S! |7 M4 W, c
& n# u# g, P4 u- k6 fNOTE: If you are prompted to reboot, reboot the machine and log in with the administrator 9 {  D6 Y0 y! r' [, E6 J
privileges login id to successfully complete the installation. List of Fixed CCRs  
8 f9 u- m1 N7 `* v: R, K8 S# z•  Enhancement CCRs
+ l4 v: s+ b, C! L•  Bug CCRs : c' D. R, V$ Y2 e8 p+ d3 m1 T
Enhancement CCRs:
) Z7 O8 f; \+ ?2 k6 k
/ ], ?* R. q' Z: r+ \& S+ kCCR ID  Description 1 B2 \8 R' q/ W' F2 H
7419  Customer menu options added to Allegro menus . i# X0 V& p/ ^
8230  Use via in area constraint does not work 5 C- |9 m6 O5 k$ j. C0 C) P- ^
10658  Modify default formatting for Label texts and linewidths
! a  K) |6 v# n1 {9 F12216  Cannot set color or line width for wires on net-by net basis / K, ]6 n2 S) \* c0 [7 j( J$ n' K
13083  flip/mirror design to back side & m& L' v% H/ y1 H( A) z  g
13373  Select length of pin graphics
1 Z4 o/ ~' F, e6 h1 a- n% Y18072  Add docking option for probe cursor box.
- G# N" I- s8 H9 y* U6 v; m$ E21451  Change Probe print trace color yellow to alternate.
# N( q  N# ^. L  P  w0 v32798  pxllite complex hierarchy netname enhancement
3 `" x2 K; u2 r. h7 L$ |, Z) I: @% F33896  Option for changing the PSpice probe cursor   D: ]! E$ F% @8 V
39600  Option to see time spent on allegro database
1 g5 }3 {" |* c8 P0 W$ L* c$ l9 d40754  Linux OS support for PSpice
. Y, \1 {4 h) o60427  Add different subclasses for pin_number top and bottom
' S* a7 d& g% e, h! {9 k! m3 l77555  Capability to export PSpice probe data points in csv format " u) Q$ x  r+ X$ m# w0 V1 v0 P
107219  Capture.ini switch is needed as a Registry entry like PSpice
0 |/ {& \* A2 U132769  Footprint viewer in CIS should also show pad spacing info / k9 V4 a* G# q
158838  Need easy way to delete marker + Q9 V4 L, `; Z# t& N! y
159977  need attribute mapping capability in mbs2lib and mbs2brd
3 z* e) [9 \, t7 ?% E/ D162382  Enhance quickplace using schematic page from ORCAD
6 A5 w0 ?2 y& f9 Q) t164790  Improve autorouting quality on diff pair w/match length rule
) }  ]+ I# {9 M205909  Constraint Manager displays in Allegro no graphic mode
1 v% `. ^3 e9 Z+ j4 ^/ @210027  Delete dynamic shape removes net name from copied vias
  R7 s; Y7 f6 R& r& e222127  PADS_IN: Constraints are not imported with the design.
; h# B! h. y, B( P0 l' Y: h236698  Report Unused parts in multiple parts package should be DRC 6 L- ^, ^* g/ z9 W" H
240525  Add ability to change cursor color in PSpice Probe window
+ Y: l+ S% G& z$ a, k+ S245193  export dxf height information when blocks are unchecked
/ q9 q3 _3 r  [" E$ j5 _254183  Multithreading for DRC and CM analysis in Allegro
0 @% J" E2 ~# q" _' X% A- Y282027  Problem with Split Part and part graphics 2 U  s4 U6 h3 q) ]
282507  request to import IBIS file directly
5 g" K  {! B8 @! p& i283698  place by schematic page number window need enhancement
8 ^5 D; L8 n& E2 N288540  Schematic page# display order request for Quick place
1 {: Z" T, G' C290283  PSpice - Probe - setting background color from UI
" h; \) t2 P* P/ x& g290641  Option to copy paste cursor value
9 {. l' r6 q) }" f298081  Models from Funtion.olb need more explanation
9 c9 P" l% n: M, j& [) ~323813  Need negation and exclusion function in ADE reports
. L# e6 Y: x0 }7 D! _341484  Wirebond: Tools to generate wirebond manufacturing outputs
& Z  l7 N* c3 A' Z353212  Variant Name is not coming in Standard BOM 5 C; s) ~" f: W1 V3 J2 B  t
360602  Enhancement to Show element on a via
$ U. G- G: c5 Q2 T. J1 ?362934  Enhancement for Allegro to utilize Dual Processors.
7 i  ^6 X; x* K, u1 u- Y& d  J364850  change the font properties of Label Text 8 e8 }! Y& F2 z8 j: B
367468  Need a real DML_PATH environment variable # {- x8 e8 ^6 y
380714  Ability to have Power pin set to Not Connect
. q9 M9 R, R# L4 U( f# ?* Z382860  Display parts and nets in different colors / ^2 t5 T- D0 n' n4 ]3 t' F2 M
384488  Add DEVICE and REFDES filter to Signal Model Browser   y- N( B4 |* L& E& w  r
391487  Ability to have user defined directory for storing distribution files for MC analysis
: _7 }* W0 N( t' a5 a, D420008  The renamed differential pair names are different in CM of ConceptHDL and CM of
) x7 o8 S7 v2 z9 N& oAllegro.
9 |( J  }, r$ S/ l7 K0 ^1 ?420023  It should be possible to Delete a differential pair defined by SIGNAL_MODEL (.dml) on
; g$ W8 b. O  P9 {, Z- D$ \CM. 420648  Need to get RF Elements to retain previously entered values
# M* B* Y0 A+ s1 \8 q' f* ]" B429280  ARC is unable to load/save rules - submitted for tracking with Medtronic SiP benchmark
8 @$ Z2 ~0 K5 ?8 y+ P5 E, y430549  GUI for ADRC XML Rule files
' m' l  f, G% W" P1 B$ r430558  Store last used ADRC rule check ini and check values in .sip database
  I2 I! m8 I# l: b; a452606  Can we have last plot as a default  
( W" O) Q  }  h9 e! o5 F454452  Allow neighboring/overlapping die pads on same net to go to same finger during wirebond
. E1 c2 G: @, ?- ]" E. dadd. . W) a1 Y. r/ v6 a- _; H
456854  full AMS Simulator menu without pspice.ini in registry   w  _3 r; E4 q5 D8 q+ z
464056  Setup option to always prompt to baseline a new part
- X$ f' P( R% l5 H7 l, `4 t+ u& d469378  Enhancement : Hide/Unhide feature for trace
- M& i! W: E3 A% x) j( N475077  Schematic Generation Setup form is missing the Port symbol selection.  It was there in the + }6 f. Y2 A9 d6 G9 U
15.7 release.
* U% t& z. R5 l8 U3 {  s475714  User Guide should mention that Temp Sweep is not honored in AA Flow? ) V- O# L1 ~* T. M9 N+ w
480843  Requesting ability to View > Zoom Mirror current view. % i  s6 ^) O& |0 s
484632  Request for Bond finger to snap to Guide in Free placement of Bond pads ' d# R' j" v& U
490948  Provide a sketch line and text property form   A! r& J- f/ n* ]3 |0 \1 l( E
500550  CRef's should be preserved with the next run of the schgen in the preserve mode.
% A! E  ?, B6 s: T505284  Enhance The ConceptHDL can set the color for $XR0 property.
; b* j$ C4 I0 W0 W; N5 o" w; d2 [512748  improving arc routing - g( ?! a" m7 }  |6 f4 a" ~
513967  staggered C-line via arrays ) U9 V! S  n. P- K  q# h
515333  Option to specify spacing between Components in the Generated Schematic
( U9 R* |" K6 r1 D524924  Add PSpice enabled part gnd to standard library folder 4 k# [9 I, i/ ~, B% J
525748  Why is MC Analysis Sigma value 1/3rd of 15.7 version value?
: ~: j% D4 b) L0 g526818  Retain Hard Packaging Information option does not work for SECs. / D/ n5 t: T9 Y3 L
528391  SigXplorer measurement is wrong 6 ^. `; j0 P2 H+ F5 |! C
533844  Allegro password not encrypted in the .brd file.
/ h9 b3 `) z  y7 h536681  In the ADRC tool requesting a "Layer" option for Conductor to Package Substrate Edge ' Q. Z) {" d8 \4 u; L
Spacing
+ t0 `) t+ P! y( G536948  Allow  sorting of power symbols 6 [" N- b5 s* Y4 c
539407  In ADRC Minimum Shape Check requesting individual "Layer" option ) t& {7 h, {  [: r' |+ v% Q- _
541145  slide command does not support to keeping the existing arc
0 v9 m! _6 r; ]# j$ p. i/ J% `) H0 A541214  about supporting OpenDrain Model in Quad2signoise $ _; k  }$ C- ?' K4 ~
542414  A function to force diff pair spacing to primary gap. 8 l8 J( C% a$ u# E# B4 f8 G
542803  A "Minimum Shape Check Soldermask" entry is needed in ADRC / T/ f8 z, B% T% [1 I, t
543470  Provide rectangle and line width thickness for Drill legend in NC drill Param
7 B" a: n# |0 {' f2 ~$ O543766  Crefer fails to annotate occurrence properties to offpage symbols in replicated blocks 1 V; I7 K; S- s' Y. ]
545408  Cursors are toggled off when deleting a plot
! Q( Y: n6 |  e  }  b546891  Enhancement: message improvement when expand design action in Concept
( |4 K6 e' v' M. S! u' Q$ o546985  XOR function to allow to compare layers within different or same designs ; M8 l- R& w- g& L
548920  Add a document of which properties can be synced and which cannot be and the files - R, t$ N* V- B4 s
required " W  s) V2 }  N" K* |
553669  Add a 3D viewer to Allegro ; l( R- ?2 _* S- f  V2 L1 E6 t
555183  Wire Bond Report --- Report field should have save function for reuse
! p* M. j* O) H4 a' v8 K556200  Need listing of DE HDL command names and switches.
& {' D% U; z* ~6 O4 J& [556883  Grid point for Origin to be highlighted
7 W/ U( {8 E7 d* `4 ~  M559638  Enhancement for importing height from PADS in allegro
. y( t5 U- z- B% [- `- ?559724  Request cline via arrays to be applied to diffpair nets $ N2 q6 n9 p; n
560134  Show Element Customized Display
3 }' }  j; Z! n563957  Enhance Color Dialog form Class/Subclass section to expand vertically when the form size
8 ?9 {& j6 |1 Y+ l2 {* W8 Lincreases. 5 r4 c- u" u# g# _8 H
568058  Request to have component information available through the context menus 3 G2 }* k4 l) {1 o
568273  documentation of variables in Capture.ini 4 r( b0 R* E; ^" Q) P" g: i8 |
569615  Enhancement to import constraints from Mentor Board Station to Allegro PCB
& I& R& a; [& d/ i7 _, }* m569680  BOMHDL defaults to the wrong file type when html report type is selected
0 ?0 z1 e7 @) P8 u' g. ^569784  Request ability to assign netname to via during copy
$ z% e$ Z3 Y# t569863  User would like to set a larger default trace width ( F$ F$ p7 T4 g! G+ S: \7 P2 Z) x* e$ C
570128  Enhancement : Packager setup for subdesign drop down 6 ~  ^$ w/ x9 Z8 T% I' J
570195  SiP - Provide option to create/combine BF labeling with additional text required for Bond
3 u* `9 Q8 x! {diagrams 570861  Unconnected mark does not be removed even after wire is connected to the pin. 6 |3 `) N( A- A0 W  h: b
575211  Web links in CIS explorer are not working when Firefox 3 as a default Browser
4 O; |& F3 e, F" e577944  Enhancement request to have the drill legend for thru holes and slots to be separated without ' ^' Y$ [  |" i3 [6 D+ y% r  K
being on top of each other ' y( D  ?9 \6 a$ s, M
583630  Can Multiple Section pop up box be disabled?
& d& M+ e' ]7 m583712  Ability to have string values for SCHEMATIC_GROUP property % p# G9 ]. [2 o
585904  Find a schematic page with help of nets
$ P) z# K9 P6 p( F- p7 |" b% d589316  Document change in Gaussian distribution for PSpice MC from 3 sigma to 1 sigma 7 B$ T' u+ ?& B; \% {, Z
589512  RF component snap is 'too clever'
9 T2 a$ o3 g5 D$ C/ F590246  CIS to Allegro flow to include or ignore constraints same as HDL to Allegro 5 K  I! W; J/ D& n* M$ V* t+ y
591306  Suppress RF edit window when changing RF Element properties 2 I& A/ z' j( T0 k5 C+ \) c1 s
591318  Use RF setup values or retain changed values in RF Element forms
- d. s3 Q$ i" ^- {5 e% o' h) F591443  Temporary highlighting is lost when using the Copy command + {2 b% j, m5 U1 v3 u
591450  Provide a dynamic tapering option to RF PCB Route + K2 j9 e# H0 v# C! Q, X9 ]  l# I5 v
591489  Would like to suppress RF Snap windowing around the user pick automatically * z. g: k! S  D+ T2 ^( K& h
591812  Provide move options for the RF Snap command
- d, d$ N5 s1 Z$ h$ ~. s591817  Provide easy group and element ID in repackage form * Y, x! P8 f/ `  U( }# \
591825  Quickplace for RF Elements
' Z2 F; _6 c& m6 N* I' n2 |$ K591865  Request for more information on 'Other' Netlist formats
4 Q  \# D1 c( s0 v: @0 ?% q596392  Publish PDF needs improved error messages for missing installation. 7 Q9 y. q9 R+ {$ b' A
596555  Request alias symbols documentation to include and clarify when necessary to rotate 180 * W' B5 ^% S3 M, p
degrees * s/ O3 ?  E# _4 d! I0 ^2 F
596843  Cannot do global search after importing read-only schematic block 3 C$ \: O$ l' R6 U4 O
597808  Option to increase the default thickness of all traces in Probe
4 R4 g- |/ \. q. J( @- S599499  Plotting from within Allegro does not find path to stipple file
+ O. B$ `( S0 X: \604125  Manufacture>Create Bond finger Soldermask.
( }# W/ |. i! {605023  Need rats by layer function for Free Viewer 0 @$ S) p! e) ^  _% v
605112  Dies should not be counted as conductor layers in Design Summary Report of SiP
7 ]$ e* B& k8 ~8 O8 p( n0 K, s4 J7 Q% h605373  importing and Exporting BondWires & ]' i1 h! E7 H& G
609035  Voltage_bus part - Make pin number invisible
9 R4 Q- @$ s; x9 A5 j0 l/ t% Z609561  Enhance Circuit Replicate to support coppers shapes connect lines and vias 0 {+ \* r( y1 s
610934  Retain user input values in RF PCB forms - p' B. |' b7 Y
612008  Mirror Rules need to be documented for axlTransformObject. 1 W! N8 y; L  h/ {
613639  Update Documentation for "split_inst_name" property.
9 }9 p$ X: {6 l2 I0 Y+ g  C* m, p614345  Email facility for Design partition on Solaris does not work
! l( d! r/ O% e615139  option DMFACTOR  documentation missing in pspcref.pdf
* C& L$ t6 q3 [% o: x$ w# u615374  Retain Soldermask Thickness value in 3D Viewer Options 0 e$ i( }" k# X3 u9 _
615850  Auto Setup should honor device setup parameters if component value is null , \+ ~8 a9 y. C' Z3 D6 c" N
615988  PDV WHen importing from Mentor does the browser not remember the last location of
; E. A3 N' O0 m: j9 z  ~import
) s6 [8 L- R! R* F: m  n' p5 W7 _4 ~! ^616529  15.7 Design Entry HDL fails with Out of Memory message 4 T$ Q! ?$ b* [
616873  Uppercase characters in design name error should be improved 1 o4 G1 o4 X& g: o( g/ K2 G9 x: w1 E
617976  Enhancement for a way to sort user subclass in define subclass form # G+ g: N7 s% O% i2 P! c* L- B- P
620289  Server 2003 support information in pcbsystemreqs.pdf
9 F, n) |# G" ]* M# L1 O- U# Q620303  Enhancement: Shortcut key for "Select Entire Net" + l* i/ }7 V& D7 ]6 f5 V7 w1 ?# E  H! d) O
621054  Renamed net in netlist isolates components from the rest of the net. 7 i* q! C4 j! R( r
621955  Offset Via Generator utility should show a warning message if vias are already present. . a: {8 ]1 n6 T& ?
622203  Requesting that "DFA Constraint Spreadsheet" icon be added in Customization >Toolbar ) `* X' o) `, e# n; u
commands 3 j3 p  x6 e& L" F) H# F% `$ _
623218  display pin names associated with a net in net Properties
) n$ S/ V- b( [- z( s623908  Mirror Symbols while dynamically moving enhancement
- |0 A' B4 }; c( F( m- f624817  Display padstack name in data tips when hovering over Pad-stack
6 D$ Y; k1 t. O! e625733  In Netlist Report they are requesting square bracket vs angle bracket 3 W, Q. R. U( c# }
626605  Extract topology with routed interconnect to include via's in Allegro DesignPlanner, PCB ( ^  j+ s) Z7 R+ h, b
XL and PCB GXL $ B/ J- {! g1 e: O! z
626673  16.2 Die Stack Editor - Add option for DIE x y cords within DIE STACK form - shows
& z+ k- y6 _* f( u- crotation and allows move but
( k# Q0 O  J7 {5 k/ G  x; w629008  enhancements for find command
( s6 s  _) C6 k/ f6 j629548  Request an Option in Create Plating Bar where it may be directed to a different Subclass 630949  DRC for bond wire to bond wire requires additional parameter "wire profile" to "wire + \5 S# h8 V; M$ c8 M! y4 B0 Y
profile" " |3 X5 n- k0 H
630955  SCM does not see design difference after update of fixed die/BGA in cdnsip
1 F/ F- N  F& _) D- E! p# [7 N  M# C630973  SCM should see the net assignment made in CDNSIP for Power and Ground pins ; ?( n8 V3 M: U3 L6 i
631609  Clarify how to generate a cref.dat file in Cadence Help
! k; `, M; ^7 ?. L- C631697  Want to degass many shapes in succession with custom parameters
2 Z. R4 k$ W: ^" B" e5 e5 B632754  pspPN and lib_list should reflect location of new models in 16.2
8 A9 A+ j  K2 }633440  Sensitivity not varying components correctly " |1 k6 n% D# i; J9 P
633842  Add note to docs regarding padstack quickview
% u* R7 M# |: [3 c' \: U634350  Enhancement suggestions for pop up info boxes. 7 T( W% t7 }* e) G: l+ |
634877  Export netlist with properties changes scope from global to local
( u% g5 Z8 h8 C6 o# m; Q635118  SKILL variable to obtain list of Classes and user defined subclasses in a database , y6 e$ ^% E0 r
635233  Place hierarchical pin tool tip
5 K/ p8 u. x7 v, ~635543  Any command to get the current line/lock type information?
9 G* V, x! D0 W5 U8 y6 R; G- r635579  Enhancement for Structured format in parameter file
) M/ _8 T4 r* P: o636930  Die Export option to create symbol either from schematic or layout
* G4 ^' z  D: \) A637195  Allow for SKill access to backdrill info on padstacks 0 n; u  Z3 Z  m4 E0 i5 w
637768  Enhancement to assign different colors to different net based on a unique property + t- }* z( n) X# w) |+ r" M1 ^+ [
638455  Enhancement: Add some details regarding nomd.lib
/ F9 d: c, @) A& Y638581  ENH - Press ESC button Spreadsheet window disappear
# s; q9 c0 `% ], z3 p638622  Add note to CM Spacing Domain Region worksheets regarding shape2element clearance ) f7 ]; W" X9 p7 ~/ _8 c
638910  Enhancement to sort the list of available vias alphabetically in the via list ? 1 D  y  i3 e  R) A2 g
639630  Does the Net_Short property work with Modules? 3 [- P% x* A. e  R; [8 z
640262  Request object membership count in the status line and forms of CM.
: z; A; B( P/ q1 O8 y640280  Provide resizable windows in CM and other apps
% }1 b) `' s* F# K! B7 K2 _/ C; q4 @640668  File>Change Editor needs ability to go from GXL to Performance L or Design L.
* K/ ^2 {7 Y. o; A642095  Ability to disable the Pop-Up description of elements ! i# P6 y$ e2 ?: ~: e; i
642298  ENH: For license checkout detailed message 6 _$ X- S+ H: k0 a3 q! i
642422  After Copy parameters from one part to other in partmanager forgets previously highlighted
5 c4 v% V. j* z' }2 P1 ?line * W; S$ w# H8 D7 b4 k3 _3 b) l
642865  Allow format of hyperlinks in ptf files * H/ Q% D( `( O* z
642894  ERROR(SPCOCN-1993) is not documented anywhere in Cadence Help : i4 t( F2 ^! |! }1 X1 Y
643381  Add an option to ts2dml to allow user specified port ordering. 1 N+ b) b. _7 `2 H' ]5 q7 m4 X( F8 O
643390  Request for a switch or button that would allow Properties to be maintained during a shape 7 Y6 b4 C$ w6 Q1 j+ b' I
merge 7 ?( E% c. U& R( D1 w7 i" B% M
643625  Bond Wire export to DXF does not support WYSWYG
9 F0 |4 r( D, \4 B4 B643790  Include Associated Components in the Verilog netlist
& j7 V0 C: Z' V+ l9 n644216  Store Filter Row Data and Units Of Measurement in site-specific file. , b+ ]# t0 ~. p; k* H. n
644248  Need a better solution to identify and handle unstuffed components ! b. V! h; E/ g. g
644350  Incorrect upper/lower case for axlPadstackToDisk in Allegro SKILL reference manual 8 ~, F; z$ A) ^; w  a, w
646662  Enhancement to add feature to toggle on/off inter communication tool from within PCB
. O- |5 m; N( e; G' p4 s+ gEditor when using DE CIS. 3 Q2 F4 x& ]6 r, ^) o* z
646981  about the treatment of NO_GLOSS property in Missing Fillets Report
/ M+ [8 i. p: ]' `" Y  a647480  global setting for adrc settings in sip via techfile
( r# M9 }2 y' u. P! f$ G" ~647617  Degassing not suppressing shapes less than size specified
1 v, {9 Z( m5 c. L/ s/ L% v648210  Request for Working Layer (WL) model in all tier Allegro tools..
, G2 c+ l: ]' W2 c" H648218  must delete keyword "multiwire" from Doc
4 y# X* n6 X8 Y$ `; m648533  The cross probe highlighting between DEHDL and Allegro PCB Editor is not documented * E( H  |, f8 @1 ?, v" r
648801  Stream Out issue for SPACER
4 @, A* A" I  C: e9 n  h648930  If two PPT option set names match a given component which one will be used? ' x2 Q. Y& {$ I6 y# U
649603  about spara import : q4 i, L+ J9 x- v. h( V. o' a- M
649607  Management of SiP Technology File and Project Information
$ o( G. u6 K; M/ z649610  Management of Part Table (PTF) Files 8 N; K- K4 q' b1 h) x
649613  Management of Library Lists
2 q! N; X3 B( w, I1 x2 z2 ?651684  documentation improvement request on cross-probing in Capture to Allegro to Constraint / s; ~( J# e- a
Manager / Q/ U4 e3 M$ N6 M
652335  Tooltips clutter Place Part dialog.Option to switch it OF and ON
+ f4 @: e( M# M6 S2 G652511  Unplace Component command 7 {7 n% a( d0 ~% \- k" o
652547  Description of ForceDBArg1 should be added  to PSpice Users guide 652554  Enhancement request for Allegro to check the vias used to the allowable vias defined in
, @7 n8 E5 G+ y9 Q: U" `1 r! H8 mconstraint manager ' @6 J" c8 y. F5 s  n
652939  Is there a way to predefine the values for Sample Start Height and Sample Start Length in - C$ n# m% C/ v$ q$ T
Wire Profile Editor?
; _) U% `& |& }/ t' R, ~653027  Explicit RMB "Done" option is required in Part Developer symbol editor when editing text
: L: d5 U& `4 K653359  Setting the $PN to # does not set the pin numbers to invisible when part is sectioned using 3 U+ F4 Z. }( c5 _* i* [, `, C
the section command , N8 u4 [9 C% g" u3 z+ I- R
653420  Enhance ADRC rule for Acute Angle Merged Metal Check to work on a user defined
2 Z: F# G' M: U' p, }minimum constraint value
1 Y6 E! {6 _: L* O. X$ L! Q  N- x653471  Request for Die Text In Wizard option to Flip the DIE coordinates 3 k- o  y" ~. _+ c7 }5 l' I& z/ A
653825  sigxp_tier was not reset when installing a new product suite
6 G: B. S( q: h  r2 A' ^) T653902  Enhancement: Print Option? setting in Capture.ini file 5 P+ P  e/ }6 n' Q: O. v; {; W
657180  Enhancement: Tooltip for DRC markers
( C- t4 L# c. @( ^657187  SI model delete enhancement
+ {" S' O5 o, |# U: q3 m% N; n' M  U657189  SI Model assign enhancement #2
- M1 Q4 ^' {& k* S& y) |# |657501  Negative planes doesn't match with Film View
9 }8 t5 V, D3 X0 M& C0 X3 k& E659543  Need a Report to show which Die Pins have no bond wire attached ' q' M2 U; Q8 u, A9 H! H( P
659661  Function needs for setting the rotation angle in finger by group. 8 R' B2 R7 T* u+ e4 P* u0 M3 ?
661477  Color192 window sections to be resizable
) Q- x/ V) d9 L662215  Please add the function of renaming net by batch command.
: _+ T8 K' b2 M, o4 A/ M662325  Skill code example axlDBGetProperties.txt not correct
7 s3 a5 e1 z. r, b9 E% z1 R662982  When you edit shape, ministat should always enable shape
) i; V/ [" [: Q, g: @663260  Enhancement: ALG0051 message should be more specific
( F6 ~4 a9 w5 p663754  Enhancement to create Device file when saving dra file on opening another design
6 ]1 p* @; \2 g; W# y- v664240  Add CNVPATH in User Preferences to place default CNV files 5 g7 S! z, J3 L; F- F# l
665798  163BETA - provide graphical examples to show result of Flexible Shape Editor actions . y3 u7 U( Y3 X$ M* _7 T
666186  Enhancement FishEye functionality in Variant View Mode ! L8 S, c. ?6 Y: {1 T& T0 K5 y
666768  Temporary graphics for modules / groups do not reflect true size
$ z9 n: }* Y( C4 s666775  Update microvia to microvia DRC markings to avoid upper and lower case confusion
0 F% L6 p( \4 T8 P5 w: H1 F667773  Request for ability to set grid definition by entering simple formula
' \8 O6 \. K8 i. \6 g  B4 r668110  Customer wants to enter the value of radius when editing routes. & U* @3 J$ A0 k3 C6 N( ]
669373  Xnets are not formed correctly in CM. Up to 14 'extra' in a copy of the same design.
9 a# E- [, X( @5 \# P669380  Add options for ts2dml in MI 5 A: J. X1 ?! a7 @$ k$ Y, q
669798  Add all 5  Dyn_Thermal_Con_Type property options to Via_Array. ; o7 a6 j8 N% p( g+ V+ B: y- {+ ]
670775  Request to make the SKILL _axlSetDynamicsRotation and Mirror functions public
. F6 z% f+ S% M, T) x671194  Allegro not to crash when opening unsupported files
$ y; m/ t* \9 k+ Y+ _4 c671337  Request performance improvement to access DML libraries from SigXplorer or PCB SI. 0 O' T* G- S% F
671757  Handling of double quotes in HSPICE subckt. 5 T0 m" m4 r2 r& m6 u
672930  ERROR [DRC0039] Tap may not be connected with the bus Check Entire net 4 d6 Z1 _6 R! T% ^4 B" d
674666  Report the wirebonds XY coordinates 8 F; S1 `* `+ m1 M" S
675118  Cline change width command enhancement
1 u+ C3 i6 ?0 `; `7 A: q) R( m675151  Insert comment option for database elements 4 E# ?' M) z9 S. D6 o- q
675398  RF PCB setup should automatically point at the project file if Allegro is launched form a
. T& b9 ~, \0 `. }* C" D. s% @project manager
. z4 p/ |; t6 [2 p8 t675551  schematic to sip layout fail # l; h" c& _0 Z' G; N" p
676814  Signal Library command with Allegro performance license. / Z0 }- S# t! I: E: O" D+ Y! B
676906  Add switch -regenerate_xnets to the dbdoctor dUI
& G) a$ b- F% B: `. N! ~9 o677983  about setting of ibis2signoise option "-d" as default
! v$ I- y' o+ T! c678036  Request for a Physical design compare.
& X& S  i6 }" x8 M- o$ j+ \678798  Identify DC nets command doesn't remove the RATSNEST_SCHEDULE 4 ]/ }9 {8 G0 x2 d- s* B
679926  Testprep fails with no route keepin. Message in testprep.log ambigious at best
5 N2 e+ p: n* p% U' T3 p9 l680586  Explanation of functions and macros in online help % I1 B; ?, q$ G: ], ~
682098  Color, font, Text Label in PSpice Probe Window
8 U7 M) O! o* I& R& y682695  Offset is outside or on pad edge. DEFAULT INTERNAL: REGULAR-PAD message needs
/ \" p* W9 L+ o; n# J- x9 ]rephrased ) `; v, y+ @# d0 t
682865  When using PTC format IDF files don't use forward slashes. ( T1 W3 ~) w+ X( }2 m
684409  Add info for non availability of SIGXP on OrCAD Demo version
  [8 \+ D  ], y% G" }684713  pin_count view needed for packages 7 L9 I4 _0 Z( ~5 ^9 a* y' Q0 A9 h
684796  do not delete all vias with DRC for via array 686103  Replace vias evenly spaced apart 8 f* k7 z; m* E- h& r4 Z
686112  Add Connect and Slide keeps cline length
( }: [* U1 ^& e& W; i) R; I7 ^686122  Select objects by polygon
2 D. s4 w, j" K6 m8 l/ L' T. q687155  License for batch signoise command
+ B8 _8 p$ S  l: G8 m687187  BGA Full stagger matrix wizard generation ' |# e' a* M8 N6 E. Y9 v# [5 W4 D
687201  Improvement in Find feature / \# h  n' \& @% M( F4 Z7 l+ m1 S5 D
687685  Documentation of new properties in Variables block 7 d. F. {. A- n( C! ~4 e0 z; _# |
688047  Include blank space in pin name as the illegal character in PDV user guide & t5 x+ n' q8 w1 B3 Q
688830  renaming feature discrete library translator
, A, c& B/ L( X. m( v$ J4 x689720  Need the ability to re-center Vis's in center of Pins when a Die is changed.
' }- C( }! E& x! n7 H- C695957  master.tag generated from the table design needs to contain the verilog representation of the
' a8 e' D% d; w  X1 z8 U% tsch. ! N  _. P' M1 P; t( K' j
696661  Add ability in Offset Via Generator to add vias per a given Net 5 r" T+ j, D8 _, f/ [! Q7 S, \
696812  provide description for axlCnsPurgeAll() skill function in doc 9 Q2 }4 K/ V, _3 V: [! h
697824  Components not installed of variant design should not be extracted into SigXplorer. 6 J# H$ V. S6 Q& @) ]7 t# A- R
698097  Color Dialog form (color192) does not resize correctly
& @; `1 ~, T- n2 g( D" ?- u. F- t; M" X* G700262  Unable to add Signal Library Model paths in the Allegro Physical Viewer (part of the
! R* f. \  T3 N' [& t, v  MAllegro PCB SI -L tool)
% {0 L9 {1 g& T# f- f700712  Defined pin locations are not used when using Die Text-in Wizard with default option
- l$ l7 Y3 r$ \/ l' U1 ~Center pins on symbol origin
# g) z3 j% S: ~: o1 v701514  axlCNSGetSpacing online documentation enhancement request regarding "bbvia_gap"
& _# c# |. _4 C; s+ u0 e701810  Document what all database sources are supported by Capture CIS
: |* K# ]( g. ?2 D; O: c; K9 N702190  Request support of Windows 2008 Server Editions. 6 S0 R/ f" A- D  N+ t
702613  Request SaveRefdesModelAssignments support the include original model path option.
0 ~8 [4 l0 p: X; D2 ]! l703905  Need Hot Fix number Info on Help >> About
9 v! h) U# s: q! ?6 {: K704594  Update symbol removes the text present on Package_Geometry/Silkscreen 4 s4 u$ d3 o1 {
704899  Split Bundle Methodology Should Include a Next Function & \3 D2 s6 W1 T, [* o; _
704904  via matrix should be available in Allegro L and OrCAD PCB Designer
! K" _3 U- V3 |. u. x705601  Please make listnindex a public Skill command   O% N5 v/ r( ~
705615  During Updating Symbol the text location and size are changed so Reset Text location is
+ [; L3 W$ @! T  `: q- `0 V/ Kconfusing ) B* F6 K( y% p/ y
706165  idf import fails to expand drawing enough to accept text.
/ V- ]8 p4 U$ R+ R: V: X' Y706457  Change type of the fourth optional argument for Mirror in axlGeoRotatePt to boolean
& @; F0 p2 `3 Y+ F& X) t706463  Add optional Character in the starting of each line of the file created by axlLogHeader ) X8 w' ^% Z$ L, f
706787  Fillet should remain when user slide the segment far from pin/via.
: A3 s. O7 Z7 z% z& D; U709119  Requesting a pull down menu with "Comp" and "Net" to be added in the Offset Via
' h+ e) b$ v1 `9 ?3 qGenerator
8 m1 \& |8 o& x! a) d1 T/ h8 F7 G  f711837  remove the comma from the image of grid value separator
' y9 p% v6 N1 M& l- x" R714840  Enhancement: Anti-etch can be recognized as Void element. + r$ n4 E1 X' f  ~( J8 P
715454  Option to configure Design Entry HDL for Cadence Help 6 Q; _, G$ {$ E, ^6 j4 ~" W
715713  Enhancement for Wire Short Check during move feature
# e  v9 j7 R& z. P9 j% I716671  About the log file of the na2 interface.
# Q+ @6 t4 Y4 L, c9 X; M4 l717722  Pad designer  File > save as should have recent file name in file field
" p9 y2 y4 l  N0 a$ C$ @718431  Enhancement request to have DRC checks on negative layers.
# v. l2 Q, S; ?( I9 w0 e8 c- h719050  Log file should contain username date and time while creating or saving .DRA file ! r1 r' o4 o5 a0 C) n
719514  Request length column be added to the Dangling Line Report ) Q5 g) J& {+ Z8 Z
720297  about "rip up thermal-relief clines" 5 o# F8 m1 }% e: D! }
722346  DRC checks for mismatches in labeling Net ) V) @/ ?- V; ?/ R5 G
723661  Add *.pad in the File of type drop down menu when executing QVUpdate 5 ]; [" n3 [8 y& _8 Y+ c
724832  Tackpoint move on a non standard wire bond -> *Error* difference: can't handle (2043.0 - + M! a9 o# S( E& j) @
nil) 8 B/ D8 @2 y: w! E5 x- X
726057  Request incremental DRC update when enabling DFA constraints.
$ ~& i- c! O/ V. C9 v$ E' g5 t728908  Add Color View Save and Load in Symbol Editor
) Q6 |" a# |* v: \729947  User would like a metal usage report
' S" j" M2 c8 a8 @1 D
9 M) b/ V. f) N 2 |+ [( k& N+ F7 |3 p) ?
+ |6 o, ~5 s' O3 }' p
Bug CCRs:
6 z0 a+ x/ k: ]+ i" p$ G) Z
! k3 x# U8 W) ^! d6 G" dCCR ID  Description + A* Z# q0 O2 T  ?
10116  Add Intersheet references does not work in Complex Hierarchy
, Q1 a, b4 r; l8 p8 ~11833  Junction not automatically placed when it should be.
! p  O" F4 H4 i! a1 v& Y! V16310  Simple hierarchy, intersheet refs not refering to H-block
1 C$ e  ^! l" N" H- M19343  Request for intersheet reference to show grid reference zone
4 r9 c& r6 G- I- D/ H! S22424  Intersheet refs wont work on imported off-page connectors , [7 x$ Y- U% r1 V. ~. }
34275  Ibis2signoise fails with legal characters in file 7 ?. p4 \/ x7 p
85735  Cref annotations of the P_ID+00 Bus were missing + k' Y5 a, X. l1 W6 l5 k9 d7 ?  _
118279  PSpice command line options problem 2 A$ ^5 m, B2 d/ f* d$ R
134692  DDB_WARN: POWER_GROUP prop. not allowed wrongly coming
8 h8 I0 ]0 K0 t& Q) E. l& w136260  Problem with netlisting the design in PSpice 6 B9 U! L% M9 ^; U" y* H3 N
199343  Stackup-Aware SigXplorer ' z' P% r: m) p2 K: I2 G
207620  Part in MISC2.OLB has incorrect pin out & R4 Z6 ?. l# S0 v) Y' g- T9 A
270347  Changes to AXL SKILL must be Documented.
4 h3 s8 _+ b6 p4 I, X3 p283839  lm117 dropout voltage is too large
4 `8 g+ n" h( W$ _3 r6 O% _296826  Variant view displays library property
- U, K0 H, n! \' q299384  Part rotation resets the text to default position 4 _4 G1 q# K4 h0 d* t
328647  Replace Cache takes time for network libraries / N- `# Y2 T) D" e$ A
340323  Dynamic shapes need same tweaks in 15.7 as in 15.5.1 to fill # z' i) ^2 G2 A6 M) w
341035  Dynamic shape fails to fill in design that has cline arcs / M$ c- o4 M' n7 F" L( |" ~
390692  Via not getting transferred through the Area Constraint from Allegro to Specctra
' |  z# q: |, \- i0 Y405611  Environment variable for SIGNAL_INSTALL_DIR is resolved. ) k0 T1 `+ q& y7 G
428261  spaces at end of pin name Could not create new pin inst library correction utility 1 R. S1 a+ }( _
436908  The color dialog window will loose the vertical scroll bar after being minimized. & U, ~1 I" P' K+ `" E+ V) I7 V
437369  Menu selection of Export > Libraries fails to issue the dlib command.
' Z2 `! i& V  p+ `( F' Q462783  Busname is too long 2 Q/ l# U, c3 G9 r' `
495671  Unable to add the signal stubs due to the overlap between SIG_NAME & VALUE
6 t; V) {: m+ d3 b" g# VProps.
$ ]) \) m! a5 z) q! ]2 y509393  NC drill legend copies null nc_param.txt to current dir. % j: n% y! \9 l+ D
512809  Window Prt.part.ptf shrinks by 30% and I have to maximize it.
: I1 X# B( g, j& Z520802  Global Navigate Zoom to Object needs to remember last setting   l. h' S4 d  |" n  y# H* o" O
528686  During text edit the cursor overlaps a letter rather than in between
6 i" E7 B( F& @& a531555  The diode BAV99 from library works inverted in compare with the graphical ( U* Y1 z4 d0 g* W. E* T
representation. ' m0 D# f" x3 }- w# ~% @! k$ R3 K
532603  Specifying TC1 and TC2 properties does not seem to have effect
3 F5 j4 v: S, I: n) M547339  CM-SigXplorer extraction shows different topology in DE HDL vs PCB Editor # z& I' S/ C! U% M
548143  Dynamic shape on Etch TOP will not void properly. $ S, t0 w5 e! q) [6 h
550657  Importing registries do not setup printers from MWcontrol * y7 j( X5 `* w% _1 R
552227  about die export padstack  layer mapping 5 u2 i5 I  g, d4 x" V7 E9 e
553035  Cref Synonym and Netsbypage reports do not match netlist 0 B4 L/ q5 d) C' b0 ]2 H
557660  Incorrect value for I_sinusoidal of pspice_elem
. r5 [4 b3 C# \558164  All variants are affected by function regardless of being called for , v# s: n. w6 z' Z* ?
558692  Memory leak problem in loading marker files
$ e% G. z( n' [1 Y$ A0 X# L2 q5 v565681  Filling in values in CM by using ctrl+c,ctrl+v and arrow keys is not working as it
( j- K+ n% V4 I7 J( S8 `4 P" ishould.
; \( W  h# O4 r6 x7 w; E567606  PDV selecting pins in symbol editor shows pins off grid during move + x+ C4 H+ b5 c5 r! S
568049  Genview crashes 2 W7 j) B( u4 M- x
575353  Large box displayed with place manual-h and no RefDes variable set
) ^2 f- b3 ^) {581848  not able to edit Padstack Boundary - ]! s1 ~7 H5 z3 D' c) w7 _
591847  Add Intersheet References does not work on simple H design.
$ v' A' A% d' H4 ?592381  Physical Min/Max line width values not check on internal rows or forms. 8 g1 \2 x: @- R1 Q  X
593076  Cannot redisplay an invisible OFFPAGE connector's name . l. b) T' P# t- V1 Q0 X8 J+ z
598038  Detail button of Markers window with 16.01 0 \$ @9 }* W9 U: i
600967  wrong order of nodes in PSpiceTemplate for part AD8138/AD
+ u# |/ j/ y# k5 C601415  Allegro Design Entry Tutorial corrections. 7 a. G7 c7 @+ }: u+ q" g
601531  When using the place manual command and rotating part a ghost image is left behind 603181  Formula to calculate the Actual Temperature for Smoke is incorrect.
0 D: A2 M+ C+ v# P$ \9 V604965  need to document how tcl cmd addComponent handles property values with spaces
. N, n2 a/ d$ ?' ]$ }605843  Aliased nets do not fully dehighlight when next net is highlighted / J5 a- o' h. s5 m
606493  Targeted nets are not remaining targets
% J' Z" o8 p2 c7 v# u4 }  a* n+ _608150  TestPrep generation is creating DRC errors ) ~3 a* r% K* W2 l* G
608787  Missing Constraints Report
6 k# G- n* ?  F$ {7 `& ]: o608942  PDF Publisher output misaligns text in tables 8 U, [3 o' r" D+ I  _6 a* y5 S
612511  Error in Flow Tutorial regarding checking default user units 1 J8 Y8 m  s) X+ a
612982  VLIM model giving error that line is too long
( d8 K" k2 S% O% W2 D613194  Adding wire bonds with current selection does not yield DRC's, mismatching Allow
& C. d0 S. ?" Q3 U# a3 fDRC violations option. * G0 R5 X! |9 ?& G* F* v3 X" z& h! W5 `
613738  Variant BOM report lists identical parts in separate lines due to POWER_GROUP
9 k+ t- Y" a7 S! x# i; @) l0 g617146  Symbol fails to place through Component Browser
; {4 P8 U/ r2 e! F! @% _4 ^) z617327  Change root operation results in SCM crash
( N' h/ m. O0 P2 w3 b  V/ l617784  Trying to open page 2 of the design Capture crashes
, \  z6 {3 }/ u! B6 p8 K618150  Property Editor Functionality
0 u7 |, N, ^* h2 u; S0 b  |8 W4 E618617  Enabling strokes requires checking/unchecking options boxes ! O9 w8 Y" r( g' q
618771  PDV error SPLBPD-382 when importing from APD. : l$ o, O# s2 o" J
619053  Diff Pair problem with creating them in DEHDL. ) o; k( p" K  D4 L$ J, |# Y* f
619849  Hierarchical Blocks Loosing reference
$ v% Q9 l0 x" d620001  Measurement's Maximum range calculation is not correct ) T: w/ p' L% N3 y7 ?5 K9 @- v
620343  Bogus error during schematic write
5 w3 ?' {# r8 A0 K6 S, c& c620826  Changing the units of dimensions does not work " {2 `% ?1 t- \/ r
621072  Capture CIS Crash while configuring Database 3 L' L$ N/ K8 a  T
621163  Ambiguity about the how is the ?start of the wire" defined in CDNSIP for ADRC Wire
$ G( t7 B1 q8 ^* vto bondfinger optical short
5 t7 D) l) j' F% j/ B622263  Drill Customization sort order for oval oblong slots should account for Size Y 2 j6 E1 n& I# s
622583  Allegro produces erroneous error msg - symbol not found when the placebound is too
, o* E6 I! U8 o1 {large for the board. 8 W1 l# f; Q- C  J6 o
622692  Why is VGSR negative for N-channel MOSFETs
# u8 W3 f# [0 u8 G& X0 q& H% w: j624378  Device file content conflict ! c1 q9 i4 K& n4 V- I
624492  Model Editor finds the wrong model definition for BAV99 6 h5 x7 g7 E& Y' j4 f! ^0 _
625462  Symbol pins Property are lost when once stretched . _. W6 h9 U# z" [$ w
625519  hspice_mt is not used in Channel Analysis simulation
5 B1 w* I. q& q% P% I626674  Allegro CDS_SITE setting don't appear to match documentation
* {+ X- U# G; P9 w627018  Find Net in instance mode displays twice " N  Q* u  N" N  @
627864  EDIF c2esch crashes $ w6 s' W0 V6 [! M
628077  Degas not voiding correctly
5 t& D  A5 o# S& T628265  no "Unused Blind/Buried Via"Report in APD products
0 c8 t7 y* \; ^+ Q5 a( ^; f628845  Markers> Packager menu is unselectable even after pxl.mkr is created.
5 @) W% O; Z9 W1 d9 }* v631344  Mouse Wheel Scroll misses the "along with the Control Button"
' w" l$ k. \0 x$ s631792  Design Compare not working for OrCAD PCB Designer.
1 A7 v3 _8 m0 `% M0 N1 ]8 U631910  Capture hangs when working with search option # z: }4 B$ V& t) L/ k* L7 b
633084  controlfile for OrCAD installation does not work with PO100E and PO200E
. ]6 I+ S; p6 N- g( G633086  Generate Part for Pspice Model is incorrect
0 i) V; e4 m+ t8 R4 v633130  The Verilog netlis is wrong
  e8 K9 B' U& {/ w633223  Running skill from a HDL script causes segmentation fault. 8 [1 G8 }/ N  p9 r9 X
633473  INPUT_SCRIPT inconsistency when removed from .cpm file & t( f( s; F4 ^, ~
634075  draw_etch_outline doesn't work for circular shape/arcs
  @9 ~% ]* B/ C& O8 L8 t7 f635779  Allegro OpenGL distorting text at certain zoom levels 8 ]" e% D  @' s# O: S2 f% B5 y
636156  Unable to convert SDT Schematic to Capture Design   Q9 L; S& k( k/ O. p: t  y
636215  Allegro documentation for Export Parameters is incorrect 4 ?9 F, x  U% R5 J6 G! U. Q+ k& F
636585  Rotating components in Capture reset property position   v1 j! i( L  O# t2 n1 i
636688  Signal Model Assignment UI and Find filter association is broken
$ M4 K0 M, S6 D: u0 Z636819  Documentation wrongly indicates that DFA Analysis in unavailable in XL
4 k0 |/ g# [( M/ ~7 F6 E& F& ]637379  No column for ROOM shown in Constraint Manager
+ c6 ~5 I- I) G; U638140  Intersheet References not offsetting relative to Port
; W5 \, q! \( d( U+ C/ U0 S2 L638670  Testprep parameters - padstack selections - Bottom Side replacement text not entirely
( \; B: a$ c. Tvisible. 638987  Change command hangs on customer?s database
! {5 G# J* T* D& I. j, C- [639052  Database Objects Preventing Layer From Being Deleted report fails to run   j1 J0 L2 C& t2 P+ Z; k2 q% g
639685  Capture crash while deleting a Hierarchical Port from the Design ) W; T8 g- b! N0 V$ F0 b. Z
639698  HOME variable defined with %USERNAME% doesn't use value of variable. ' D/ z- d1 O# c8 Q( M
639829  After setting Zoom key(F10) to a new alias Tool Tip is missing the key number
6 C4 M1 m0 ?3 l1 K1 l2 I640127  Correct IDF documentation regarding UNOWNED objects
( n9 I3 E& @: i' N4 `5 Y640293  performance issues with scm and large pin count devices . E% W! V1 N: s
640314  The number of menus written in DE-HDL UserGuide is untrue for Unix/Linux users. - t, a2 R1 P+ H9 u- O8 o
641503  Stop running the VAN check on a PLUMBING body symbol in PDV
1 i, u& r/ N+ Y! Q  y6 N641676  Incorrect link to assign refdes help
1 d# ?9 U: @, v642053  Drag Connected Objects icon is always display as on
& e* w1 ^% I) m. t642299  Switch the windows mode by set command ) {  j6 V( t( H0 c
642436  Save As symbol in part editor is not working fine & x1 U, o5 ^9 S% W& X& G% b
642713  Materials are not refreshed when material name have only numbers. 0 k( {3 c- C) I1 x
642873  Dynamic shapes out of date message refers to Setup Drawing Options " I8 U( _, r6 d5 u8 K# k
643721  Attributes with Null values in symbol.css files are removed when saved in PDV 6 r4 z6 h" `$ n; j% _! j6 T0 G6 Y
643949  Can not create Region-Class-Class for same net class. ) n1 N3 q( n; F2 }: r
644016  APD crashes when creating a tile from LEF file
  ^: @1 }. A/ y- k7 x9 Q644733  Import reference text file gives incorrect results - t3 ?6 F- `" Y. [& C
644879  Change forms to enforce naming of lib.defs file
4 M9 q4 N9 S: d9 d/ t3 F# B645046  SG1525A PWM model is reporting unmodel pins and producing incorrect results
5 m4 G. [2 S) l  ?( N6 _: s645427  The save button is not enabled on changing the line width
" X, ^( s5 d; U$ n% L4 X645996  con2con fails to parse ppt file correctly
1 ^4 T8 p. N# V) ~8 |# f4 D) m646175  Please modify the limit length of "Allegro PCB Editor Limits" correctly.
6 k5 G: x. h) L0 h; A647555  Drill Customization text Non-standard Drill is not readable.
1 `0 [. b$ m* c, ?1 f647628  Annotate Type should be removed from PPT Option set files and documentation
% K) i) x+ [, ?$ D8 F# o6 h648443  Launching SCM without a license is not reported in debug.log
, [% u/ r! J' g% ]1 E649166  Capture CIS crashes doing Place Database Part with non-admin User rights " w) W$ W: @# k( \  n  b
649222  Silent install adds extra License Server to CDS_LIC_FILE on the client ) Z2 T1 }) @* {. I+ S
649570  PSpice COM Wrapper error while opening Capture PSpice project.
2 c  k" N! S: s: ], ]+ ?4 d650558  Die Pad layer changed after refresh padstack
, ?! R' Y( B& L0 y1 b# j650997  Incorrect Pin Shape in CIS Explorer Footprint window
- a, S" R% l! Y651000  "Wire length over parent die" violation is incorrect.   ?) n3 s* u" ~) O  ?
651153  Results for imported CSV inconsistent in PDV 5 w+ Y: U- e) {, m) v
651521  Resizing the display color visibility dialog box corrupts the display
% w" r5 m  K: J, [4 O* Z. m: [651526  Parts are missing in a advance analysis library list document and font size issue
8 Z& {* Q* K% r9 u& N0 _651532  Scroll bars disappear after minimizing the color visibility form & t( t# Y* K+ b
652050  Append waveform does not work in 16.2 for .dat files created in previous release with
* Z8 h* e! ^( }6 Ximport text format : ]" |4 f' U* Y8 [; n. j
652904  significantly low performance issues when using edit interface to delete ports of block 1 M' c  K+ X( H. Y: L3 E
653067  Incorrect warning SPMHNI-198 - Pin name is not legal and will be replaced by `$#? % F# y( S3 z7 c  ]$ \1 g
653784  Off-page connector name change to internal starting like "I12345555"
  I, n9 d) p" F" z4 }: N) X$ l654580  Save As should update lib.defs without executing the edit die operation 0 c1 q* S% L& t6 p: M4 V" T: n+ k' z
656282  BGA Generator adds outline and RefDes to wrong subclass
1 {5 a7 C! E$ d6 Z656723  visibility of clines in 3d viewer needs ALL instead of just CON field in layers
2 e9 \3 s) K. U657836  Text crop on User Preferences Editor form 9 x0 Y* T. |4 S; C+ Y
658347  Rule Continuous Soldermask Coverage Check should not work on Cline Segments + f& J5 c+ x: h' g6 \* D2 y6 j
659437  Move group fails to display anything with Open GL enabled.
9 v) @$ _2 u6 [; n- B: `1 Y660937  Import techfile fails with etch on layer yet layer has no etch
0 L4 A" X5 e5 ?" k661369  Importing design fails with the SPCOCN-1158 error when DBL_STR_LEN 'ON'
7 W7 y( q" S3 l0 {661754  Hyperlink publish pdf to correct page but wrong grid location
/ J* m3 B3 f& {" `6 C7 J* [' B662622  Export Physical reports error Output Layout Filename contains space
" O4 R9 f" I% B% }# T2 c662918  Skill code example for axlReportRegister does not work
7 L" k. ]; b2 D662971  Moving Bondwires disconnect bondfingers.
7 J0 T  K7 J8 Q& {7 K5 f4 j663088  Cannot add connect to a C-line in Etch Edit Mode & t, W: B' b, P, D; u
663220  IMPORT_HFS_HARDSEC_ON_SWAP_PINS directive causes error on save in 9 I: c- G8 k6 a2 R1 I+ X
DEHDL 0 R4 W3 s+ j  V/ f# d
663726  ?Each? menu under RefDes is missing in BOM HDL user guide
# T1 W1 V8 n- K9 J- T; j664764  Material changes when layer type is changed 664900  Project manager User Preferences Editor form has text crop. ! [& {8 T& V7 i4 }+ R; o& H$ z$ d
665236  Unable to import a Quartus-II version 9.0 pin file.
, c3 L0 ?' M1 r665389  Spread between voids not working for customer design 5 P" H5 N9 {7 M: W
665413  In File> "Import and Export"> "Import-ECO pin table" the NEXT button does nothing.
( V, N5 w3 S- y4 ^# E665451  Import - Part logic - information popup window has incorrect user preferences Editor
/ q# ^8 C3 m% M4 a' DCategory ; H- ?8 W- j) u2 {# E5 @; \/ m
665661  Wirebond Die Escape Generator failed to generate Clines
; t1 q5 ?6 H$ Y( D0 c# d666099  Mandating at least one symbol with sizable pins for using size..1(not for size-1..0) 4 L, B- l5 o2 }0 `# u* w2 I. x
SPLBPD-310/SPLBPD-309 on reload
1 X0 O8 F" w5 u- `3 S. P2 @666667  Relational Table View Browsing Issue 6 _( i! K  Z3 k0 Y; d. m% a
667286  import IFF No Component Shape Line Via found in IFF file.
" C8 [8 u! ^3 M) r8 U; f; N667751  db(v(out)) and vdb(out) gives different results for FFT
3 H1 W2 v* z0 n) A6 d$ A668080  Improve handling of curved routes
* {' X6 t2 j; z0 N% y7 ~4 }668081  Capture Crash during Edit options
  ^+ t3 a+ {. s2 w: O668393  Dielectric constant or loss tangent values do not update when changing conductor " \- W. [  Z) m5 f1 o6 {5 L) }
668785  Capture not displaying variant values for Uppercase Display props % u! d$ D9 `! r) W( P/ |$ P5 _( k7 u
668799  Placing specific part crashes OrCAD Capture
7 @. s; \* ^2 `+ M& g+ ?  B668876  Text on the Add button is crop on the Edit via list form.
1 U5 V' Q. t3 I$ J, e* a668892  Incorrect Parallel Length data in parallelism report + @0 ?. s& q5 H% t7 P
669206  Parallelism rule causing significant performance issues during DRC update
: B1 ~+ `0 ^6 k1 \8 [4 A669238  Unable to use permanent highlighting for groups in version 16.x
3 N5 D2 M  Z% j* Z1 a5 Z669323  Allegro PCB SI User Guide Doc page 229 ignoring vias needs to be updated ' v. c8 ^, q" v( J, y& x3 b; J
669336  Error in documentation of DE HDL Reference Guide
0 h  w2 O6 x1 h) V. @4 E670874  getVersion() function not reporting tool version 7 ]2 w2 e9 b) D* f
671811  Allegro extracta fails with more than 10 output files / }2 ?9 a! }& y) r9 x
672420  User defined property added to component instance is a function property in Allegro
7 \/ B, _2 N: w672614  translator converts the symbol "\"  in the original Spice model to "[url=]\\\\[/url]" ( M: i# d* A6 \" V* r
672615  Translator generates 6 external nodes should only have up to 5 nodes
! u0 {8 K9 t+ N' X1 Z672618  Translator generates statement in the dml file: Language=hspice causing Spectre run
6 D7 @" `$ a+ h& F, Werrors
' k/ z/ y$ h, e6 |672715  Steam_out takes a long time and then fails but the .log file reports a successful export
2 E+ J7 u% V2 h- R2 v; m673279  Same characters are listed as both valid and invalid in naming rules. - b  [7 l" j6 P) ]9 o5 |2 T
673410  search by net name is finding electrical % q5 i5 r9 t  ^% A# `# K9 W
674058  Incorrect Variant Report , \; G0 |' ]6 ^+ U( i: x
674291  Library Explorer fails to start and I receive a 'Runtime Error!' pop-up 2 e4 z0 h+ u$ |2 x. r# e" g
674555  If the DSN filename contains spaces, autobackup will not write any DBK files to , K& L% M' A8 \% i1 R
675192  Adding a second BGA caused dsa_api.c to crash
$ H' M! |; {6 E  O9 i$ g- U; V675231  SiP Layout doesn't handle ! characters in port names from Verilog and OpenAccess. 0 t; f+ t/ E/ Y, b; ~
675562  axlWindowFit() documentation needs to be changed.
/ X/ N$ n; `7 T+ I675783  SiP Wirebond moving a BF sometimes results in the BF placement on the guideline to 4 p- U5 \: C2 x; U) h
become unplaced from alignment option
9 W' @: k! U& P  E. x* [3 V% V676201  Cross section impedance not calculating with single license : J4 Z9 f4 \, G
676601  behavior of launch product from library manager & A  ]1 k- A" x% {" P9 S: w! W
677582  mirror of die component on sip designs 4 [  t& i$ |$ _1 C" a
678013  Error: Symbol not found, though symbol is mapped in psmpath
& w: E( q: F! ]$ @2 M# C8 b678427  repeatedly placed symbols has strange instance name 2 T% K* Z3 m/ m( ^
678538  Why derive database does not transfer the Schematic Part property to CIS 9 X, _1 x/ M1 k+ A
678814  Spin a temp group will not rotate the symbol
3 z; |& @9 g/ e' p4 h678851  Difference in lengths in 16.01 and 16.2 % X. l/ f' z  P; _
678884  dbdoctor fixes corruption and then it's reintroduced
% ^8 z2 U  p3 I679224  dbdoctor states it fixes an error but the error returns
0 {; _* I  l& D+ L; T679960  Capture crashes from diff pair setup menu . M0 l: E8 K1 t4 b1 u& m7 l; F: ^: u& n
680565  Capture dsn files are not properly associated during install 5 q8 d% o- y, @* J# \
681197  Report generator Hangs Up Allegro PCB Editor
/ S( _' @/ u& q! H1 y( W682135  Justification of $PN placeholders not working in 16.2 release , h6 I, C% P# H2 S! H
682204  Cdsserv.exe and cdsqmgr.exe crashes using 16.2 release on Windows
1 k1 u8 ?0 {  j7 V! D3 v( v& Y# ]682331  Incorrect reference to the middle mouse button. 2 W- t9 c1 b' x& E/ s5 N; }
683146  export variant path appears wrong in output folder while two DSN are open % X2 v5 B% p% M7 {: Q. E- R7 |7 G
simultaneously 683182  DRC0037 shows incorrect Alternate Net Alias.
4 x% F% h7 q$ f+ S$ _683379  ERROR in Measurement ConversionGain_XRange 5 @! ~( h( {) c0 t7 u) S
684180  Sizable pins and vector pins cannot reside together in a component.
7 _3 k1 T. P) B9 s2 ^$ {684661  via array created wrong results + R6 H) e+ r4 Y. C
684700  via array can not be placed on both sides of the cline , z* b9 H% f: G  H# z
684912  16.2 documentation is incorrect for axlDeleteFillet $ Z) h4 z/ E' G& O5 B6 u
684915  Incorrect mention of creating graphics template in the PDV user guide
8 y: g7 J# t+ q" t# k. c6 \% n685685  When the customer tried to merge shapes, they disappeared and  do not merge. ) k) V% i3 F2 z4 m7 g
686338  ERROR #8012 Database Operation Failed with MS SQL database 7 i) ~" I, t! t7 _% e
686560  Changing pin group property after pin swap resets pin numbers % d( k% p* R/ w6 v* U$ k: P/ M
686736  Load property does not propagate to the associated MECH part
& M$ `# J) k  g6 T4 Z: i, j687008  ERROR 8020 after removing Place Icon , m& ~9 S! k% |, i) B
687074  Part disappears when you open it + J# u* n6 j- \5 s" p0 S
687354  Not able to create allegro netlist 228 ERROR(SPCODD-228): Cannot package & M0 c9 ^- O5 _  b) e  |7 R
687385  Publish PDF outputs the net name (with underscore) overlaps with wire. # P( J* K( V! k7 l/ b' l5 O
687708  Smoke deration calculations for Capacitor : o9 M8 v. D8 \0 O0 |& i/ m
687715  Getting Warning TJL will not be smoke checked ) w0 \  \! H" ^3 _
688606  Inconsistency in synchronization between bias display and icon ; L( e9 P; n( w. m
689542  Comma in ESpice model name causes simulation failure ' U. o" C/ F# L9 x2 ~& X& p
690112  Ignored nets are displayed in simulated crosstalk worksheet in CM
  R; r; z: }; ?4 d! c3 k1 Q2 a2 E% M691668  Stimulus editor hangs on doing change type
- D0 J( c# \( |! V) S( [% C3 O691740  crash when setting coincident uvias in CM beta testing 16.3 0 ]$ s  f( @/ u
694139  Case difference of net and bus while generating FPGA netlist
; @& k; _' m+ j# L2 O; ]% V% q2 a0 X694716  Waveforms are flat when using IO b-element in HSpice
: u3 i& ]4 j2 K- ]& J695109  Incorrect Diff-pair topology extracted by Paksi-E field solver ( ~$ X' }* N' p1 Z" i
695431  csv2ptf fails without providing any error message 8 N, i/ r& g& u' w
696273  Shape disappears when updated in CDNSIP 16.01 and not following the constraints
- w  w5 p, t! n( i  E; ~' ^* V696534  Pin Visibility check box doesn't work while creating part from spreadsheet editor 9 W+ l8 E& W' a9 N
698494  Shape not getting filled correctly
' r7 F7 _- A- ^& m700160  Error: TVCurve must start at time zero .
( w: S8 T1 b0 |' ~) F+ m7 r700644  Allegro Crashes on doing Zoom In 8 Y  B8 @5 b( U- l. J
700725  Create Fanout with Via structure add structure from Top to Int. for bottom pins
6 O( D- s' Y* `3 Y/ ?" j  `$ i! h701128  Inconsistent warning message : TBreak (Tknee)is less than Simulation Temperature
$ e. o4 W* u/ Z5 J3 T" T702557  Incorrect Behavior with FSP 2 FPGA Option License 4 S. r  o' W& t
703324  Cross probing board DRC objects to CM DRC spreadsheet fails to zoom in + f3 d1 x. i- c( J
704268  remove ARC and TOGGLE rmb options when in add rectangle or add circle command , b( r; k% k7 W7 T% I, B5 Z
704317  Capture crash when deleting schematic folder
$ {# H9 T( _5 n$ e704475  Allegro SI change editor to Allegro PCB XL causes menu problems
% u- l. \& R  V& p705902  ERROR(SPMHUT-144): Illegal arc specification error when Run DBDoctor : W( P8 t% q( ~9 A- w0 G
705903  Cannot remove a matrix view after modifying the connections " i- ]/ m0 e5 @  S* W* m
706169  IDF in error has spelling mistake # P$ A4 r. S1 g: q! w
706613  Diff pair is not extracting properly through design link.
" x% g. w5 x6 A: p9 N- D706729  Import properties fails with ERROR [IMP0020]
! m7 G% n$ B! I. @' ^: `708134  Place > Manually command menus not refreshing the Placement list
2 U: Z& i+ ]/ W; P$ f/ P708145  Creating a netlist with Rev. 57AQ is not formatting correctly
2 z+ ~& c" B8 J; _1 d; `3 T708634  Shapes getting incorrectly displayed in 16.2 1 ]2 k0 W3 h# [0 ^/ N- B
710279  ERROR 8020# Place component operation failed.
1 {; `6 ?0 K, ^: t710859  Unable to create Diff Pair from Autosetup
1 L( p$ s4 }: V& f/ t711739  selecting one component/symbol of class IC can move unrelated component due to
$ ?( J5 {! \( ?/ S9 _9 Zincorrect group membership. $ X; M( U; s! C
712299  Internal application error while creating new design * v2 G- j. ~% W% Z, w* Y
712898  Netrev should not read PARENT_PPT_PART property value while importing the logic,
  g, \- ]! R. Z& [  S+ q% odue to which import logic fails
" X. a& z! V$ y+ v; F, x713465  Problems with dynamic shape creation over routed full-arcs diffpairs
" |' ?( q4 ~$ ?. v+ W713480  Display issue when adding a custom property to the first bit of the bus. 6 D0 J, }! j5 ]: j# ~
714072  Error while linking database part
* k1 ]. v2 a1 R3 p2 p: P714156  Capture crash while archiving project for external referenced design
+ H9 Z( [0 [# h. c+ |! s6 ?716097  Specctra is crash during route.
4 c/ i# A* R/ l3 C716212  PACK_SHORT property gives package error for visible POWER pins 717484  Dynamic shape creating voids when moving a symbol
5 G* B) z2 j$ E8 o718151  Geometry not selected when we click tab for selection filter in pad designer
9 m- ~  Y3 \) p* @720092  Difference of behavior for slide for segments in options tab & RMB options
+ z8 N: Z  g% _  s# U2 u720191  Delay tune cannot keep the Gap if the diffpair segment is diagonal.
. m; y  d; J7 E7 E" u) r0 C720482  Include steps to Enable PSpice Menus in Design Entry HDL
" r: V9 \2 e6 s721415  Two buses are connected without a warning when moved on top of each other
8 C7 H, w! A5 [4 F721938  Cross-Section open error
" A' b/ |9 V' a& H7 A2 @722997  Hyperlink function does not work if zone info. includes hyphen
: }/ S) @  V& t; G& X723146  Pb during compilation using predicate getFileStrings & A1 X- ^- T* z2 w' j0 l2 a
723159  Typographical Error under "Synchronizing PTF Information" section
& t2 V* _9 ^0 y% G/ j, w723235  client install results in incorrect, redundant, and problematic cds_lic_file variable
( E2 f0 {8 N7 K$ d$ J1 m+ ?1 ~* T$ D724414  State Wins Over Design does not reset the subdesign_suffix block values 2 o% ~0 H6 @% ]% ], @& W! N. C
724969  Allegro crashes when using place replicate function , ?1 L" `' R) h" o" s
725852  Impedance has little difference - BEM2D # J- W9 m# D+ u/ f+ r
726731  SiP - Wirebond -> Edit -> select bond finger -> RMB Change characteristics results in
* M: e# p' f4 F! @bf not following snap 8 T2 K. M  g0 K4 t3 J: j- M" U
726763  crash during logic import in Allegro CM enabled flow
# D& E& S8 f+ F+ Y; u+ Y6 ?$ R727663  Remove Subclass in My Favorites (Color Dialog) doesn't refresh properly
3 b) P) b6 B; Z* [, z9 Q( ]" B! z1 d3 W729496  Build error in 16.3 and 16.4 cdnsip.exe
作者: gleefly    时间: 2009-12-12 23:20
一般人根本上不去,下不了
作者: jobjin    时间: 2009-12-17 05:43
Good
作者: xiaocat85    时间: 2009-12-17 08:47
有时间扔到网盘上给兄弟们
作者: cassy    时间: 2009-12-17 17:49
等破解完善了再下～
作者: elm99    时间: 2009-12-17 19:34
Very Good
作者: yejingang    时间: 2009-12-19 17:36
BUG可真是多呀
作者: cxt668    时间: 2009-12-20 16:23
有那些bug呀
作者: T45524093    时间: 2009-12-20 21:45
等待网友分享
作者: yjgyiysbcc    时间: 2009-12-21 12:40
刚下载了
, ]# [+ ^8 {3 e8 ~& o/ Yfor linux版本7 ?7 ^2 m" F0 A
正在试用
作者: suiwinder    时间: 2009-12-21 15:36
有没有好的破解？
作者: jima    时间: 2011-4-12 14:27
运行很慢，bug也多，不如用15.7的
作者: wzwang2000    时间: 2012-6-17 11:02
呵呵，我都用16.5了，楼主动作有点慢哦。



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