标题: 求救—谁能帮忙改一改 [打印本页] 作者: zhong0985 时间: 2009-10-31 17:10 标题: 求救—谁能帮忙改一改 library ieee;/ J; V3 C& [) Y; R
use ieee.std_logic_1164.all; {: d0 ?9 x9 A! t
use ieee.std_logic_arith.all; 2 A( u. C. ? q& h* B: Ause ieee.std_logic_unsigned.all; E$ U# {/ B0 K& \entity hour is $ p$ y' H& y$ s p7 C0 h port(clk_h,clk_t,tp_h,res_h:in std_logic;" O( B8 d1 O& l. Q- t
hset:in std_logic; - A! G' G8 T5 m* k, S" Q R o sig_h:in std_logic_vector(2 downto 0); # F/ o# Q+ y3 J" v% ? din_h1ut std_logic_vector(3 downto 0);: K9 [5 o' j' E( r- Y
din_h0ut std_logic_vector(3 downto 0); : q1 V% i+ F! }/ k) Y8 r pmut std_logic; s+ a9 {' h( K( V' d- Y
cp_h:out std_logic); 7 s& U- l* [: v 3 c4 |8 H- `' w) c& w) Send hour;! D' G% ~4 y7 L( k/ W
architecture behav of hour is/ q" A5 b! `7 I! z! m S6 ]
signal clk:std_logic; ( N, H8 s! }$ w: B0 e- E- L$ Cbegin2 t" y5 J0 d) N- x$ N1 U
process(clk_h,clk_t,tp_h,sig_h,res_h,hset) " |5 F$ R4 g# m variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0); 0 ]7 v9 m7 g+ U8 V4 x. r3 ? variable co1:std_logic;' ^ A9 o. ]- w7 Q6 ^$ R7 R7 C
variable co2: std_logic_vector(7 downto 0) ; ( x1 J1 B( G. r/ F! ]# c begin " q! k" \! y" ]2 d. m+ \( x( ~
if sig_h="001"and tp_h='1' then clk<=clk_t;! q- y, \$ k$ @% I
else clk<=clk_h; , H7 s% R( Q5 m' I- L) l0 T4 Z end if;; `$ S- g+ u* x' U: [' M! p7 U
if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0'); 7 ?& u4 j7 X8 U# {+ D, [4 N( i elsif clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1; + w' }& v+ m7 N: t if cq1="1010" then cq2:=cq2+1;cq1:="0000"; ( D- |7 i8 u4 a* J; ~$ o& t end if; ( z( J/ ^2 B# B; L- \7 ~ if cq2="0010" and cq1="0100" then ( m, b. f0 z3 A4 |( q+ F( ^ cq1:="0000";cq2:="0000"; - D% a2 q a& g co1:='1'; 6 e+ E- A% e u+ @5 A9 @/ d else co1:='0'; ( T& p h8 q* ~% l end if; ; d7 p7 p W. y) Z* z if cq3="1010" then $ Z$ u, L" R1 x# m2 x
cq4:=cq4+1; * ^) ^$ y' h- q5 J cq3:="0000"; 7 E9 O) p, }* \1 z end if; 7 G$ P0 c4 d5 Y* I if cq4="0001" and cq3="0010" then 7 N* F1 g. A$ Z" T9 K: z cq3:="0000";cq4:="0000";co2:=co2+1;' }) _4 h: [/ y3 D5 P
end if;8 N8 n3 A, D3 A. V+ r4 [
end if;, c( _0 C6 \ }1 ?* b+ r- u
if hset='1' then 7 \( \9 `& E. g# \0 z! u: }4 y3 z din_h1<=cq2;din_h0<=cq1;cp_h<=co1;. ^, a8 [. q# s' d
else7 E$ E4 u& F: Y0 E% D9 a, v
if co2(0)='1' then / u( O( S( G9 u) j( w& m! Q
if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0'; / ^" n2 ~4 n7 ]/ J. d+ K end if;; _ |+ j; H$ `! Q" X1 u' Q5 w
pm<='1';& {) W. u& U* L, a |& Y! Y5 i
else pm<='0'; y# [6 V0 i c+ u
end if; - h. j/ J* I* G& | if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1'; ) q% p+ ]- h! j9 _- w0 O% z else cp_h<='0'; ( G4 Q1 r- ^2 o2 ]3 d end if; 2 |* W. V+ i/ @ din_h1<=cq4;din_h0<=cq3; ) L3 S V, i- M& z end if; --12/24转换* ?! [5 Z2 P. ~
4 d* o2 J) i- g4 { end process; " D8 P3 \+ X! qend behav;作者: zhong0985 时间: 2009-10-31 17:10
报错：9 ?) U! q6 E0 R5 g; N' N
Info: *******************************************************************) F, d' F) A4 ]4 p, G9 G- J" k
Info: Running Quartus II Analysis & Synthesis : w1 R5 P! c" N% J( o Info: Version 9.0 Build 132 02/25/2009 SJ Full Version % W0 d" I, O5 p# m& z. ?. ?# ~0 o Info: Processing started: Sat Oct 31 17:04:02 2009 / O: s$ T4 D- E% E/ @! TInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour5 K1 v( F( Y( C% m' r6 [
Info: Found 2 design units, including 1 entities, in source file hour.vhd * K( q1 p' X y; |& E7 d Info: Found design unit 1: hour-behav) T$ o& [. e. t, D# _
Info: Found entity 1: hour % D4 w, }7 n. N3 WInfo: Elaborating entity "hour" for the top level hierarchy" b+ }# E# D; e* M3 i/ Q# D
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list ; R; I& U# L* A6 q# l( j' iWarning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process E3 m& e% G4 k/ R+ ]Info (10041): Inferred latch for "pm" at hour.vhd(20)+ n6 ?1 ^8 m8 } G
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model 8 z% N- R) \: Y2 M$ E& M fError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model 4 d8 P( d" e# O3 Y% O9 a# u% {2 BError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model 6 j2 Y6 c& ~7 j7 gError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model 5 K) h1 f* d4 M9 mError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model 6 @4 K2 y. M2 H- \5 h6 VError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model. i; c0 v) M( Z' {. c
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model . g, V* r* }7 Y. r% f2 n5 }Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model) }" P e2 }; H7 c8 |% p& \
Error: Can't elaborate top-level user hierarchy ) E( S7 A t% L3 `& ?. iError: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings3 t: H; U o$ N/ _* A. G" F+ n, w+ W y
Error: Peak virtual memory: 184 megabytes - Q4 ^. O1 a$ ^( |6 n" { Error: Processing ended: Sat Oct 31 17:04:04 2009 ) A; V! p d3 ~' @* F2 ?* x! q Error: Elapsed time: 00:00:02. `$ _4 {0 Z4 E: L! g
Error: Total CPU time (on all processors): 00:00:01 ; ? [ e- Q7 w. LError: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings
ut std_logic_vector(3 downto 0);: K9 [5 o' j' E( r- Y