4 n% T* O( R: {7 x5 [9 j我是新手，我用orcad画完原理图，drc检查没有错误，但就是不能生成网表，请教：谢谢！ " C) j& @: [. b/ \& E( ?0 r + w: K- v `6 `: e8 u5 R# Ilog： 5 v. n$ ?; r: `& `: }- R7 j. W" M+ Q $ c$ m' Y* t- A$ k# b% [* ]0 I& z. X7 g& T& z0 x
Loading... C:\Documents and Settings\Administrator.ASUSTEK-4295C4C\桌面\sch\allegro/pstchip.dat: V' l0 K$ V7 H. P* P; }. G! M
#72 ERROR(SPCODD-72): A mismatch in the number of sections occurred on line 1701 while parsing logical pins.' a& Y2 d; L! V8 f
To avoid such errors, use Part Developer instead of manually editing the library part definition . V# F2 u! i5 {, ^ ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.2 S# y' F- z' R6 c, m6 E0 G( w! a
#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging. 8 X7 e E- a7 ~! U#21 Error [ALG0036] Unable to read logical netlist data.作者: 袁荣盛 时间: 2009-8-30 19:59
中文路径作者: _new 时间: 2009-8-31 12:53
我改成全英文路径也是提示错误,一样de错误log,呜,