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标题: 8片 DDR Layout Guidelines and Topology: [打印本页]

作者: tzwhzf    时间: 2009-8-1 13:54
标题: 8片 DDR Layout Guidelines and Topology:
Layout Guidelines and Topology:
4 y/ R; K1 r. L: A' @1 E' ]The following are the routing guidelines followed for DDR memory interface section:
  I* {( h" X5 m8 i5 k! Z8 o1. Controlled impedance for single ended trace is Z0 = 60 ohm.4 t2 W( v3 ?3 H: p0 L; a- U6 f
2. DQ, strobe, and clock signals are referenced to VSS.* b; m) ^, d/ ~7 h5 {* K" S. ^( _
3. Address, command, and control signals are referenced to VDD.6 C2 q* t3 Y" C' B* o, C
4. The length of address, command, and control signals are matched to clock with +/- 100 mil  f. w6 E3 I/ i1 q! S8 b( N
tolerance.
  }$ W1 l3 l3 K; _5. DQ <0..7> & DM signals are length matched with respect to DQS with +/- 100 mil tolerance- o" n$ w/ ~0 [5 D- m
(byte lane).
# [3 t' O9 F0 P, B* r* u4 K6. Each byte lanes are routed on same layer.
* V$ \1 I4 ]6 P( _9 ~7. Byte lane to byte lane is matched to clock with +/- 500 mils.
$ u' y% J) X/ h3 Z8. CK & CK# are matched with +/- 30 mil and are routed as diff pair with 120 ohm differential# x1 D# u2 y+ g/ w
impedance.2 Y% R) ]$ B: x6 x
9. Clock - pair to pair matching tolerance is +/- 30 mil.3 h3 C) Z2 O  V4 D$ I- C
10. Trace to trace spacing is 2X and signal group to group spacing is 3X.
! w( Y, {% U- Y) \5 x: v11. DQS signals are routed in the middle of the byte lane (DQ<0..7>).) `6 S0 Q6 F9 D! \4 e  k9 L
12. Clock trace split point to DRAM is less than 1 inch.3 u( o, X1 f! p4 r$ o9 y- J4 Q7 K7 W
13. VTT and VREF islands are separated with the minimum spacing of 150mils.
! @5 M2 y1 j/ F' h: n7 H14. VTT island width = 150 mil min.; 250 mil preferred.
( g0 ?% Q  |8 O* R* C- P( b7 l) G15. VREF signal is routed with 20–25 mil minimum trace.) V& z9 m9 \+ K5 j/ W
15. All signals are routed with minimum of 3X spacing between other signals9 @+ S0 S( ?; @. j& t, I1 U5 h
16. Layer biasing is followed for dual strip layers.
+ g* Y& A  p2 Q% [& G# YFigure 1 shows the data bus topology and figure 2 shows the address/control bus topology.
作者: tzwhzf    时间: 2009-8-1 13:58
元件放置方法:
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0 H) r- g% N0 l1 h( Q数据线拓扑:
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% E5 W. b% B4 A2 L- A$ S地址线拓扑:* x4 T7 J! z* M0 _/ Y/ [$ U

8 M* c; ^9 d6 `- r1 S时钟线拓扑:
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作者: 一粒沙    时间: 2011-8-25 20:15
瞄 画个立体的更直观
/ _) v# y+ o4 o* r# _
作者: mcizhy    时间: 2011-9-16 14:27
提示: 作者被禁止或删除 内容自动屏蔽
作者: xieyifu    时间: 2011-9-18 16:15
谢谢楼主,学习了
作者: wanghanq    时间: 2011-9-19 10:13
原档

Memory Controller and DDR DRAM Design Analysis Document.pdf

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作者: lbq211    时间: 2013-12-29 20:42
谢谢楼主、楼上的




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