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port(clr,sig,door:in std_logic;6 P, }: Y# ?7 S6 ], a* }. r V
almut std_logic; 5 D2 B# }: K4 E9 |q3,q2,q1,q0,dangut std_logic_vector(3 downto 0));% X, E6 k5 x) Q
end corna;: d1 X" P, j9 ~8 v8 t
architecture corn_arc of corna is / {2 L0 d% |7 e9 X0 g* Q$ Rbegin; F. K3 C4 j0 T( {' y
( j/ G1 R8 O1 S+ C1 _ m1 t
process(door,sig) : ^/ g' [4 |% k9 N3 z6 g. _9 _# s7 J/ y' b, z% p
variable c0,c1,c2,c3,c4,c5,c6:std_logic_vector(3 downto 0);4 w" C5 ?$ f' x: ^$ f% F
% c- n X [4 C" Y: ?7 C/ p" d8 K" ovariable x:std_logic;; k! ^- j0 q# f+ J
$ Y( G( |+ l3 r ^/ N$ w
begin g x8 K3 _8 X& Z. P3 h6 ~
if sig’event and sig=’1’ then * T0 k: a7 G. x$ f- J5 C. }2 p8 ^6 S2 g) R! b
if door=’1’ then$ F: E- \5 {# k& p9 ?
, y, C/ K7 i4 \: Zif c0<”1001” then, U. e. I& A4 a" y* ?( W
8 @0 _! A- E# k: g4 s) ]c0:=c0+1; 9 Z* j6 ]) L: g: s8 e9 r8 ?/ p: y
else 3 D) o5 O9 K# t0 q) o / @& @+ t0 r1 c& g, f/ ~& p4 a 9 P4 c5 @* }- m% a; Y& Lc0:=”0000”;9 Z3 Y) e X3 S3 o' ?" F( M
+ {. }% a4 Q Y$ `
if c1<”1001” then9 Q* ^. U$ ]: _( ~, n( N