# X$ u2 S) Q, p4 V( F- J/ H) a6 M6 \+ v作者: gleefly 时间: 2017-7-2 18:37
Fixed CCRs: SPB 17.2 HF021 / X7 a. M$ t% e8 ~' e0 t! {. }06-3-20177 @ E% ]+ e v; B/ p5 i! R, d
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CCRID Product ProductLevel2 Title. k, o5 m3 r% i g
======================================================================================================================================================== ) D [2 H/ g& r0 I( l1401318 ADW DBEDITOR Bulk Edit - Previously modified cells do not turn blue when selected 5 g5 V5 a1 z+ V: q1621446 ADW DBEDITOR Bulk Edit - sorting highlights incorrect cells to mark them as changed( g" N( H3 [5 x) ~( i+ }
1743997 ADW LIB_FLOW Match file for standard models is incorrect$ F. U! [; |, W3 g/ n5 ]8 \
1746052 ALLEGRO_EDITOR DATABASE PCB Editor crashes when applying no drc property2 U2 M, i- K. Y8 {+ G
1736067 ALLEGRO_EDITOR DRC_CONSTR Interlayer checks not reporting DRCs between cline and mask layer * g. ~, H+ i; V! F6 L: {1738587 ALLEGRO_EDITOR EDIT_ETCH Line width changing on slide for ETCH - Conductor (Not on a NET)& r3 ]. B P, f) l$ u6 p1 e
1745277 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on using the slide command - O J- D; i" a) \1747942 ALLEGRO_EDITOR EXTRACT Fabmaster Out does not export arc in pad_shape& d2 I- l" ]; j: u/ {
1737202 ALLEGRO_EDITOR GRAPHICS Setting the variable display_raster_ops " ?; \' Q4 Y' n1744042 ALLEGRO_EDITOR GRAPHICS Unused pad suppression is not working on few nets" a; E+ Z' n; ]& R
1703848 ALLEGRO_EDITOR INTERFACES IPC 2581 fails with error 'E- (SPMHGE-268)' and the log file is empty. @3 g+ R0 `- |
1743899 ALLEGRO_EDITOR MANUFACT Glossing dangling vias crashes PCB Editor* H0 N' H5 o3 `- T( I3 j( H9 s5 u
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor8 m0 y' N9 r7 d% j
1748520 ALLEGRO_EDITOR OTHER TDP fails to load on an empty database+ ]* O% l$ X$ E( b8 i4 V
1748581 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes when changing default pad geometry & }7 S* b8 A# J5 o# c1751469 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crashes/freezes when browsing for a shape symbol% T& A3 I! q4 F+ W& y$ e
1725948 ALLEGRO_EDITOR SHAPE Shape differences after conversion from release 16.6 to release 17.2-2016 ! F9 g7 ?7 @' Q& T2 I1729306 ALLEGRO_EDITOR SHAPE Seting shape_rki_autoclip variable causes no void to be generated & n/ S E# k4 c6 s+ ^1698876 ALLEGRO_EDITOR UI_GENERAL Tabs are large and text is compressed in release 17.2-2016 . N/ Q/ u, \( `7 C! l$ a: h1698883 ALLEGRO_EDITOR UI_GENERAL In release 17.2-2016, enlarging icons makes selection boxes/text unreadable on 4K monitors 7 Z2 I6 p' w5 t3 T Y% Y( m7 ?1707933 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not locating menu as per x_location4 B/ J4 `0 G- y
1741460 ALLEGRO_EDITOR UI_GENERAL Right-click, context menu options grayed in some cases after choosing Edit - Copy" C$ E) K% C! K6 T
1747588 ALLEGRO_EDITOR UI_GENERAL Interacting with PCB Editor by sending messages is not working' q4 O# O' Y- M8 b
1747488 APD EDIT_ETCH Route connect is improperly affecting existing routes in locked high speed via structures ( x( H' Q2 a* A8 v7 E7 d2 E1750182 APD STREAM_IF The stream out settings are not saved" k) t5 o+ ]! |/ Z8 c+ g1 o
1752067 ASI_SI GUI Links to differential waveforms do not work in Sigrity SI report! e" I/ I) \2 C) J
1752131 CONCEPT_HDL COMP_BROWSER Symbol view in part manager doesn't match the symbol version1 M# M1 X5 R8 f! a
1754116 CONCEPT_HDL COMP_BROWSER Default Symbol selected is n°2 instead of n°1 in component Browser- r% W, R/ T+ v) U
1754949 CONCEPT_HDL COMP_BROWSER Part Information Manager displays preview window with the wrong symbol and missing footprint ' [$ z9 ]1 n9 D9 h) }4 b1721334 CONCEPT_HDL CORE dsreportgen not able to resolve gated part on schematic ! ^/ U) x2 Z) G- m6 Y; R1750916 CONCEPT_HDL CORE DE-HDL crashes when trying to uprev a project in release 17.2-2016 * ?" z( f$ K, `8 j, v M1711487 CONCEPT_HDL INFRA Restrict opening of release 16.6 designs from a release 17.2-2016 design using File - View Design* M) R& e; m. g9 Y$ i+ D
1746915 CONSTRAINT_MGR CONCEPT_HDL Unable to copy a Physical and Spacing CSet generated from the Constraint Automation flow' V! N5 ?: ^- \/ T8 |; H
1743523 CONSTRAINT_MGR DATABASE Suppress warning pop-ups from the constraint automation script : D* \0 J4 W" x$ m1746941 CONSTRAINT_MGR UI_FORMS 'Go to Source' from DRC tab is not working in release 17.2-2016 " f+ h$ }) `9 e' w% j1753010 ECW METRICS Metrics not getting collected due to old license in use8 s$ H% L. p6 |2 }9 j" V
1713052 FSP GUI Pin/Port Name and Group Name are not aligned properly in FPGA Port and Use Pin Mapping for DeviceInstance 8 R% C3 ~& {! H5 @: p* D7 V9 d B1719099 FSP GUI Net naming wrong after building block % n2 r v C( [ x- p1719105 FSP GUI Tabular sorting not working in FPGA System Planner 0 s+ `0 _- I3 R7 j4 k# n1720479 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems 5 f; D P$ t8 ?, s1723411 PSPICE ENVIRONMENT Probe window does not open consistently on Windows 10 systems. c% s/ ?6 B' ]2 P/ r# h! n
1746628 PSPICE ENVIRONMENT PSpice Simulation Manager displays same message for all simulations in release 17.2-2016, Hotfix 016 0 S4 G' A f' Z; V! t2 U1745976 SIG_INTEGRITY GEOMETRY_EXTR Arcs with coplanar waveguides are extracted with incorrect spacing0 g& x0 ?; x) p* `) k
1690820 SIP_LAYOUT PLATING_BAR Cannot add fillets to pads with plating bars in release 17.2-20169 b' H: ]3 ^! |; d; j6 N _
1725042 SIP_LAYOUT PLATING_BAR Creating a plating bar removes dynamic fillets8 p! t& }+ S: u7 E3 P0 p [
1747534 SIP_LAYOUT SHAPE Moving fiducial crashes SiP Layout9 Q m* B& B9 C, Y! X/ Y