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在网上寻找数字地与模拟地的英文材料;* F8 f( U, y9 \, O) h& z
无意间浏览到一个国外的的CPLD/FPGA论坛,点击进入3 b: W# u e) q
发现了有人求51的IP CORE,在回帖里面看到这个,所以下载了。
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@: mc8051@oregano.at
5 U, u) V3 B3 g7 V* bW: http://oregano.at/ip/8051.htm' }) r' t3 I6 D [! l
9 X: ~& _# H! N& U$ y8 K************************************************************, V$ d3 G" i: W& S
This is version 1.4 of the MC8051 IP core./ o5 g j4 c/ t1 C ?. a5 a
November 2004: Oregano Systems - Design & Consulting GesmbH
( |+ R; q+ L1 w+ D& m* ^4 N============================================================/ t6 x/ \3 [9 ?6 ]9 J
Changes:
7 F8 U9 @5 u( c5 K- corrected behaviour of RETI instruction handling
/ k" U9 |0 X8 M/ t8 J# R% U- L- added synchronization for interrupt signals# j! \5 a/ A8 X; X
- corrected timer problems
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************************************************************% O- y8 r! G+ g
This is version 1.3 of the MC8051 IP core.5 I3 l4 `2 V1 s+ V0 G% `+ ~# {
September 2002: Oregano Systems - Design & Consulting GesmbH
) z# {9 p7 L; F! ` ?============================================================: y+ J/ F; p) @& A% d0 T1 Q
Change history:. V6 v. N2 f, p; M
- Improved tb_mc8051_siu_sim.vhd to verify duplex operation.: i ^$ x5 Z/ B5 `: ~
- Corrected problem with duplex operation in file ( E5 ^( L# Q3 J6 @# O; ~8 K
mc8051_siu_rtl.vhd
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* g% D0 S" G5 ~" X' u1 f************************************************************
' G t9 J$ M U+ L+ |This is version 1.2. of the MC8051 IP core.- O, m! ?( U$ S5 y" q- t# M
June 2002 - Oregano Systems - Design & Consulting GesmbH
, i9 _0 S! f6 M$ E! U M- g" C! c/ I============================================================8 I7 u. u$ H- l7 o+ h
Change history:# |% P/ C" h; b0 i
- Eliminated the scr subdirectory form the distribution.
' J* g$ I/ V4 C# _% A4 C8 }3 Q3 H1 X- Improved documentation." i! b* Y$ d9 U+ |
- Corrected several bugs in the source code (see the
2 V+ B# q& n! {$ h( @. x website for more details)., X% S$ w& t9 W: M
- Improved the testbench with respect to the I/O port+ f) |; m2 S4 ~5 j' ?
behavior.
! V5 Y) S: o/ D2 M- o- Enriched the msim directory with the assembler source
1 q3 X( \# y: i4 c$ y; @+ F8 w code of an example program.( z6 l& v: }# b' M: \1 b' p' X
- Provided the source code of a Intel hex to binary; M+ J1 { V$ v' O
textfile converter to ease simulation of the user's+ f# l- J4 D; G* s. Z
assambler programs.
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************************************************************; r8 L3 o/ Q/ b; y/ C! j
This is version 1.1. of the MC8051 IP core.
: J. b6 ]( l& j+ ]0 sJan 31st 2002 - Oregano Systems - Design & Consulting GesmbH8 m- k" c v# J) {% R
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下面是里面的部分VHDL7 j' e" g& L4 z4 K; |
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* n" q2 Z- t, x0 ^) @library IEEE;
) m+ R+ t8 i( x9 duse IEEE.std_logic_1164.all; 6 G) N M! Z2 M' l
use IEEE.std_logic_arith.all;
! ]: M, K" \0 Z6 S5 u0 b, Clibrary work;2 J0 |: x) N# W9 ^9 ^; w: u
use work.mc8051_p.all;( k3 I( w3 _3 |8 M
# ?) {7 ]: K# I7 _" o5 S3 X1 a- Z-----------------------------ENTITY DECLARATION--------------------------------! l4 b+ \) G7 `, F
entity addsub_core is
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3 k6 t6 C6 q3 A) d generic (DWIDTH : integer := 16); -- Data width of the ALU: k8 l1 H+ h+ B( z
port (opa_i : in std_logic_vector(DWIDTH-1 downto 0);
) K4 C% r* b. ]5 i/ V: y5 } opb_i : in std_logic_vector(DWIDTH-1 downto 0);" J& p3 H0 A( h# j: @
addsub_i : in std_logic;! v( d. \7 a# L( X
cy_i : in std_logic;
& D& O; {8 M$ U" Y: U/ A cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);- \3 p) A: [; R
ov_o : out std_logic;: r3 u' }& m9 t# x, z; B
rslt_o : out std_logic_vector(DWIDTH-1 downto 0));
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end addsub_core;8 a9 ~ f; m2 K7 t+ O- B7 `2 s
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entity mc8051_alu is$ Y$ e( F$ Y, t9 h4 l6 _! F2 f& |
generic (DWIDTH : integer := 8); -- Data width of the ALU) J1 L$ P" l9 E/ N
port (rom_data_i : in std_logic_vector(DWIDTH-1 downto 0);
8 o- S3 |% F; |8 A. Y: r ram_data_i : in std_logic_vector(DWIDTH-1 downto 0);
. U+ r) d+ } K' P acc_i : in std_logic_vector(DWIDTH-1 downto 0);
- u2 D, o3 o- v cmd_i : in std_logic_vector(5 downto 0);
: }" p3 Q/ A) l2 X cy_i : in std_logic_vector((DWIDTH-1)/4 downto 0);4 p9 Q" M+ v. V6 C
ov_i : in std_logic;
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* s0 A8 C- ?! D$ `8 v+ ^6 r$ s8 G new_cy_o : out std_logic_vector((DWIDTH-1)/4 downto 0);
* c# P9 |( i y/ J* F1 j9 ? new_ov_o : out std_logic;
3 r2 M7 T# h6 V- L G! ?1 ]( M0 y result_a_o : out std_logic_vector(DWIDTH-1 downto 0);
& ~" Y# A7 L3 u& D3 ~& @. R8 { result_b_o : out std_logic_vector(DWIDTH-1 downto 0));
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end mc8051_alu;5 A6 ?. w8 F$ B( x5 Z$ s
--Inputs:
$ z/ N8 z# y# j& d-- rom_data_i...... data input from ROM
; j9 r) F# e; p; a-- ram_data_i...... data input from RAM8 `& D- H5 v: J5 C# s
-- acc_i........... the contents of the accumulator register
& U2 l8 H% X( z5 n-- cmd_i........... command from the control unit! V2 r: T" W0 d" d1 P' @
-- cy_i............ CY-Flags of the SFR
2 b4 [/ t; J W. R0 o. o-- ov_i............ OV-Flag of the SFR& A1 B$ e) \& F3 Y4 K- T% n: t
--Outputs:$ w, e2 I- i- l h' |5 k
-- new_cy_o........ new CY-Flags for SFR) S' T3 I6 t1 {/ l- W
-- new_ov_o........ new OV-Flag for SFR
3 _5 e6 r3 s. s) P3 W-- result_a_o...... result' |, E$ @' [( Z! j: t+ S
-- result_b_o...... result
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1 Z( e" F+ l6 B1 c& Z4 n2 @6 iarchitecture struc of mc8051_alu is; ?7 n4 x4 c* l5 z: ]
signal s_alu_result : std_logic_vector(DWIDTH-1 downto 0);1 y1 [7 M& U7 h" n. u
signal s_alu_new_cy : std_logic_vector((DWIDTH-1)/4 downto 0);0 f* g9 L# ]3 |/ c1 y0 ?
signal s_alu_op_a : std_logic_vector(DWIDTH-1 downto 0);
) q( V3 v/ T/ n+ x) L/ x6 F2 M$ R signal s_alu_op_b : std_logic_vector(DWIDTH-1 downto 0);
4 w) F) Q+ D/ D& N' N7 K4 d, `/ | signal s_alu_cmd : std_logic_vector(3 downto 0);
& W, {! y2 K% G9 k signal s_dvdnd : std_logic_vector(DWIDTH-1 downto 0);
" n, o, t+ j3 |1 T9 _ signal s_dvsor : std_logic_vector(DWIDTH-1 downto 0);
: Q" E7 F% f& {/ I! M' s signal s_qutnt : std_logic_vector(DWIDTH-1 downto 0); d- F$ H' }/ c; t- f
signal s_rmndr : std_logic_vector(DWIDTH-1 downto 0);
, {1 @1 W7 v- h: r signal s_mltplcnd : std_logic_vector(DWIDTH-1 downto 0);
, ~4 T5 ~. R3 P9 [; b1 P signal s_mltplctr : std_logic_vector(DWIDTH-1 downto 0);
1 b( W, R+ f, b$ ~7 k signal s_product : std_logic_vector((DWIDTH*2)-1 downto 0);* p5 Q! x+ |2 M0 J
signal s_dcml_data : std_logic_vector(DWIDTH-1 downto 0);. [% i7 t5 |$ A2 [+ e& p' K
signal s_dcml_rslt : std_logic_vector(DWIDTH-1 downto 0);; |# y, `1 \4 \) @% _! f, i
signal s_dcml_cy : std_logic;, {" L/ I9 s( I' y. T/ O
signal s_addsub_rslt : std_logic_vector(DWIDTH-1 downto 0);
) E# a" J2 Q F+ i+ b' V2 y signal s_addsub_newcy : std_logic_vector((DWIDTH-1)/4 downto 0);2 I6 w8 j# \! G& V: `$ _. W
signal s_addsub_ov : std_logic;. S' R7 Y* C) [
signal s_addsub_cy : std_logic;
/ {9 D) R& i. z- w k0 i signal s_addsub : std_logic;1 \0 H8 ^; Y9 ]/ s1 O- g2 C
signal s_addsub_opa : std_logic_vector(DWIDTH-1 downto 0);# d/ L# l. K* O* Q. Z) f" I0 V
signal s_addsub_opb : std_logic_vector(DWIDTH-1 downto 0);7 J9 T" A8 u& `
begin -- architecture structural, }/ A$ d# h/ ` C9 B
i_alumux : alumux
1 i7 X% Y2 z2 B/ i$ Z$ n: s+ r+ R generic map (7 h+ C2 p- n; m# ]% j- Q+ h7 D
DWIDTH => DWIDTH)* k _6 ?+ ~2 Q& | l
port map (
$ D! m5 l, \* g3 K. B" a8 @ -- Primary I/Os of the ALU unit.4 c$ D) {# X5 P3 c5 z" R
rom_data_i => rom_data_i,
8 s, a" L$ Y5 \: P# Z) e1 \ ram_data_i => ram_data_i,/ e& @, l, k9 X2 _( O& P
acc_i => acc_i,' Q( q; p5 f; P& J3 d
cmd_i => cmd_i,
0 M3 G) u3 n: u7 P' E9 i3 M4 c9 q cy_i => cy_i,
$ Q# {: m* ?" [, e5 A9 \" ?" ?3 L ov_i => ov_i," K' ^7 h- ~1 t( F! p
cy_o => new_cy_o,, N' F3 _: g4 c, w0 J6 s1 B
ov_o => new_ov_o,
; E% ?4 R0 B2 n- ~ R' @# \ result_a_o => result_a_o,8 m6 H5 W7 A R n* v: s, E% e* s
result_b_o => result_b_o,
6 f2 L/ q H K9 t- p0 E -- I/Os connecting the submodules.( M0 N0 ^4 m% e6 W' j
result_i => s_alu_result,
- C; C5 w! Q b' | new_cy_i => s_alu_new_cy,( k9 Q7 Z# T4 ^ D4 B6 K
addsub_rslt_i => s_addsub_rslt,6 Z1 R- Q% \5 Y/ m) I/ D
addsub_cy_i => s_addsub_newcy,
; [( J V5 ]5 x. [ addsub_ov_i => s_addsub_ov,
" C6 B0 w% o/ m' `& j, } op_a_o => s_alu_op_a,
2 F$ I5 k( z" Z4 d0 {7 p, Z3 |6 Q6 ~4 V op_b_o => s_alu_op_b,; |0 t# Y. b. @: D: s
alu_cmd_o => s_alu_cmd,
( x( s0 D& J8 |) w( {0 t1 a opa_o => s_addsub_opa,
1 p# E& a7 | A opb_o => s_addsub_opb,7 I% r' j) C" [
addsub_o => s_addsub,
& s, q& ] E6 k9 c8 K8 e1 W addsub_cy_o => s_addsub_cy,9 z! b B/ {6 ]" M. m
dvdnd_o => s_dvdnd,
9 {7 h/ ]- q. [ dvsor_o => s_dvsor,+ X m# `5 z: }6 N D
qutnt_i => s_qutnt,0 f& e4 S" F9 b+ M* N2 b( z
rmndr_i => s_rmndr,* F" w7 ]5 a# @6 {" x7 i8 x+ R
mltplcnd_o => s_mltplcnd,
% v- d# J5 _: G: y mltplctr_o => s_mltplctr,2 y* R1 L; r: h: d# X
product_i => s_product, S, a; j# f# [/ A( F
dcml_data_o => s_dcml_data,
% S" p" Z8 j5 p5 y% Q* U+ m dcml_data_i => s_dcml_rslt,
: W7 l9 |% x! g dcml_cy_i => s_dcml_cy);0 q2 l0 ` o; v( E
i_alucore : alucore
; _* c, ^) @6 W e" P generic map (
0 Q" V* d2 R0 t3 H- O i DWIDTH => DWIDTH)
. x- J( h. t6 D port map (# D8 A3 E5 N& w7 J" y1 ^4 Q" R
op_a_i => s_alu_op_a,
- T! v3 \+ {; M( h op_b_i => s_alu_op_b,% @: A$ b1 Q/ C2 C3 l9 S3 d! i- A
alu_cmd_i => s_alu_cmd,
% l' J a6 R4 w$ E" |# W- D# G0 L cy_i => cy_i,
, {7 z- X$ B% i N8 Q8 S/ S- q cy_o => s_alu_new_cy,+ @! t8 S. i; |4 A! S3 Q. A2 U: \/ ^6 W
result_o => s_alu_result);, W8 F$ ^, E) f* m
i_addsub_core : addsub_core
, R* }- a- ]$ l9 V- w( D; b' p generic map (DWIDTH => DWIDTH)8 s5 {; t' y9 k, q
port map (opa_i => s_addsub_opa,
9 N6 }2 e8 x* ^6 l0 J6 I' O& \ opb_i => s_addsub_opb,$ |( D+ v, S: { l* Q! i
addsub_i => s_addsub,
; E4 k" X1 {$ o# @/ D9 s: O cy_i => s_addsub_cy,' E! d7 l- y; M0 x
cy_o => s_addsub_newcy,
1 ~$ O) w: h9 c+ r' ?) J) w( n& x ov_o => s_addsub_ov,, f/ s3 T9 Q, h3 z1 U( o
rslt_o => s_addsub_rslt);, Y1 k" G. w, `6 T0 `; o1 Q
gen_multiplier1 : if C_IMPL_MUL = 1 generate% F& J) H# u" j: @& f' `' B
i_comb_mltplr : comb_mltplr8 C: S6 c& ]1 a% z- D0 C) i r0 d
generic map (% R( x+ w* ? w, j6 U+ Z
DWIDTH => DWIDTH)
; s8 [$ [3 `" ^1 u8 N0 E port map (8 v: ?7 h! R" _6 e6 ^
mltplcnd_i => s_mltplcnd,! d' Q* B4 g& W( Q
mltplctr_i => s_mltplctr,7 f1 K8 k) B" I) w5 P
product_o => s_product);
0 q D2 G+ g( Q) ^1 m/ s2 c end generate gen_multiplier1;6 q( ]* q& x6 b/ n0 H- J
gen_multiplier0 : if C_IMPL_MUL /= 1 generate. U8 g) Y6 z; y2 C$ b: ]/ R
s_product <= (others => '0');
+ l% z* U9 o$ x1 t' l) Y end generate gen_multiplier0;
1 L/ g; X/ o- N) A& s2 z gen_divider1 : if C_IMPL_DIV = 1 generate
, T/ n+ C9 w9 p1 r' f( y! Q i_comb_divider : comb_divider
1 T3 v: o f' j5 t5 D3 v$ c generic map (# X4 E4 V1 U1 e
DWIDTH => DWIDTH)2 b2 {' X0 n6 G1 ~# X# }
port map (
' g% O, j J0 u3 K1 ]8 y* g5 {/ Q) e dvdnd_i => s_dvdnd,
6 M1 z2 \% h" y e0 }7 W dvsor_i => s_dvsor,+ s2 z! v0 p" a% R1 J
qutnt_o => s_qutnt,3 z/ W( x' T3 G" J2 K! _7 x
rmndr_o => s_rmndr);. E9 z+ u* q1 L' A$ D# w/ f5 D& B# c
end generate gen_divider1;
( J, i, ], B0 ?4 m) t4 W gen_divider0 : if C_IMPL_DIV /= 1 generate: K. Z) W4 y K* ]' X* [0 f
s_qutnt <= (others => '0');- F: d3 R, r6 t7 K
s_rmndr <= (others => '0');
2 D2 u1 s6 a: \, ?# l end generate gen_divider0;8 G3 r: [. C6 r/ ?# r
gen_dcml_adj1 : if C_IMPL_DA = 1 generate; B& H. e k m* }+ o }
i_dcml_adjust : dcml_adjust" s0 A F& {& M% Q
generic map (0 A. O3 L' k1 x/ ~6 ~( [
DWIDTH => DWIDTH). ~7 w+ V, Y+ x! }' V" \/ e
port map (9 M" }' @* J9 g4 X, d) I. q w
data_i => s_dcml_data,
/ o f2 c/ h4 D: _# V- J3 L" F& m cy_i => cy_i,
7 f- ~& w0 i6 Y& ^- x data_o => s_dcml_rslt,
" Z- s% S2 O4 [/ o cy_o => s_dcml_cy);; \. z8 S' W) b) u( |9 _& ^
end generate gen_dcml_adj1;
' X) ? s/ v* W! j3 S gen_dcml_adj0 : if C_IMPL_DA /= 1 generate
5 @3 D' P7 M1 m& t8 T) S9 h. k s_dcml_rslt <= (others => '0');
' S+ L/ p7 E) A5 a9 n" e9 ^' n s_dcml_cy <= '0';+ T1 \/ T1 q/ o/ _3 ^" m+ o
end generate gen_dcml_adj0;
8 k0 G" T* [ D; F7 Nend struc; |
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