标题: 17.2 hotfix001-004更新点 [打印本页] 作者: 金志峰 时间: 2016-9-7 01:03 标题: 17.2 hotfix001-004更新点 ) v+ a8 e) ]( ^: r5 y* t- P/ f
DATE: 08-14-2016 HOTFIX VERSION: 004 % [. f" |6 Q3 p: C# a& W, i, R4 W=================================================================================================================================== ' d b ~: i( {- `- gCCRID PRODUCT PRODUCTLEVEL2 TITLE # c+ W! }5 S! [5 Q. m! M===================================================================================================================================0 N* w2 [( Y4 m0 l* h
908816 CAPTURE SCHEMATIC_EDITOR Few graphical operations are active even when a page has been locked 5 ?2 I1 Z; @' w& @- b* @5 b/ [1213923 ADW LIBIMPORT Cannot delete parts in the Library Import project (XML)' d9 k% O8 Z2 B
1250476 PCB_LIBRARIAN LIBUTIL con2con does not check for PACK_TYPE * F2 h2 T6 R3 W" a2 H1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value' k, L5 }6 W/ E' g4 ^1 ~+ G3 s
1322242 ALLEGRO_EDITOR INTERFACE_DESIGN Using add connect together with replace etch Option is causing the tool to slow down for certain constraint nets5 r/ f6 }. r5 C! ~$ w2 m
1326716 ADW DOCUMENTATION Dataexchange documentation correction needed2 U* X$ }' Y) A9 l
1356948 APD DEGASSING When using the Degassing tool on shapes the size of the file becomes very large4 V9 W7 S0 `0 D' X, Y
1376510 ADW DBEDITOR DX output ERROR after Property Display Ordering of Part Classification.9 F! \8 @/ [8 ^' z
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file 6 k R, ?- ]9 n9 |8 {1410485 CAPTURE SCHEMATIC_EDITOR W shortcut and Autowire active on Locked design : @! x5 D4 |* a2 x& Z' f4 ~1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only / |3 @) @" O' y2 u5 x6 ?1413287 ADW LIBIMPORT Library Import uppercases all Attributes when reading CSV0 K* A1 b! Y5 H
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle2 s! ]% \* _! V" f$ f
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins4 n; h: N& J" X y" Q0 s
1430251 ALLEGRO_EDITOR PLACEMENT Quickplace placing symbols outside of a polygon shaped room2 {2 o. d5 v- f7 c$ c, W4 U
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option " |# t4 A3 {; i1441086 PCB_LIBRARIAN OTHER Changes made to a package with sizable pins generated from the sym1 view are not saved 5 Q. j+ u: a1 b& a& Z7 }! e' m1443339 PCB_LIBRARIAN PTF_EDITOR ALT_SYMBOLS syntax in PTF file not checked 1 \, Z- |3 c: o( E: N1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC $ C1 C" U0 {- y- X$ J; a2 l9 g+ x! E( {1451766 CONCEPT_HDL COMP_BROWSER License error message should indicate which license is required! g: [: p! A$ W4 y9 _
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set . N7 R$ Z7 @& Z7 l0 ?5 K1457138 CONCEPT_HDL CONSTRAINT_MGR devices.dml: difference in content generated by _automodel add command and Constraint Manager launch5 V9 o% ?8 Z1 w0 s' O$ V& g
1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties4 S8 z5 ^ ~! F4 [$ s0 O
1464865 CONSTRAINT_MGR ANALYSIS For identical nets, topology in DE-HDL CM is different from the topology in PCB Editor CM ' b2 T/ @+ L% a3 G1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools1 t: B. j) F4 I- y A- `9 ^
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename : E8 F0 f$ D0 j( r1470106 ALLEGRO_EDITOR MANUFACT silkscreen program cuts auto-silkscreen lines excessively: t( Z4 X. m& j) S( \
1471287 CONCEPT_HDL CONSTRAINT_MGR Importing pages from other designs with different units should inherit the source constraint units + c* c2 Y5 l' K n6 N" G1472046 ALLEGRO_EDITOR OTHER Gloss routine, 'Via Eliminate' - 'Eliminate Unused Stacked Vias' is not removing unused microvias from the stack# V0 B1 W1 X( {8 k N- W# J
1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region! b+ ]8 s$ W6 O- w* A+ x+ C' T
1472444 ADW ADWSERVER Multiple errors in adwserver.out after SPB 054 / ADW 47* r- z, r1 A, n& l$ }
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design" R3 G9 H, F6 A9 ^0 T4 Q" j
1473900 CONCEPT_HDL CORE DE-HDL stops responding when a hierarchical block with variants defined inside the reuse block is enabled( W/ z2 Z7 S6 y
1474020 ADW DBEDITOR Unable to modify schematic classification when a part is checked out previously by another librarian ; D% Q# @& p3 M8 h1474066 ADW DBEDITOR Bulk edit performance lags when parts included have large number of properties$ n* o" c* w7 E, R. W2 a( l/ l3 m/ a; a
1474764 ALLEGRO_EDITOR PLACEMENT In Hotfix 56, the 'place replicate create' command does not produce desired results if a fanout is marked ( E0 y; x8 }9 ^5 m3 c; v5 v1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits. 4 u! c" v M5 S- x2 B# @* ~1475650 ALLEGRO_EDITOR OTHER Using Outlines - Room Outline gives WARNING (axlRemoveNet): No match for subclass name - 'BOARD GEOMETRY/__EPB_SCRATCH_'3 s) U' f. E5 @! e9 O! s% t! r3 h
1476528 ORBITIO ALLEGRO_SIP_IF While translating a .mcm to OrbitIO, the error 'allegro2orbit.exe has stopped working' is thrown + D+ c6 V9 f( m9 q1476920 CONCEPT_HDL OTHER Genview consistently fails in some indeterminant manner. X+ K: J: K! J/ b% }8 |: q. M1477369 CONCEPT_HDL INTERFACE_DESIGN A significant number of problems are reported when running genview with port groups : }; v3 I9 M" W. Z7 m" c1478111 F2B DESIGNVARI Hierarchical block variant not shown in testcase with S57 although it was working with 2015 release. m! W: _$ I/ W3 M( W
1478200 GRE IFP_INTERACTIVE Allegro give error "Low On Availlable Menory" and then crash % B5 S0 \" B% w( S1478680 CONCEPT_HDL CORE Unable to move components in a schematic using the arrow keys6 ?! r9 ~5 c; e1 k7 H
1479135 F2B PACKAGERXL Hierarchical design reports conflicts when signal names change through the hierarchy* ]: D, O" K m& u$ T* \% x4 s$ x* Q! N
1479153 CONCEPT_HDL CORE File - Save Hierarchy flags an error and does not update subdesign xcon0 n/ v8 h4 h$ g7 e" n; I/ O% b
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy4 B( j* ]6 \. X3 Z- K
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable & S Q1 g+ f' W( {/ j1479569 PCB_LIBRARIAN OTHER hlibftb fails with error SPCOPK-1053) ~; `0 M4 J0 D% K) b e
1479785 ORBITIO ALLEGRO_SIP_IF brd file does not get loaded in OrbitIO6 ]# c' B1 M- U( \7 h
1480005 ADW DBEDITOR DBEditor/DBAdmin GUI do not allow the same characters in Property as LibImport CSV Files( L/ q/ A9 K. ^# s3 k; O9 ?- E; g8 X% X
1480367 SIG_INTEGRITY OTHER Differential pair extraction SKILL error, 'parseString: argument #1 should be either a string or a symbol'# U: U0 P) l4 d# L" u% e
1480499 ALLEGRO_EDITOR PARTITION Cannot delete partition$ O( @" \& E2 N( w# D4 \9 p
1482544 ADW DBADMIN Hierarchical PPL not functioning correctly h9 \' L' S# k9 A3 F1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode, M3 j$ f7 l( s- Z* U8 e- {
1483617 ALLEGRO_EDITOR DATABASE Delete islands command crashes database with filled rectangles - @, y9 |+ V/ u* |1484100 SIP_LAYOUT INTERACTIVE Tool crashes when copying and rotating a symbol 1 |5 i4 I: }) o6 |, w f1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues# H+ B' A9 w, l
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only0 _8 d3 b- d4 p6 u
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file v# S- ~, G* d: K) f5 v/ n2 K# D# C" [1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project % S* Q0 N% c( F4 H" z# m1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork. " V: Y' p/ L$ P$ B5 Z, H" @$ i- j1486378 ALLEGRO_EDITOR PARTITION Unable to delete orphan partition as it is not listed in workflow manager. + X- }/ ]- o3 D/ L' U# R7 h' o. f1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems( k. O' y z5 H- w# X: e$ a
1487125 ADW COMPONENT_BROWSE Results not displayed in the component browser when no mfr parts are associated . N. M' K" w/ H7 i: `: v1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior ; t' e. t4 b; Y4 h: d1487496 ADW DATAEXCHANGE DX Changes checkout ownership when override action is set to remove existing relationships" R: \% l: z! ^, M
1487656 ADW LIBIMPORT PreAnalyze reporting false warnings/ }, n/ `( ~1 n- T
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board( Q5 ~: A0 k" ~8 [
1488753 CONCEPT_HDL CORE Import sheets in a design with no change in models: CM_VALIDATION_ON_SAVE variable is triggered1 T3 B) W6 w" {1 y: p! i) {, \
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager8 f4 Q8 M# n- \# r
1490299 SCM OTHER ASA does not update revision properly 1 n( q% _0 \8 ]0 ^1 m4 Y1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer : o; j2 o4 g) F" j% W1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints / P; o% F2 I, J$ j" }" f- [1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working# N8 ` L6 u. J2 C6 I2 ~! {
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)6 U2 l4 n8 \! M7 Y" o7 C
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong& ^$ m- _+ s1 N/ y
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit" [; F1 { a+ ^$ O+ R
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash : O$ {. |: A% l; y# W, c1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL 1 {2 R- L6 R3 i4 `0 U1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs1 I3 {# W6 \9 e% G, A
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size) F5 m( d; U8 C I6 N2 x- u' b
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root ' U v# z) ]) y1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file) p8 r% H( I1 W
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60 0 Q: d6 D0 ^$ v! T2 t7 \1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch ( C. v2 ~# p, Z8 e1500725 CONSTRAINT_MGR CONCEPT_HDL Unable to clear pstprop.dat file conflicts: y! S7 q( u: x7 D; I. T
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant t! J: y/ j9 R+ S6 g1 Q1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out 5 }8 N% J7 Z2 E, _! K4 Y1501294 ADW COMPONENT_BROWSE Missing tabs such as graphics, properties and classification properties that were there before the migration: h" V2 X0 [* M
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL: F, J3 Y1 X! I& B: {/ P6 H
1502282 ADW CONF What does Message: 3 > 2 means? 3 ^6 ]: j6 }: I% B. J1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings7 M* k* R2 v2 p0 }+ B2 L- E( T
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized9 l ~& O K2 v& _ M' L4 S2 m
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary9 i; `; ?# N9 g# s. Q
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin3 n" v" f4 \/ D! y# S$ ?/ g
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving % B9 |! r" x) K3 \/ A, |6 y) J1507497 ADW COMPONENT_BROWSE Switching rows in component browser does not change the graphics of the symbol 5 \# k- j. D, ^2 c# T1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork+ [0 h4 \8 F- t( P( B: F# y0 }- b
1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain - w! W/ a) M( h& ?5 Y1510570 ADW DATABASE ERROR: Unable to check in block model because the part with instance id used in the model is not available in the databa $ y/ i. t7 @ k" F3 l1511180 ADW DBEDITOR The DBEditor dialog wizard shows an incorrect message about a schematic mode when performing an association of a footpri 4 ^# e* R, H8 q5 w% z6 ~1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6 ! G1 j8 @! ]; x0 }/ I" F5 Q+ L1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance1 J: O0 Y2 Q5 A2 |( _/ @
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command. 1 M, Y ~1 f( Z0 M1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working 9 d' Q! W3 _5 s2 J$ c9 i1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor8 O6 B4 P$ j" H! C% P( B
1513092 ADW DBEDITOR Create Footprint Model name is not working properly if it already exists in the local flatlib * t* p/ t$ x! J% ]' ?1513737 ADW CONF DesignerServer from a different network domain does not show distribution data" q5 Q1 U) X+ h# N
1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property% t# `/ M$ ^( A$ [+ s4 d9 H5 x
1514942 SIP_LAYOUT CROSS_SECTION Why is AIR not permitted in stackup in 17.0?# P7 o% B3 i' I5 W0 U) m1 X; d
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly 6 n% ]5 D9 Z1 H1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol2 T$ B! ?9 Y2 K, _. Z) Z" R
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via ; M, a" N5 c/ A# S+ S1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.' ' B. B& [( D( L7 f: \3 w- a6 T1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes* n8 j; c2 f" f+ d7 H: `/ ^2 c
1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer. 0 F0 d, J. h% l# k, _! R3 P1519518 CONCEPT_HDL OTHER Genview does not generate split symbols5 I% g! y. h6 Z
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas ' ]0 Z! _& {; |: a: M1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default3 x% H* Z1 F2 m' c
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net5 {3 F4 E2 Z3 w7 l0 ~& [
1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist 1 F' c6 r) ^' |$ i4 X/ Y1520207 CONCEPT_HDL CORE Genview crashes after renaming ports 8 v3 t) e* M5 _) S2 T2 S7 {) l I1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic 6 s: @$ X8 Z8 D) N1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor 0 \2 ^6 a& h% w9 I8 W5 F- F) k1521871 CONSTRAINT_MGR CONCEPT_HDL CM from DEHDL Allows Creation of Layer Set Name with Illegal Space and No Warning2 L* Z6 \7 I# W# t
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents. " W$ Y& }' W+ J- Z% ?1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design/ |1 u7 b, x) l0 R" N
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash0 w+ }; Q1 k( F) }$ ~
1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated 6 ~) i1 {+ _1 f$ _$ T: Z% q1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine ) s- i6 E# }. ^. Z4 U1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor E/ i/ [5 I! G- i F1525883 ADW DATABASE invoking libimport on an existing DB should verify that the libimp_su variable is set correctly m& Z' r6 k5 J9 D; }, ?
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct4 _7 D2 p1 ~, [0 @/ j. p2 S
1526914 ADW LIBIMPORT Can not import to new library DB 7 k) a1 x& V* a8 J9 ?$ c6 K1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63 / z5 [( _/ p, A9 X$ X. D8 q1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.' - m( L! k$ V+ c. O% N* q3 [4 X/ k8 i" j1528235 ADW DBEDITOR About the rule "Validate Classification Property and Property Values" of Release/Pre-Release$ _3 l9 M) ~; `) F* }6 Z
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes3 E. w7 t" W- q; }: l) R
1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property7 o+ A7 y- |+ l |0 n ^
1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design 6 c0 U- S/ \5 y( |7 s* M1528894 ADW DBEDITOR Lack of PTF_SUBTYPE in the classification prevents Part's release9 v- R! }& ]# x Z3 u0 Y# }6 h
1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net " y! j# L. Y9 s( D4 f* C1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions9 V" c0 t) w- x" |$ W7 a
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file: w1 M# W t" C' `
1530445 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when 'Add Connect' is used8 [/ X( L0 R8 E; A Q
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes 6 J! h$ B8 k. ]5 m: [* j1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup: j5 q3 w) X+ C: t8 p' G* H! R
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr 9 H2 u8 A0 Q* }6 g; a! j' M" Y% j1533543 ADW DBEDITOR Component Browser free text search returns 2 parts when only 1 exists* Q; W+ _3 u2 l) @. j0 l) R: l9 v
1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue - r+ d0 R1 C: d: J1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties . ?5 r8 S/ k3 c) Q5 s1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net ) T1 D) k; i1 _: y1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform / V4 V) T* r% q9 |1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing 'Layout - Renumber Pins': \4 e. ^! g0 Z; m0 @
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor. # j5 z' t2 Z0 W% ]2 \+ G4 h c: o1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run( A+ F5 Q: D9 `/ D0 S% R1 h
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error : r6 g& \* X4 g: F& S* O+ d1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib6 v9 ?; _, a; V( z6 g
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board, r: y4 ~/ [) P' S) `* ^6 d
1542949 ASDA EXPORT_PCB Export to PCB Layout Fails to Accept Entered Output Layout File Name 2 z( B# l% {: m: M2 _9 f, P1543537 ASDA NEW_PROJECT While creating new projects, the new folder name is not visible clearly in the explorer 4 ^" u% h+ }1 F% k1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash, f9 s2 Y a4 t5 K6 N
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash ) m: V! ?6 w- f4 U u/ v1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked( _% n5 z1 c! x/ X- J: q
1544856 ASDA CANVAS_EDIT Edit > Find places the process (UI) behind the SDA tool. + B Q# I0 ]1 Q) M" B' b) t1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with$ j& W0 F; [) R3 S7 O2 @; w
1546062 ADW TDO-SHAREPOINT Failure to launch TDO Dashboard, need to update error message with more useful information " Q c% S9 V3 n; a0 s3 I. v1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted' . b6 ?8 f; }( x0 f' G1549658 ADW TDA Unmapped network folder in TDA P; m: h; T5 W6 ?1 E4 A& Q& l
1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols' J/ O* o/ G3 e) `; @
1551635 CAPTURE TCL_INTERFACE GetSelectedPMItems returns error for design cache objects 4 s% D5 y* U) L& c* |6 }& ^8 w2 I1553027 ALLEGRO_EDITOR UI_GENERAL Beta - Allegro display freezing very frequently - canvas not resposive and turns white.9 `( H4 B! r; Y5 M0 E9 h- s2 }
1555246 ADW DBEDITOR Part Copy As does not copy AML and reliability model relations. " a0 z$ V$ c& |; D" r/ x- l# Q1555254 ADW DBEDITOR Loose focus on Free Text search Window removes the text.& Z# D7 g" |! S: M2 q
1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon+ |1 ^ t7 i' _2 H
1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export: t U1 }' V6 J. j! L+ A
1580571 ADW DBEDITOR xml files for released FP and padstacks are left in flatlib area. + t3 b/ ]6 n/ _7 S! y1580580 ADW LIBDISTRIBUTION list files are not getting cleaned up for custom models if they are purged. * g& R" ]( a7 w$ P! c, l4 n) @" C1582064 ALLEGRO_EDITOR UI_GENERAL User defined menus not working in 17.2 4 Q! q0 X& l& I/ p1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes . H L# I# u; ^' q1582856 PSPICE MODELEDITOR Getting ERROR: [S2C3471] Base part library does not exist when Export to Part Library, though olb created8 w a# u" ]1 t4 v- p* J7 q
1584719 TDA CORE Caching errors coming for a board ref project while doing Block update3 t4 X3 b; X. \
1587045 CAPTURE IMPORT/EXPORT Unable to import PDF file0 W- T6 G5 P% \! a/ m
1587259 ALLEGRO_EDITOR UI_GENERAL axlUIMenuFind not working correctly for the 'bottom' option. J, G. j& x9 D% Z3 D4 _/ x
1588736 PSPICE MODELEDITOR Model Import wizard says "Invalid configuration" when lib opened in Modeled7 Q' m3 C& k$ k0 l1 X- |
1588742 PSPICE PROBE Browse icon is missing from Pspice File > Export > text z( Q7 l, U- q+ ?+ D1590006 ALLEGRO_EDITOR UI_GENERAL PCB Editor 17.2 crashes when multiple browse windows are opened7 Y2 T2 K& \0 |# ]: {
1590597 PSPICE PROBE Problem with the adaption in the Probe Window icons ( \( r; l6 N( b. L1591264 ALLEGRO_EDITOR UI_GENERAL Film order in Visibility View sorted alphbetically and does not match with the Manufacturing artwork 2 x M q: I5 H* ?0 v& W$ b1592089 PSPICE MODELEDITOR Can not get PSpice DMI Model DLL while using PSpice DMI Template Code Generator; t& N) D2 t; \- U
1593436 ADW DBEDITOR new Model type form does not focus cursor in window, User must select the Model Name before any text shows up 7 n3 G( q W5 V; ^4 u1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified" Q$ y* m8 F, A: U4 G3 A0 N
1595987 ALLEGRO_EDITOR PLACEMENT Subclasses not getting updated in Placement Edit mode [! d W0 l, F8 K+ r/ I2 ?: \0 O
1596162 ASDA IMPORT_DEHDL_SHE Importing sch pages from DEHDL imports the block as well & q! s& x% M, f) N1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names( C- t3 J! Q$ Y- L
1597406 ALLEGRO_EDITOR SHAPE Dynamic Shape does not void the traces and voids open areas2 _$ L" W. K7 s2 s) t; i0 Q2 @/ ]
1597957 ALLEGRO_EDITOR PLACEMENT Quickplace: placed and unplaced counts not getting updated ! I: W+ c0 Y( }7 |3 v) D1600194 ALLEGRO_EDITOR DRC_CONSTR Update drc command changes the amount of DRC count when using 8 threads ( [ L- ?( }$ N1600800 ALLEGRO_EDITOR GRAPHICS LINUX 17.2 operation of Update DRC is not the same as Windows – graphics not updating% C* ~9 B, f) `0 @( |+ m0 S
1602605 CONSTRAINT_MGR OTHER OrCAD: constraints not getting saved 9 Z- {; a& Y- l3 z$ }: ]5 b1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool. ^1 c+ Z$ M* Q* j V$ p8 M6 V
1603377 PSPICE ENVIRONMENT At Markers Only option does not generate .dat file ! F" R$ [% p$ \4 E Q6 _1604166 CONSTRAINT_MGR CONCEPT_HDL Audit ECSets does not work from 'Referenced Electrical CSet' column header % `5 O+ `* L8 P6 q1604741 ASDA CANVAS_EDIT tcl console changes the present working directory (pwd) when you open the proj preferences & close it. + x5 s8 F- \9 N% V$ p: x/ [5 Q* e1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard5 j6 g4 m) o0 W2 w1 V
1606861 CONCEPT_HDL CORE Crash on Linux during Generate View7 r, Z8 T9 y) i+ n) i
1606917 CONSTRAINT_MGR CONCEPT_HDL Importing tech file in DE-HDL Constraint Manager is creating a duplicate 'DEFAULT' cset8 ^& w/ C5 {% {+ i3 ~& _
1607157 ALLEGRO_EDITOR INTERACTIV Edit - Change allows lines to be copied to Cutout subclass, but that subclass requires closed polygons 6 Y2 Z) D4 n% k1607330 CONCEPT_HDL CORE Variant view schematic PDF corrupted with attach_props set& c/ V \% n; m! |8 ^
1607568 ALLEGRO_EDITOR NC Allegro shows wrong drill legend Top to Top drill.' B5 J0 r. \, l0 Y' H7 s
1607986 CONCEPT_HDL SKILL cnGetSetupProjFilePath skill command in SPB 17.2; V* ]; H4 u- M1 x
1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error. B o- U# ~- k9 p
1609400 ASDA CANVAS_EDIT RMB > Assign Differential Pair should be grayed out when a single net is selected/ e. }0 w+ W O
1609809 ALLEGRO_EDITOR UI_GENERAL Crash in Allegro PCB Designer version 17.2-2016 on Linux ' d5 E, c$ F- ^ g6 F1609856 ALLEGRO_EDITOR ARTWORK Embedded paste and soldermask showing up in both top and bottom gerber files. 1 b% A: a5 R! y, g1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only5 A6 ]) @! s2 a) e9 d5 X- I
1611226 ALLEGRO_EDITOR SYMBOL Allegro shows crash message while saving flash symbol.6 @; G/ N/ T+ l/ H" J1 O$ S
1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message. $ }- f4 S B/ P) g# A' E1613123 ALLEGRO_EDITOR SKILL drillType Attribute in Skill for Ovel Drill return OVAL SLOT in place of OVAL_SLOT & P7 E! x" k$ M' f$ B& V/ E1 G F! c1614000 ADW LIBDISTRIBUTION lib_dist does not complete and does not allow to delete the .lck file./ Y8 c5 j" w& C1 U9 V9 t8 ~
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp % G- ]% \5 E9 T1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error 9 d9 g3 x% ~3 L; ^9 M! m8 m8 g5 z3 m1616235 ORBITIO ALLEGRO_SIP_IF oio2sip import doesn't map layers correctly 3 N6 z$ P6 L# X- F. U1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update ( y1 z) n! {1 L0 w9 W0 i8 C1616733 ALLEGRO_EDITOR INTERFACES Genrad output no longer working in 17.2. Gives Error: extracta process failed. Command terminated* L" y$ _" P: X
1618751 ASDA DRC SDA is showing Zero node Net errors when we run DRC checks, but user had RETAIN_ZERONODE_NET 'NO' in Site CPM file.$ }2 A$ t' S1 \% _. Z( B( [% K
1618797 ADW FLOW_MGR Flowmgr fails to execute command & u- c7 G" ?8 R" }+ B1 |1618930 CONSTRAINT_MGR INTERACTIV Hovering over row column cell causes the application to go into a not responding state. ! t1 r$ k- S; o1620350 ASDA EDIT_OPERATIONS Uupdating version for a connector pin looses the pin number % H/ x1 F! |9 J! @% Q0 n1621963 ASDA SELECTION_FILTER When working in SDA, I am able to select "Pins" on all parts except connection pin symbol./ E5 p, ^( o$ h! I* ^- k! c
1622715 CONCEPT_HDL CONSTRAINT_MGR Extracting a XNet crashes the tool . M- y+ w; [6 `0 e W$ Z1625209 ASDA IMPORT_PCB File Import from Allegro shows board differences( Y, X( ]' G! F; T5 _
DATE: 07-28-2016 HOTFIX VERSION: 0030 l! a7 }. l$ @0 z) Y8 ~
===================================================================================================================================# r% W7 Q) U" r$ b
CCRID PRODUCT PRODUCTLEVEL2 TITLE3 }: Y+ g4 I7 @. Q+ M
===================================================================================================================================8 V4 A) J8 a8 m# n
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result" k, W5 t; B; J% q& I
1461626 CONCEPT_HDL CREFER CREFER shown to each instance of block pin though net changes * [, j1 }, F. N1472456 CONCEPT_HDL CORE XCON and design are out of sync 4 J( |& y3 ]5 ^% P1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears 8 d6 N6 @% K6 i: _7 Y3 { n% \1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066" f2 y$ x/ {- q4 ~
1560102 ADW FLOW_MGR 172BETA: eval in command string does not work/ o' c+ u0 {7 X1 y, t
1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View' d& l3 v! k: Z% Z2 Q
1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly6 i/ W- U$ x I2 A! h0 A) w( W
1578876 ADW ADWSERVER Component Browser crashes when trying to show details on a part number 3 F4 J% o+ G' z8 {! V. T5 o1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found0 ~7 |; ~2 X' O, z3 P
1582863 CONCEPT_HDL CORE Generate View creates non existent ports ' A5 n; s, Q L5 j/ l! H& c5 o* K* V1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window. 9 Y8 a: A U) }2 ~$ R( z1587018 ADW FLOW_MGR Project Update at Ericsson in ADW 17.2 asks to specify flow name. ' y& Y0 v% l/ L$ l' E1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties1 d0 [. _4 i& U
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed $ }7 Y h' d( O t7 B1587718 ADW LIBIMPORT Library Import Pre-analyze report is not being written $ p( ^. D; ~/ @( { O7 {% N- k1588197 ALLEGRO_EDITOR INTERFACES STEP output fails when External copper selected on Win10-17.2 ) b' j+ e# w: T! X! a$ P4 m/ [1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message" / Y( g5 w; Q& |# C, C" P1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component9 |2 k, r2 V- |3 r' U$ J
1589318 ALLEGRO_EDITOR DRC_CONSTR Via to SMD Fit DRC between Embedded pin and via which do not share layers" a9 w2 Z' L2 {8 f
1589979 ADW FLOW_MGR Design Name change in EDM 17.2 doesn’t reflect in flow manager in same session of project4 c7 G& f* l ~# e' K8 b
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior% K2 P/ R5 r2 e+ H5 j8 g
1590639 CONCEPT_HDL OTHER DEHDL crash when importing design ( v$ J/ L5 P1 b: F1 \& U, x8 {1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM : m! F4 y. B# {+ D1590720 ALLEGRO_EDITOR INTERFACES Text Size Parameter file does load names into the text table# t$ N" G9 O% t5 p _
1591070 PSPICE PROBE PSpice crash while evaluating measurement from trace>measurements : l1 u8 R! o: b- [4 ~+ M1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic; y! h- G3 I/ ]9 f! X! W6 t; _/ O
1594240 CONCEPT_HDL ARCHIVER Archiver is not able to change the permissions of the cells archived ) M5 [! ?- q/ h: q2 C* P- H( d1594416 ALLEGRO_EDITOR PAD_EDITOR Padstack Editor crash in 17.2 ) \# K2 H- R9 R) E% g1596615 ADW DBEDITOR Component Browser didnt come up to search parts, also the database editor didnt return search results 9 {, z' M9 g: a6 I# S' c# T1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save& G7 f* ?6 \! G l% D
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor) `& Y: {6 o# |; G# J0 R
1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI) q I W1 I( @$ A
1598629 F2B PACKAGERXL Export Physical crashes7 D- y8 g0 U4 Z' I% w. C8 H
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.! s" l5 \5 M; |9 A
1599744 ADW FLOW_MGR Few flow manager buttons are not working in EDM 17.2. i3 p4 c, v1 ]6 h6 r8 ` y& B
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time. 0 r- A: B0 `4 s4 g1 n$ E1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group ' E- ?0 j) W4 `7 O5 k" }1600618 ALLEGRO_EDITOR DRC_CONSTR case sensitive issue with Physical Constraint Set ( m( W7 c( N$ m, s( e! @1600914 ALLEGRO_EDITOR INTERFACES File > Export > PDF shows the shape as unfilled.6 [3 v8 t/ {6 g& x( t
1601165 ALLEGRO_EDITOR DATABASE Thermal Relief is not added for Rounded Rectangle pad + D, q% E7 w7 b; t+ ?+ d1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol & o/ T2 l) a3 J- x/ ?( N" @1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name. % l7 A/ V5 \' c" |/ A" G! w. T1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project 6 q' U0 N0 e! ?4 n0 U1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command ( H1 }2 s* l7 f9 u1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer. & \* h$ o6 Q$ x7 K! d1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error0 e, _3 \) @3 W6 O: |
1604746 ALLEGRO_EDITOR OTHER In 17.2, there is a discrepancy in layer data when importing extracta files into their Mentor Graphics extraction tools.7 P) o, C$ Z2 E) g6 @
1605322 ALLEGRO_EDITOR TECHFILE Cadence SPB17.2 Issue - Long duration in Tech File generation 2 f3 a& U. Z7 SDATE: 06-31-2016 HOTFIX VERSION: 002 : ~9 \4 W6 S( S j$ B( U( r6 f& a2 c3 s=================================================================================================================================== 3 |0 N+ w4 B- G8 u7 mCCRID PRODUCT PRODUCTLEVEL2 TITLE3 F: R) r, F8 H L$ f
=================================================================================================================================== v: t: R/ S( g" s1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets# W- _$ `, q& ~: ^1 u
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package+ J+ x$ t; L3 ~, i0 S& d% N( D
1481802 ORBITIO ALLEGRO_SIP_IF import of oio to an existing sip offsets the results incorrectly7 ?6 d. q& z. e+ G. A: ?5 ?
1518957 APD SHAPE Shape void result incorrect) b& j u5 v8 @( ?* [2 d/ ]: F
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error; V3 w7 v7 \" j1 J
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly( b( Y8 l! n$ j; w
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols. 6 L% V* J5 A2 C1 u- H* b1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.( g9 J& v4 W" }0 f; j4 B* W
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.) 2 `4 ]' d& \7 h q1 ?1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set & M3 b+ ]/ {% |7 A/ |( K$ x1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None' " l" H7 v! {- w4 F& c1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library* i6 s) \% r( U2 Q+ f' [- R0 Z# ~
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG $ o5 H* t2 _7 H# d |* |7 g5 J0 }1 t1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets . @4 K3 p3 Q* L; a( \% m1 `8 W8 C1559552 SIP_LAYOUT ORBITIO_IF device offset in oio2sip translation 9 x, r6 z* S3 H6 M1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open 0 X; C6 b+ _5 m1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters - k4 b7 _1 ~7 X8 }1561501 ORBITIO OTHER oio -> SiP refresh seems to hang 8 j4 ]+ B: w: B9 I- w1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC ) |2 B8 i0 _0 c/ B7 p2 j" Z: t1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins : z6 l4 O/ [* K# C% G( F5 {8 s1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas 3 |# a. |3 _7 ]1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions 4 ]: a; f( h) x' n0 S1 P1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete9 |* K) q2 i& l' X- i
1566942 ASDA MISCELLANEOUS SDA172: A lot of files in /tmp/ on Linux6 |: w9 U; Y* y" I9 s
1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape. 0 k5 C p1 \" I0 y: H1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct) A2 |% l1 a7 i4 B1 V
1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window9 [" \" i; d- ]- Y' Y
1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.' , C1 X1 C& g2 ]6 T1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed+ ]1 F* p7 w" p# x3 N, S, U
1569394 ALLEGRO_EDITOR SKILL axlPadSuppressSet( 'on 1 '(via)) not working on SPB17.2 ! ^1 A' C+ K* z0 C6 y" s& g* T1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*... 6 p$ L; y; j5 p9 ^- L. Q5 k: c1570398 SIP_LAYOUT DATABASE Diestack layers can't be deleted if there are unplaced symbols in the design5 ~1 J) B6 r5 A- E, f' H
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager0 c, i" V2 ~: D, N
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short i& K+ k4 o5 \1 N: a, S* n
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property # d: `2 ~' S9 L5 X. ?( l. e1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only1 G9 _$ S, p" e4 k) U
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display9 r. ^! v C) y) G
1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry 4 P6 O+ C; V' ~& q6 _5 T2 D1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET) M: I6 q* j( |! u3 a1573625 CAPTURE PROJECT_MANAGER Toolbar customization is reset when Capture is re-invoked in SPB 17.2) S/ H. ^( T2 l1 [" m, O v/ S
1573755 ALLEGRO_EDITOR CROSS_SECTION Switching between plane and conductor changes material in Cross Section. 5 c; C. P; K7 v) J8 o$ c1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file' v2 w7 l1 h& g# {8 a' J$ X
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings0 f1 f1 D9 s) W4 Q1 \
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log' $ u5 W7 k. n5 `7 n% P" O$ A1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure8 O) D; s" I" G# D1 _/ r
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files ! J$ q; G* t$ \0 {3 M4 _: V+ J( d1580891 SCM REPORTS Dsreportgen crashes on different scenarios : S7 h9 N" ] L0 J, D. [. ?& @ |* Z1581254 SIP_LAYOUT CROSS_SECTION "Apply" or "Ok" crashes XSection % {- R& F3 S" Y! f" V8 \, t1584957 ADW FLOW_MGR 17.2 Flow Manager, JavaScript - Tool Launch Error4 X8 j$ ?8 u' N, k* F) g8 m2 C
1588823 ADW FLOW_MGR UNC paths have stopped working in Flowmanager in 17.23 ~+ q C0 t" g, K
1590064 ADW LRM EDM 17.2 gives LRM unnecessarily. 5 p4 ?/ J3 R9 G2 y1 XDATE: 05-06-2016 HOTFIX VERSION: 001- R; C; ]" p8 B0 _0 i
===================================================================================================================================( y) X: } [3 g$ {* e- M9 m
CCRID PRODUCT PRODUCTLEVEL2 TITLE 9 X2 ~( K0 [5 B/ ]# c3 i5 M+ b===================================================================================================================================2 ~+ s6 M% G: b. `( t& @/ }7 Y" \
1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output + L) U2 _& o: F9 Q7 d- }: F/ o1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group ( |6 O2 ^/ y: p% G: g# S) Q1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines + T! q* Q# Q/ Y0 L1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail2 `8 ]# {. s6 P/ P7 G
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol5 }9 q" ~4 S% e9 m: G7 i( f) Y- K; I Y4 V2 ?
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser9 i3 A: |1 ^7 f$ ?- S
1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing 1 |5 H0 u- x0 }3 b% a6 r& q1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager 7 F# Z4 X$ a% u. d) {; _5 F8 S1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute ) m: k2 w ?; x1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals: q( |( |8 k9 J. w/ G
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes' C0 ^. g Z" w$ Z
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork ! J( N- a! u: X' w$ c1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed $ r- M' N6 b1 S8 c1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled. K7 V; [ X) F# v, z! |/ a) w/ B( \1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder. \! [; X4 Y% \' `" S) J
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols) R2 x& ^4 n1 } q
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work! s9 d0 T: y6 P! [( o
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file# H! x. l6 v& ^. V* ^6 p
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design6 P, f. `' N7 q9 G' C5 }
1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license) F3 j }' A( g; W& {7 a
1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork $ s; N( T% V, g1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message & G2 g3 T6 E9 O- O v+ C- b. B1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system % [: C# H% R! [4 X: h @1 ^' q m1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected. ( K& \0 E9 D/ ]1 x$ Y1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol' i, e6 m- ~- P# B( @
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file% A6 y0 n5 R4 S3 ~6 ]
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report; E9 M& }; @% q7 a: _; ~
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines ; `& F. i. r( G- Q; c; w1549662 ALLEGRO_EDITOR OTHER Import Parameters Path' fails if parampath does not have the current directory ('.') set ]7 L1 U) q; {/ N
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts$ e! q& w( @/ d/ Y" S0 U L
1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems 4 b3 Y! R; G6 M1551713 ALLEGRO_EDITOR DRC_CONSTR Hole to hole drc between Via and pin$ j8 X) p$ c ~2 |. a0 j3 o
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro ) z6 c- g/ z: |( |3 T2 @2 m, y! w; ?1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups # E, ~: N5 ^: e' }3 L. l; _1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons % p7 z% s8 V0 b6 r+ ?4 \ d8 Q1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes 4 U. S7 z$ g) x8 X+ O% a1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted 5 w$ g0 [3 p4 a3 Z( V& D! z1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die! @8 H6 Y9 G+ x9 N; G3 p8 r5 s
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM+ }: A8 S# h- A! T
1561077 ALLEGRO_EDITOR INTERFACES Beta - IDX User Layer export fails on Linux5 x& d2 S3 d5 R2 I( _7 a
1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error6 ?. x. U) G5 P+ H/ C4 S2 } J
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film.# E* m: |! H1 w7 g0 D2 L
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