标题: SPB 16.6 從061到071版的補丁內容 [打印本页] 作者: jacklee_47pn 时间: 2016-6-29 12:21 标题: SPB 16.6 從061到071版的補丁內容 DATE: 05-28-2016 HOTFIX VERSION: 071, A/ d& V" I9 l& M: o# @' E
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=================================================================================================================================== 4 r* h0 E, J7 F% q6 A1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets - a7 C& q6 Z* J$ q7 ~9 `) J1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package% W+ f! r/ w2 ]$ z$ m$ s* _
1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser ( W) l. `0 S2 x1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly+ J4 t' m0 G, _0 }
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.. @0 v, z0 U! m& u
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.% ]0 o- T' b/ M5 i9 C8 A: T1 _: f7 v
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)$ Q) ~, d% l$ O; I7 E
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set $ v: \' v6 c2 M5 b% w8 ?0 G1 j1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None' o& |9 H& O$ n3 P6 M
1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library# \7 t* S$ P. @6 I" w! N3 q
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG 4 f7 Z' G$ H" X7 |* r# b3 S' d1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon& x. p+ l0 g8 J: b- Q
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets + k; y3 Y7 s0 A2 z" g1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open ( g( g$ F! q1 C1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters - h9 h% H7 ~; x- B1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC+ S. f. z: A; Q! B. h& F8 a$ {( N/ Y, t
1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins5 h: C% a; u6 a
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas, K5 x& H% L/ @# y) j+ b4 L/ ~3 N2 C
1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions - ]- y3 A$ @* T5 `) }1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete $ _' ^" w0 {% `4 R1 j1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape. D* T- j: G1 `2 l& P; s
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct 9 _9 a( b( C5 e1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window - O7 O% i0 e: h$ V8 N/ w1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.'/ v& @$ Q( z9 n4 \* x: L: ^( t* z0 r
1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed ! c: Z+ N: u" j W6 ?& t \- W1 }1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*...; }0 [0 O* y! E
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager; z+ w0 J& j: i% Y
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short) C4 q+ I" j4 U
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property * W! u* c; U# v! @1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only 8 e- v6 L0 y6 \1 i. |7 @7 X1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display: C: r4 t9 }6 p5 S7 b' k* ?
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET) O L! a: Y7 m: G W
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file1 z$ V; j8 s! ~$ s2 `
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings2 M4 @; j) u' M; K$ h+ Z' W
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log' 3 G' N) T9 q- j, ~* j1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files / ^8 y2 `" Y% m ( r. N# n1 N3 j& f" nDATE: 04-22-2016 HOTFIX VERSION: 0691 N: ^3 X0 s6 Y2 e
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1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output4 i$ u ^: S" z9 s" _+ i" }
1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode W; I3 s: k; o2 v" Q" r1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail : U" }' x- L; G) j1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol 7 a5 V! C) x6 N* v9 p3 B1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing5 R- u5 D2 R3 [2 K5 a2 v
1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute# |6 d: f3 E, n+ u
1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals3 X y1 U5 a5 `( B
1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork* N$ I5 h) f& w0 ?/ C3 y% h
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed 2 V8 G! B0 l# B1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder # y* O) `3 D6 ^ Z1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work % c' S# L2 m; G1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork 3 x, X* V) c# }, U# u6 Z1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message 7 a* S4 F5 j, `9 h' a/ l, n/ k1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point % [, r8 Z. y) d$ O: ?8 K* ~) ]6 g1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines 4 K. z) y% {) D5 d/ d4 Y& {1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems+ Z+ w1 K6 D! O6 L8 U, g( ?
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro! R1 \0 P' m* z$ ^& E% r0 k8 i$ t) z
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups. N/ v. e* f! K/ }+ Y# m* n
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons + W: y; C8 T5 t2 C" d1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes2 A. R9 v; Y4 c. y' E2 t3 i J7 b
1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted+ N- L o7 b" d3 b# ~
1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die7 I7 @5 ?+ u; H9 K) |+ b: x8 o9 U( H! B
1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM ' Z# u6 Q X# Z+ d8 }1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error5 c6 G8 [0 e( [6 A/ Q4 Y& w. C
1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film. 7 q4 @: c+ x$ `5 v6 s2 q" m2 m3 U' ?4 M) C/ |% J w8 B
DATE: 03-23-2016 HOTFIX VERSION: 068" K' f/ g; n* p) }& H$ m
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1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short & {$ L4 @ N7 ^3 ?) d* c1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system 7 K5 z0 i) q! I1 t8 A# T1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected. 2 w N; m7 w1 m1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol$ L; D7 D8 U; g- q, B, ^
1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file: M: [$ ?; Q6 C9 s Z
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report 2 m; b6 N" v& Q" y9 X: J$ o4 M* M1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted'# I k7 ]4 @6 [4 g: l. I! l
1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have .( l4 L: s4 t3 w* |- G1 r+ d
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts : Y4 k* g: ?9 l8 [% c! I) B3 W1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols , ^8 r, e/ r+ F- b 7 Q6 p% i0 t- Y, [7 P& s( v, lDATE: 03-11-2016 HOTFIX VERSION: 067 - g. S0 B' A7 ]6 `( x=================================================================================================================================== 6 a# M) x& R$ H* }3 G1 w1 `CCRID PRODUCT PRODUCTLEVEL2 TITLE : |! d) {* B% u. r0 A===================================================================================================================================( }+ v# Z" ^- W
1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group6 O0 b6 Z2 \+ L" C" L: \0 B9 w
1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines* F* G: Q1 p( V4 g" d! ?
1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error' L8 [. V: ^7 p- w0 P
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.' 6 j( a$ z% @. z( `1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property % H+ N" Z" ?" \1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net 4 x& V7 \7 B- S) R1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file 8 g( W( Q9 _' {! d. G+ o1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes* Q8 y* T* A9 J
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing% G) C9 k7 w/ O5 s0 A: l4 o H
1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager# j+ m2 l3 q/ w. J2 C/ n
1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters 0 x: d1 L& s! m; ?1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties& Y( j. L$ z s" Y
1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer( J* H2 n! G/ x& P
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net7 ~( i j1 N( Q7 i' S; ^0 F- h* n* T
1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform % j7 ~9 A! Z& b8 Q6 N1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor., {7 J( b6 \" R' `. K
1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error ~6 ^. B) i2 w* ]
1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled. 1 G, y, Y" ]+ p. D1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib9 O) V: C3 Y! j! \- L; R1 s
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines0 w; l2 A) U5 t
1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols7 D9 O8 {/ u6 b2 Y5 S
1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board2 n. j6 O% L. ?7 O: m
1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash" H, t" |; f# _ w2 X i
1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash t5 T8 G/ J0 r3 ]! @3 T5 E1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked9 B# D; |) u. D7 y# R
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions. 1 M: O) R+ X* N8 O. @+ d- l, i1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with 4 t h. N3 B: W+ L7 `/ [- ^' [ d1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design # p- q; s8 v) R( U) i) Q. i3 e3 X) _ u4 c
DATE: 02-26-2016 HOTFIX VERSION: 066& J( g9 b; b, }) n6 M
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1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated1 R( Z- l5 D5 E1 @, D
1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes 2 Y$ P, J8 h. g* V1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions+ v2 S8 T3 [% ?1 L" x+ B0 l
1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message6 h" _) e- L0 y# c
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr ) E9 B7 L8 W' G2 Y1 o2 r% k1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue7 ^0 {' B6 p7 g2 O2 z- `1 F
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer 0 W" X, ~% Q* S3 Q1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins 7 R! |; e0 t' p7 {- ?1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run2 w! p. A( h: [5 V! X' C
1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed % W% _- A5 z3 `+ r% J$ [ * F" W' l6 v6 }, S# n0 UDATE: 02-12-2016 HOTFIX VERSION: 065 ) \& m! g5 |3 e& o/ ~=================================================================================================================================== 5 g5 }9 w* R' XCCRID PRODUCT PRODUCTLEVEL2 TITLE: U' ]& S$ j1 `5 P7 C4 z! u
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1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working; w, |0 R' ]1 l( r
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via" ?5 n, P3 d: j$ ?. X' z
1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit4 e3 w2 k" ?0 ~9 Q. `1 `* g; A6 B0 c
1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents. + w {& l8 d# u/ q1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms 7 S9 h- y- K, u, m5 u' I1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine4 V3 C/ U+ \3 _$ z' Q( D! K- E
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger % ^4 o& m" ^' Z1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design : q. Y7 i# |6 e% D) q Q* A1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup 6 r8 o3 l& |2 S6 A* T! s1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.2 S" L/ r0 ?( [% h
c% h) Q5 B0 E2 Z6 a+ mDATE: 01-29-2016 HOTFIX VERSION: 064" e+ m4 o0 |' j- c) z+ d! R
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1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain& B5 m* E( o5 P, K8 x3 c
1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF; y% ]7 z, v9 E4 [. y/ ?* L5 E
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.; S! i7 [; m6 l4 p2 c! @. x
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected & C, R1 z0 d8 t; o. L7 d1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.( ~! \1 t! @4 n: s% p( [
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default' L: S# U6 w# Q8 h
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas 3 }( T6 H% i) @9 I% q0 w- [1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net $ |& B& q- D3 x1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist" J8 _* _5 R* d! ?8 z4 t
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic 9 Z! ~6 g$ L& D0 c1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor6 k+ Y$ Q g6 ~5 S- A
1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file) A% Z1 g( K) L
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design * R: P1 z: T3 M) [( r6 n8 n1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash 7 ]6 `$ e, N; Y; p( Y$ U1 _0 z3 N6 p# t1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes* Y R6 Z: A' L+ f) G; J) `
1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor/ T6 X" T: S% u5 w- ]4 W' d1 X" d
1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct ' G: u5 v, w4 e" ~: e1 h. d1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63 1 b5 y4 m' s- ?+ q+ j1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes! ?3 r; w) @, V t q( U$ q( F
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DATE: 01-15-2016 HOTFIX VERSION: 063% r0 v) N. I* i2 \" u' P
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1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region # c$ x# g5 D# z; q7 L; e1 Y1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs ) ~! H! `! O0 p+ l. c u1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs/ k( \% B5 M$ Z; @* m
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant- F! `* [% M/ Q2 A$ |
1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork ^! c7 x* w+ y4 j6 E, M. S
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6) s3 i) U# p( z; e6 A
1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance( G% |, U; ]4 o' ~& G6 i# }9 G
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command. ( L' `6 N# D5 Y I. B& o4 w1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly. 3 u5 U2 c/ h8 |/ u1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out' R5 L( K. w6 X+ H8 R6 G z
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor 7 ?$ x: y: [/ u6 ]" m# J" ~1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property" [& u1 z; G t5 E
1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly1 [+ g- j! f7 _; x% ~- P
1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation: Z& e# m" L. m* p+ P' \2 y4 f
1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol$ c) C6 `1 I9 Z6 r" t* ~/ y
1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.' 6 t( a) }1 J2 ~3 y4 g1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes+ G! B( ~0 c$ N* P5 Q, N0 E
1519518 CONCEPT_HDL OTHER Genview does not generate split symbols ; c; ]7 ]) r& f+ |3 `1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas6 G/ l' v% E" ^- Z% | k
1520207 CONCEPT_HDL CORE Genview crashes after renaming ports8 k: i" L5 M$ N+ J; y1 M# G
' ]3 u4 d+ R1 f, L# Q5 S- s' RDATE: 12-11-2015 HOTFIX VERSION: 062 u; I( v, T1 x/ C; {% U5 Q- j=================================================================================================================================== 4 U7 m0 g7 m; s0 l/ UCCRID PRODUCT PRODUCTLEVEL2 TITLE. X. O5 x" @, ]$ k0 i; T
=================================================================================================================================== . i, ?1 w6 ~* s7 r1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output A- Z* a4 ^1 s* x6 O. v; r1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file: v0 _. z( H% T V3 G# B/ b
1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option # W+ S6 Q N- }9 W. Q1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC ) S- m3 @& H$ ^5 r8 Q1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view% w4 s! m0 c- U2 B7 X {
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked 4 r! k2 z# G+ e' S, e; C4 r+ ?$ l7 K; G1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits. " c, E8 k4 M& h1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file 6 h! V2 B2 @! N, Q" w) [3 }9 z1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding 5 |1 V, K4 b; a! N4 F1490311 SCM OTHER Block Packaging reports duplication when it should not& k' \* Q& H0 e7 a
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes' + s* f4 Q: E8 i9 ^% b1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message, D3 Z6 R. L. M
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation) 8 h, G1 | C x0 u1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit! v1 q5 j2 z4 c' W0 Q( ?
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout / @. i* B: b& o, U! M1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT ) ( B9 B4 K; ^7 a3 X( [! G2 |1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types( ~( V F6 @% t: u# j# [
1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape' ; w% p( `2 h; e2 S1 a! ], _1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly! n# m' T1 l' o4 d
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this. Z7 Q9 [3 W. r0 W0 X8 i, o6 N
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch: q4 V/ t& Z1 X$ [8 p6 g! ]8 T; U5 S0 ?
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default, P% g. L9 O# T7 ^$ h
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts 1 r' V6 I) D& X$ v6 W* k. G1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks; F0 d. d. g2 V$ |' p. T; I; M4 Z
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out7 f9 I u" s& }, G6 \8 k% E
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF# u! n8 j5 z2 O% c4 K# v2 r8 N# k
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form; R6 G. S6 v# `( B) L
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL2 N k: Q w E. L- d# `
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings1 \" ]7 j9 c+ n% _. I9 r
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location ! X% [0 n% j4 h4 t1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized # n/ z$ E1 j& U0 ]6 [5 n( r* Y1 ?1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary5 N+ Y4 U: d7 y: L0 O* T* {0 W) S# d
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items [# E( p% N# v1 l3 F; d# m/ [& H' L1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin7 a, r5 Z8 m4 S- q) X
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving # ?, s2 s2 Y6 n; D- Y1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None: W7 G8 _. E7 b y% p
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DATE: 11-20-2015 HOTFIX VERSION: 0617 U# D: D3 ?; J& e6 U
=================================================================================================================================== 6 X! [4 s$ a+ [8 [$ M( T/ `% U! ]CCRID PRODUCT PRODUCTLEVEL2 TITLE A6 ?4 O2 `* B
=================================================================================================================================== 0 E5 u7 j1 P$ P' ^ c0 @' z! Z1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value, ], d7 K# i& f; I% a. `
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init) I2 f' k L4 w: o
1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only) I0 T% G' r& ^% t
1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle # J% W+ `! Y4 K/ L: Z/ r! k) n1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins* U* w$ f5 M+ Q# v
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set7 {, u5 j2 c! ]! H2 Y# P
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin , i- R# H. n5 d: L4 N1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools + J4 d7 f, |' x1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename+ y) ~/ E# X4 {& N0 g7 ]
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets B! O" }% p8 r) ? A0 Z1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL" r' B4 L, ~0 W; i. h: ~% D2 N8 {! }1 G2 d
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy 3 X( o0 G' v/ |9 [9 H0 V8 d( e1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable4 {3 `7 l2 z$ N& H6 f% b
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets : Y7 |3 n% d2 A1 ]# r/ q1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice O) O. B: T. M% I$ Q1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues$ `( ^) ^7 D }9 z
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only # |% x8 j; V% v* H0 ~& n1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project- A0 x& E2 d9 e3 I
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.# J8 c2 U# n- `5 t2 V( t% q
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility % p/ N6 i8 k% C' X) M! u1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems9 C# g$ ]' V8 ^" b; F: C" M0 l
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported 7 ^$ u/ z! ^ d( }5 E1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior+ _4 o% j0 u: l0 u ]! p. u6 x% I- M
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board 2 N( {$ }: r- V$ w1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager / o) V, B, p9 H1490299 SCM OTHER ASA does not update revision properly ' d8 i# A+ q$ R- U1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer 0 |3 W) q/ Z5 H {0 l1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints7 K# y( l: F& {! H" f
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working 8 x, F$ r$ a q6 S, n/ Z1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong) }6 i* L* D+ N4 r( {$ A
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash 7 r) A0 E/ K% L1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL/ v7 U* l( e7 e% s& ~2 M, H) N+ _
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581 5 z: N2 o; h4 Y f, q5 T1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size 4 v, f& m( \9 J1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root+ e7 p' e* }1 `
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file4 K& s) t, h4 y9 m; T7 w
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60作者: jacklee_47pn 时间: 2016-6-29 12:27
截至目前 071 版本， 1 X- B0 C% l* V7 y8 V3 }, [$ W$ t7 Z有關 CAPTURE 最後補丁到 061 版。 ( x0 m; n2 p4 t+ G- f有關 PSPICE 最後補丁到 058 版。 / `2 G5 \/ A* b, P3 k7 Y只用上面所說的二項軟件的朋友，不用追補丁到處跑。作者: hermes 时间: 2016-8-17 13:05
何处下载？作者: jacklee_47pn 时间: 2016-8-18 07:41
; c) H$ [' O$ k3 j C1 l4 iHotfix_SPB16.60.073_wint_1of1补丁: [& R U& L& z- L+ {; c+ C
z6 O! j0 {' j. i http://pan.baidu.com/s/1i5jStCx5 D9 p; V4 c2 ?* F/ u 作者: hermes 时间: 2016-8-22 09:13
已下载，谢谢!作者: jacklee_47pn 时间: 2016-9-2 06:37
新增 076-072 版的補丁內容: _3 A( \1 J, C( s. j
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# D0 ?1 _: O& a& IDATE: 08-25-2016 HOTFIX VERSION: 076 ! j1 y3 Y. `5 M! ^ H9 T=================================================================================================================================== 9 \$ v6 b9 G5 C5 V/ T# nCCRID PRODUCT PRODUCTLEVEL2 TITLE . u0 a1 G7 `/ r3 {# g% _===================================================================================================================================9 H! Y, { r( A$ P0 I
1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp 4 _9 P7 i5 _7 }1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error , D( Q" v" l& c) I, B v1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update 7 Z& {9 z1 O: j4 r/ O. h h0 M ' t7 d7 J) O% T, CDATE: 08-12-2016 HOTFIX VERSION: 075* z6 z/ j1 C8 D4 ]2 q! Q( K6 w7 j
=================================================================================================================================== ; Y$ _, g3 T l9 E' A' p; U$ LCCRID PRODUCT PRODUCTLEVEL2 TITLE& H) v( A4 t9 z6 `8 H/ j0 L
=================================================================================================================================== 8 ]! m% t1 o% E0 u! V3 s! l1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ 7 e8 R. k* G- I1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names 1 O$ D' ?6 M1 R, |) j% Y N1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool." U/ f) H1 z9 g9 f# d! u# ?: d
1606861 CONCEPT_HDL CORE Crash on Linux during Generate View / t4 O0 g m) ^1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.% v) w. Y$ a% h* w( G
1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only 8 A. _# t% g, G) W, b& n7 S1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message. , y% M! f& d3 P& T; U. V. z* |) \) n% f( F: M e
DATE: 07-22-2016 HOTFIX VERSION: 074 8 `2 v7 Y$ B7 A9 O=================================================================================================================================== 0 R# v5 M% K+ B& Q: [0 T: l; @6 DCCRID PRODUCT PRODUCTLEVEL2 TITLE : ]6 P6 X9 ~6 O; I5 b! f===================================================================================================================================. J" G- ^ A3 ^; z: g9 @' J5 Z
1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result# Q4 L7 P' @( @4 M9 ~8 \
1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066 % i8 k* U- ^8 A0 V6 K9 l! W$ B' \1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once 5 o9 ~9 O5 d; u: U% N% E: U4 ?1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly % {6 w+ D0 U8 T9 R' g0 F1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found . r5 [, a& R, [1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes - ?% o& `, t( j* D n* q1584719 TDA CORE Caching errors coming for a board ref project while doing Block update% d( W/ Q" ?4 v$ S; ?. w! R
1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties. S y. k, v# I) n9 Z$ H
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed! ? ?$ k8 l" e2 b [1 g8 n, J
1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message"7 j5 |8 t7 P! @' ` B, ?5 Y
1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component# K* n6 @# B( o# l* j5 ~: M- b1 m4 i! K
1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior & _- u7 J, y' {+ ^8 [1590639 CONCEPT_HDL OTHER DEHDL crash when importing design1 ?% t+ x4 i; {# X5 H& S: U
1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM1 L( |0 W; g+ q* |
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified 7 f$ }, p. B: @# H4 P6 o1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view 4 B) |- W/ U3 v. _( E1 x1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save( t: i$ M3 l& \, a0 w7 ?
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor 8 g6 j2 ^5 h8 M" ^ ^, f" H+ b& u1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI h% r+ o. c) w- P: k) ]
1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas / S8 n( |; S x1598629 F2B PACKAGERXL Export Physical crashes * e6 E$ X. Z f% M J/ Z5 _( s1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes. - e% }2 m( b) ?/ H6 l" h1599950 SCM OTHER Adding the GND net to parts/pins takes a long time. ! r, ~% E* P7 w* R$ t1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group & y' |* u) t6 R% W& w7 k! y1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol 3 i! W! B, a/ e6 v2 w& ?/ L1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name.( ]; m% V2 M5 p( P; O
1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses 1 ?6 S [( U1 c k: w1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project ) A7 h6 N+ C6 R, G) O/ Z+ x1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command # ~5 `' p0 [' u% X. l3 b7 c- U1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer.% f$ P l& \6 Z' }. g j
1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error% Z: U0 v1 E! p' ]0 M6 M& I) r6 z
1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard* [( ] r8 j1 L: {4 U, q
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DATE: 06-24-2016 HOTFIX VERSION: 073 $ X: E: o9 i7 [& J% Y3 C===================================================================================================================================0 `% I# l3 U* m& V( X
CCRID PRODUCT PRODUCTLEVEL2 TITLE: Z2 a) h2 N8 f( T! R
=================================================================================================================================== 9 v% ?: f* e7 [7 c1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View 9 N& N( i( P' t* Y7 t1 h& o9 x( k1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data 8 |4 M7 A* x- f! U1590954 ORBITIO ALLEGRO_SIP_IF import of brd file fails with "Undefined argument" error+ Z& N3 H+ D( T9 m+ k
1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic, l' x! P7 x. I7 N/ U8 H5 K
7 o+ w; {0 W. ]DATE: 06-3-2016 HOTFIX VERSION: 072 0 g9 R! z- r2 R n" J$ [7 H8 C! A=================================================================================================================================== : E0 e) n; F3 _. }3 vCCRID PRODUCT PRODUCTLEVEL2 TITLE/ m; E; \: c5 i8 g
=================================================================================================================================== 8 Z" }; Q: X- S( B, z1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears , R+ G- A2 }( _: U/ S# x. _1566274 RF_PCB FE_IFF_IMPORT RF-PCB -> Import IFF crashes in DE-HDL 8 L$ X- W: j% }& ^ ~, Z# X5 [1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export . R% G" T) K9 n/ O9 f9 |1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry, U ^1 l0 B$ \6 a4 H
1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure 0 r5 J% \- A$ @. Q3 m/ A1580891 SCM REPORTS Dsreportgen crashes on different scenarios: c) ^; d/ E5 H0 I6 e2 @5 v: f
1582863 CONCEPT_HDL CORE Generate View creates non existent ports6 \) J! v( H/ K) O
1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window. ( w5 X. u, A5 j) H2 P0 Z' }2 H