标题: SPB 16.6 從061到071版的補丁內容 [打印本页] 作者: jacklee_47pn 时间: 2016-6-29 12:21 标题: SPB 16.6 從061到071版的補丁內容 DATE: 05-28-2016 HOTFIX VERSION: 071 . L% X- N; _. H===================================================================================================================================, T1 [9 a% }, g# L4 R$ I
CCRID PRODUCT PRODUCTLEVEL2 TITLE . i$ y2 I4 w' a! M9 u( l. k' ~===================================================================================================================================. U; W* i2 L# }! o0 }
1452838 CONCEPT_HDL CORE Apparent discrepancy between Bus names and other nets8 l6 [2 s9 S6 {+ l+ e8 [5 j
1469146 ADW LRM ERROR(SPCODD-5): Pin '1<1>' on the following primitive instance cannot be packaged in package ; b2 u% \' A$ G$ K1499515 ADW COMPONENT_BROWSE The Search Criteria property value is automatically being set in the ADW Component Browser4 i* C! ~6 t6 J+ l% P, f
1524947 SIG_INTEGRITY SIGNOISE SI Base, PCB SI: Custom Stimulus is not recognized correctly# U' j* w% A! y% M/ ~& \
1532162 CONCEPT_HDL CORE The Rename Signal command does not update split symbols.3 ~* S2 D1 v9 K, q
1543997 CONSTRAINT_MGR OTHER Import Logic is overwriting the constraints in attached design.$ U6 i4 C5 T; q% T
1544675 ALLEGRO_EDITOR OTHER Export libraries corrupts symbols if paths do not include the current directory (.)5 C2 \* \) h3 s- d1 R
1549097 CONSTRAINT_MGR XNET_DIFFPAIR Need to warn users creating differential pair(s) in the Physical Tab with nets that have voltage properties set+ W4 c" } J9 \8 j. L, B# H
1551934 ALLEGRO_EDITOR SKILL axlBackDrill command is not analyzing new layer set when application mode is set to 'None' ) j1 Y2 E5 A3 k5 ?5 \1 v1554919 ADW LRM LRM does not find PTF data for cell 'res' in the reference library1 y( ?+ H. S9 s* ]/ o/ a
1555009 CONCEPT_HDL INTERFACE_DESIGN Not possible to rename NG ) D7 e: z- M# h6 G; Z! u: M1557542 ALLEGRO_EDITOR OTHER DXF export creates strange result for donut-shaped polygon$ r4 n9 M9 x6 A s9 h( f9 Y
1559136 ALLEGRO_EDITOR EDIT_ETCH Cannot connect floating clines to vias with nets1 X; A% r5 P3 ~2 G
1560301 CONCEPT_HDL CORE DE-HDL hangs when Edit menu commands are called on Linux if xclip is open, c: _" g6 B$ N# ~! @# R8 S
1560804 ALLEGRO_EDITOR OTHER Film records order gets reversed when using File - Import - Parameters after File - Export - Parameters: s0 C7 i8 N8 X
1564036 CONCEPT_HDL CORE User-defined custom variables are not getting populated in the TOC 4 g* Y7 A& J* E% K3 D7 H0 r. d! S1564545 CONCEPT_HDL OTHER Signal model property deleted from an instance is not deleted from the instance pins9 X/ y# b! h+ _5 Z" A, N
1564552 CONCEPT_HDL CORE Find Net should zoom to the nets on schematic canvas ' Y) B+ E" Y7 X1566119 CONCEPT_HDL CORE Right-clicking the schematic to add a component does not show all the schematic symbol versions % g! L% ]8 d( U! E( C- C6 v1566848 ALLEGRO_EDITOR ARTWORK Board Outline artwork is incomplete % t# |- c$ N0 f) {$ x1567290 ALLEGRO_EDITOR MANUFACT Import Artwork fails to import a shape.3 ~6 O0 w" J! g
1567587 ALLEGRO_EDITOR MANUFACT Extended tool name in header of drill file is not correct , B3 I8 }/ ` i4 Y6 T# Y1569056 CONCEPT_HDL CORE Opening New Cascaded Window Causes Graphics Artifacts on Old Window 4 f$ R4 `5 k. S) A0 t4 f8 U! n1569087 ALLEGRO_EDITOR DRC_CONSTR Running DRC Update gives the message 'Figure outside of drawing extents. Cannot continue.' 7 N% i: ], o+ J! X% c! h1569147 CONCEPT_HDL CORE Signal Name AutoComplete Drop Down List Not Correctly Displayed. k' N$ M: Y$ Q( i( [
1569924 CONCEPT_HDL CHECKPLUS ERROR (body_to_physical_check) - Pin name(s) not found in package : PEX_REFCLK0_N* PEX_REFCLK1_N*.... A1 l0 r# _* U, P
1570419 CONSTRAINT_MGR CONCEPT_HDL How do I add a customized worksheet custom property weblink in Constraint Manager& M2 C3 X' e S7 J9 g7 u
1570624 APD ARTWORK Artwork file has missing voids on a layer and is causing a short2 r- q4 B7 s: q) Q
1570678 F2B DESIGNVARI Variant Editor error when adding an RSTATE property 2 w$ n+ D) i9 ?' [1 L1571113 CONSTRAINT_MGR DATABASE Reports generated from cmDiffUtility show the differences in mm units only# R' F# G# x: M( v' s2 \
1572593 ALLEGRO_EDITOR ARTWORK ARTWORK: 'Draw holes only' option does not match display; j. E% I; M* M0 J
1573205 CONCEPT_HDL CORE dsreportgen is unable to resolve the physical net names (PHYSNET) q" a i8 B$ X0 w. k" j9 z4 E& D$ t6 Q
1573970 CONCEPT_HDL ARCHIVER archcore fails to archive the <project CPM>.arch file) x3 ~; ?& V8 N) X, f
1574381 CONCEPT_HDL OTHER Packager crashes with some advanced settings+ E: ^2 M4 `( ?) D
1576100 ALLEGRO_EDITOR SYMBOL Update symbol crashes, creates '.sav' file, but shows update was successful in 'refresh.log'+ C' w0 K) \ w3 b/ w% m+ b
1580103 ALLEGRO_EDITOR DATABASE dbstat of 16.6 does not recognize 17.X files; J8 O3 d3 m! ?! r" @
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DATE: 04-22-2016 HOTFIX VERSION: 069 0 y! J+ i; Q2 P$ Z' v2 L* A2 B=================================================================================================================================== / F ^5 ~9 ~, Q& y; r8 hCCRID PRODUCT PRODUCTLEVEL2 TITLE& l+ c; w$ }/ N1 o: t
=================================================================================================================================== * Z4 C9 e* m; {; `) t$ @1272355 F2B DESIGNVARI Property changes on replaced component shows incorrect result in BOM output X8 E9 _9 t9 _* x1483136 ADW COMPONENT_BROWSE About searching the parenthesis or comma in Component Browser of ADW Mode 3 [. I& d2 j5 l7 ?& `1488909 ALLEGRO_EDITOR DRC_CONSTR Test Via causes net scheduling verification to fail6 m9 F! m8 i7 a2 U- Y6 ` A- m
1498389 SIP_LAYOUT DIE_GENERATOR Provide the ability in the 'die in' command to specify flip chip as a DIE symbol 9 X2 h) r. I( v6 Q! n& k1506672 ALLEGRO_EDITOR INTERACTIV Replicate Place - Shapes are missing $ x/ I. m- {0 w, o5 {1523532 F2B PACKAGERXL Adding subdesign names in the "Use subdesign” or “Force subdesign" sections hangs for more than a minute / \+ I7 Y- o. }1525783 CONCEPT_HDL CORE \BASE scope does not work for SYNONYMed global signals ) `6 T$ s' m; K. B ~* {1529846 ALLEGRO_EDITOR SHAPE Some shapes are not generated in the artwork9 Q9 l* k" Q& X4 r8 }
1537499 CONCEPT_HDL CORE Adding the same version (already placed) with the same split block name should not be allowed* I- R! l( V9 A6 P
1542334 CONCEPT_HDL CREFER creferhdl leaving lock files in sch_1 folder5 Q5 k7 Y- N5 X" s
1543410 ADW LRM LRM shows confusing pat status. It reports that update is needed but clicking update doesn't work - l! @( {1 a9 E! h! H2 W1546141 ALLEGRO_EDITOR SHAPE Shapes missing from Artwork' h* W$ T4 |7 u- I/ K. B# f: O
1546877 CONCEPT_HDL CORE Align Left on Wires Fails With Incorrect Error Message 5 j5 n Y. S$ C- f# }" ~1548953 CONCEPT_HDL CORE Genview generates a symbol with strange graphics - lines going to a single point# Y& W9 I2 G5 [, e9 U
1548978 ALLEGRO_EDITOR MANUFACT Shape not voiding clines 8 H, T1 y$ Z! \6 g) H$ }/ w1550941 PCB_LIBRARIAN PTF_EDITOR PDV Part Table Editor new column sorting causing problems$ v p: ^" Y; L% |4 x
1553950 ALLEGRO_EDITOR SKILL Executing axlUIControl('pixel2UserUnits) crashes Allegro0 \2 |* T3 B& f
1554333 CONCEPT_HDL CORE Changed connectivity error when aligning ports attached to netgroups2 v. B" b9 S/ v, ^: I! L
1555092 SIP_LAYOUT DEGASSING Degass offset is not working with hexagons ( p) L: X" o4 T& p! w) m1556261 ALLEGRO_EDITOR DATABASE Running DBDoctor on board file gives an error"Illegal database pointer encountered, Exiting DBDOCTOR." and crashes 5 G3 x! u- h e1557716 APD OTHER Stream out fails with request to terminate detected - Program aborted E0 x" ]2 j# Y) q7 V1559951 SIP_LAYOUT SYMB_EDIT_APPMOD Wrong bump locations after Symbol Editor -> Refresh co-design die & L- h2 Z$ R( E- v0 y+ ]# }, V: x1560197 CONCEPT_HDL CORE bomhdl adds extra charcters to subdesign_suffix when generating hierarchical BOM ; V( V; ^, m$ g+ m1 i1562537 ALLEGRO_EDITOR MENTOR Mentor BS to Allegro 16.6 results in Fatal Error $ a: U N' j2 ]7 I% o" @, l1564203 ALLEGRO_EDITOR ARTWORK ARTWORK : Can't generate negative film. D* }3 h8 o" f
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DATE: 03-23-2016 HOTFIX VERSION: 0681 s# t+ u! N3 N
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CCRID PRODUCT PRODUCTLEVEL2 TITLE 6 }3 i. G. ^8 [9 o! |2 N; |- P=================================================================================================================================== ; G) l8 l! O/ ^) `0 W1522411 FLOWS PROJMGR License selection should persist on invoking Layout from Project Manager2 o, n+ ]0 W- _ x
1544614 ALLEGRO_EDITOR SKILL Associative dimension data reaches the 'psm' file despite deleting the layer on which it was set in the 'dra' file 1 s2 p9 Z5 j0 ?2 C; w! R1545909 ALLEGRO_EDITOR UI_FORMS Show 'microvia' checkbox in 'Blind/Buried Vias' form only with the 'Allegro_PCB_Mini' license) g9 w* k: ]+ w; x1 h3 s6 \
1546842 ALLEGRO_EDITOR OTHER Unsupported characters: Not being reported by 'netrev' and causing nets to short 3 N- H3 O- r2 U+ _0 V1547224 CONCEPT_HDL CORE Lock the 'PATH' property once it is assigned by system / f. O2 G2 i# c1 Q) Z# J/ n- E9 V* r$ g1547584 SIP_LAYOUT OTHER SiP - Design Variant - delete embedded layer if not selected.7 k5 W+ l. i$ {+ S
1548116 CONCEPT_HDL CORE Some versions of Technology Independent Library do not appear when adding a symbol 0 A3 k3 Q& K- g; x1548151 ALLEGRO_EDITOR INTERFACES Exporting a step file gives a component rotation mismatch in the *.stp file/ U2 G2 n* P p A
1548421 F2B BOM Parts with same 'BOM_IGNORE' set do not behave the same way in the BOM report" b1 u5 R, ?3 ?* n
1549105 APD OTHER 'Stream out' fails with message: 'Request to terminate detected. Program aborted' ; d* { p- f8 v8 F" r$ H& R1549662 ALLEGRO_EDITOR OTHER Import parameters fails if your parampath does not have ./ g$ w- ?+ b! k* U K K) g5 F
1549836 CONCEPT_HDL CORE Tools -> Customize -> Keys -> Reset does not actually reset keyboard shortcuts % Z' ?! c- ^1 b* c6 w1550052 ALLEGRO_EDITOR PLACEMENT PCB Editor crashes when copying symbols& y1 M$ M6 G# M# X/ S
9 V0 l* t, h& Z, b, o' y0 QDATE: 03-11-2016 HOTFIX VERSION: 067 ( [% G$ S! B' o3 h ]===================================================================================================================================9 d8 c# s& C& i- m0 Q
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1482953 ALLEGRO_EDITOR DATABASE Part change disassociates parts from Group8 `6 n, h+ U- ]( l
1484075 ALLEGRO_EDITOR PADS_IN 'pads_in' imports ASSEMBLY_TOP and PLACE_BOUND_TOP outlines that are defined as shapes as lines ; L) {% j+ @0 m% x! r4 ~( Y: O- X1519155 ALLEGRO_EDITOR OTHER IPC-2581-B Negative Plane Error" A7 i/ }) z/ S, N/ R$ B
1528075 CONCEPT_HDL OTHER Auto Generate: DML model assignment fails with error 'There is PHYS_DES_PREFIX property in PTF file.' 8 Z3 x" c! r7 F7 B4 S3 n8 J1528398 ALLEGRO_EDITOR SCHEM_FTB Problem with pin number format used in NC property # h$ W1 Q* z! N# o' @( W1529178 SIG_EXPLORER OTHER Values not transferred correctly for PinPairs when created ECSET from a net2 @0 d( x6 w# t- P L5 p# B/ h; h z/ V
1529720 CONCEPT_HDL COPY_PROJECT Running ADW copy project does not update the 'master.tag' file& [1 i/ F) _" V- }( A( `* a$ _
1530707 CONCEPT_HDL CORE Request to recover a 16.6 design after DE-HDL crashes! L( z# y* ?' W5 V3 _# Z
1532124 CONSTRAINT_MGR SCM 'File - Export - Technology file' in Constraint Manager crashes SCM if .tcf file is missing 2 x6 f( F; h# L! b3 M+ I1532788 CONSTRAINT_MGR OTHER Pin pair is hidden when Highlight Filter is ON in Constraint Manager 1 H% a3 O% O7 P7 ^7 |0 B9 |1536912 CONCEPT_HDL CORE Customizing keys in DE-HDL - Disallow mapping a command to alphanumeric characters 4 {5 I& Z6 j9 q2 O1537055 CONCEPT_HDL CHECKPLUS Rules Checker - POWER_PINS value not obtained when schematic instance has the POWER_PINS and POWER_GROUP properties * h% G! }* V/ i/ K, d a1537278 SIG_EXPLORER SIMULATION SigXplorer (Allegro Sigrity SI) crashes when simulation is viewed in SystemSI Waveform Viewer3 f9 C# O/ f7 M2 p" T
1537339 CONCEPT_HDL INTERFACE_DESIGN No warning is flagged when moving a Net Group over a net & m' Z+ b, b, ^. }0 j1537521 FLOWS PROJMGR Do not allow project creation if there are spaces in directory or file names on the Linux platform/ {2 l+ q% K2 g% a8 X
1539227 CONCEPT_HDL CORE Renaming a page from the hierarchy browser crashes the schematic editor. 5 B& k& V6 |2 |4 P/ j1541532 SCM SCHGEN Generate Schematics crashes with 'Out of Memory' error * Y0 I$ ^; }# ?8 ]8 P7 ~; E1541589 ALLEGRO_EDITOR INTERFACES STEP model incorrectly shown in 3D viewer. Shows pins as angled. $ w* E. I E' h7 K' [3 f2 X0 B2 g1541680 CONCEPT_HDL DOC A dot (.) or period in design name created 2 separate design folders in worklib0 K& c2 v1 j8 R& q; E0 c5 f- E
1541687 ALLEGRO_EDITOR PADS_IN PADS closed polygons are imported as lines 6 B" T9 ?, i! B2 G( m! t1542722 ALLEGRO_EDITOR INTERFACES IDX export: RefDes and PART_NUMBER missing for mechanical symbols / Z- H P& _) {" _4 j1542817 ALLEGRO_EDITOR DATABASE Import Netlist not getting completed on specific board % x0 M0 C* X$ D9 L1544060 SCM SCHGEN Generate Schematics causes Allegro System Architect to crash * i* o: h7 M5 V2 Y2 z0 R; N0 R1544633 APD STREAM_IF The 'stream out' command causes Allegro Package Designer to crash ! i C# U' O4 [/ T1544698 ALLEGRO_EDITOR PLACEMENT 'place replicate' does not add clines and vias to fanouts if fanouts are marked' A9 |. e7 u9 f; j4 o
1544859 APD PARTITION Timing vision menu is missing in APD/SIP partitions.( y- ] a7 o4 W! z- A
1545136 ALLEGRO_EDITOR PLACEMENT All fanouts are marked as part of one symbol instead of the symbols they attached with" h; O q9 M7 e7 M
1545370 APD OTHER Pads in .mdd file getting placed on different layers as compared to the design# [: R3 [/ P9 X% x- ^9 E$ \3 ?! O
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DATE: 02-26-2016 HOTFIX VERSION: 0668 d( r" q8 W& q% B- I0 C2 c
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=================================================================================================================================== ; W; P% ?. V N1523426 ALLEGRO_EDITOR DRC_CONSTR Dynamic shape not adjusted based on keepout; DRC generated 8 [1 m! S/ o7 v) a1526729 SPIF OTHER Exporting a dsn file causes PCB Editor to crash - in the interactive and batch modes 6 m) c9 l, p, Z- Q- K1529209 CONCEPT_HDL CORE When adding a component symbol version, the More option does not show all the versions 5 l" G; [7 r& K. X) J! S- D1530888 ALLEGRO_EDITOR INTERFACES IPC2581 does not generate production files and fails with a segmentation fault message9 p3 i* d* R3 H: U
1532865 CONCEPT_HDL CHECKPLUS Provide the ability for Rules Checker to report a GND symbol from the standard, and not our local library, in .mkr 9 s* w3 O9 {% Y: h3 e r1536273 CONSTRAINT_MGR CONCEPT_HDL Model-defined differential pair is removed, and Constraint Manager Design Differences does not report an issue7 T/ R% c8 Q s5 `. j% h+ |
1538343 APD OTHER Inconsistent behavior when running Reports > Design Summary Report in Allegro Package Designer9 I! s& S, X. {2 t \* l9 a) n
1539077 ALLEGRO_EDITOR SYMBOL PCB Editor crashes when choosing Layout > Renumber Pins- H; {" Z- |# n5 d1 z @9 \7 w
1539997 ALLEGRO_EDITOR SKILL PCB Editor crashes when the axlStringRemoveSpaces() command is run 3 K5 _! p3 r2 W0 r* r' M2 ~3 C1541445 APD DIE_EDITOR There are two Recent Designs submenus in the APD Symbol Editor; one should be removed + K9 ?5 ?$ h! `) m5 n8 h& j 0 l* v0 G2 S3 k* F: y: hDATE: 02-12-2016 HOTFIX VERSION: 065 5 l: {) T4 P. ~, q# Z: N=================================================================================================================================== % g% E8 w7 ^( ~) yCCRID PRODUCT PRODUCTLEVEL2 TITLE9 E; ~) m0 ^, ?
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1511947 ADW DSN_MIGRATION Command line arguments of the 'designmigration' command are not working! C& `+ V b* h+ ^" R! A
1517388 ALLEGRO_EDITOR SHAPE DRC error reported as PCB Editor fails to read the void for a via 1 d0 f8 A7 d% {2 i3 Z5 ?( E1521661 ALLEGRO_EDITOR PLACEMENT 'place replicate create': Automatically select etch objects connected to symbols, but not to objects outside the circuit 0 b5 P& c7 t# u4 I3 C% S1522831 APD OTHER axlSpreadsheetSetColumnProp with 'AUTO_WIDTH' propName does not autofit the contents. % j9 H+ N9 z6 H1524773 SIG_INTEGRITY SIMULATION Running PCB SI Probe and SigXplorer simulations show different number and shapes of waveforms ! Z2 Q/ C5 d4 `/ \1 N, R0 ~+ H! D. \1524875 F2B PACKAGERXL Packaging using csnetlister fails, while manual packaging of individual blocks works fine$ y* Z, x' g4 m& x
1527785 SIP_LAYOUT WIREBOND SiP Layout stops responding when adding a wire to an existing finger 4 o N% ?$ Z/ M5 E8 M. E7 X2 J1528479 ADW LRM LRM crashes when opened on a lower-level block in a hierarchical design ) |; f' t7 n/ H( Z& b, j$ P/ v) i1531425 CONCEPT_HDL CORE DE-HDL crashing while trying to add a NetGroup6 F* L+ g% j( a6 [* ^1 h
1532722 ALLEGRO_EDITOR NC Backdrill NCDrill files not getting created with PA3100 license.& L- V/ a( u' a4 X' K" ^
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DATE: 01-29-2016 HOTFIX VERSION: 064 ) S5 F$ w5 ~8 f% f7 F2 P===================================================================================================================================$ F2 B( E( H$ x7 h
CCRID PRODUCT PRODUCTLEVEL2 TITLE . x' C! a) m. ~; P=================================================================================================================================== @* ^. N% `" k4 b1510387 FSP EXTERNAL_PORTS Break in extending a net as a deep connection when it is targeted to multiple FPGAs connected in a daisy chain 5 b( Z6 \- m7 _5 G1514132 ALLEGRO_EDITOR INTERFACES Element position changes after importing DXF9 k6 {( {7 X+ s1 }' W
1514285 ALLEGRO_EDITOR TECHFILE Importing .tcf file from Constraint Manager does not import user-defined properties.7 X8 F, ~2 [& |1 N
1515580 ALLEGRO_EDITOR EDIT_ETCH Sliding routed differential pair signals results in odd angles if the 'Dynamic Fillets' option is selected ' U; d& [( P3 O/ {1519040 ALLEGRO_EDITOR DATABASE Match groups are lost when a board created in SCM is saved in Allegro PCB Designer.2 P5 z) M5 r6 }3 x
1519910 CONCEPT_HDL INTERFACE_DESIGN Hotfix 62: Information on manually-remapped port groups is not saved, but reset to default" M/ ?" L3 V- m* S" m" F; W
1519943 ALLEGRO_EDITOR DATABASE When user units are changed from 4 to 2, the design seems to disappear from the canvas) {6 ^! a4 j' W$ p9 x1 q7 O$ E
1519946 CONCEPT_HDL CORE Renaming a net leads to loss of constraints associated with the net ; a0 i2 t m" v2 g; c$ B# y* B1519987 ALLEGRO_EDITOR SCHEM_FTB In Hotfix 61, constraints are lost on importing a netlist O7 l, G5 V9 Q g: N0 R) h. m
1520727 CONCEPT_HDL CORE In Project Manager, the 'Design Sync - Export Physical' command does not automatically update the schematic $ m3 X/ }- E% V" P1521174 SIP_LAYOUT DIE_STACK_EDITOR Padstack shapes not converted correctly to die-stack layer using Die-stack Editor " @/ |/ p% h" a; c- t( P1522227 SIP_LAYOUT IC_IO_EDITING SiP Layout stops responding when trying to add a co-design die (.xda file). \0 w; _( [% H2 O2 ~
1522900 ORBITIO ALLEGRO_SIP_IF Padstack shape distortion after translation to OrbitIO from SiP design" \; L/ p+ b G; |. Z, J' i
1523237 ALLEGRO_EDITOR SKILL SKILL function axlDBGetExtents() causing PCB Editor to crash . q6 s# \( w% {3 ~! p# y1524641 ALLEGRO_EDITOR DATABASE PCB Editor stops responding when updating outdated dynamic shapes ) o* d) u2 w4 ?1525432 CONSTRAINT_MGR OTHER User-defined property not being transferred from DE-HDL to PCB Editor {+ R! Y8 u* U M& a1525948 F2B PACKAGERXL Reference designators assigned by the Packager tool are not correct ; \$ z* l& v6 s1527321 ALLEGRO_EDITOR SCHEM_FTB Unable to create netlist with the 'Open Board in OrCAD PCB Editor' option in Hotfix 63# s$ c6 B2 Z; |. g9 M" k- |9 D
1528254 CONSTRAINT_MGR CONCEPT_HDL Import Logic with the 'Overwrite current constraints' option is deleting some attributes 0 r3 C0 }' f+ l% t' F/ A" f2 D) K' {, @1 f4 q' h. H
DATE: 01-15-2016 HOTFIX VERSION: 063 , M# q& i( d, J' ~4 z' @=================================================================================================================================== : B4 C6 r! Q& [0 B. cCCRID PRODUCT PRODUCTLEVEL2 TITLE 8 G e6 n* ~: T6 m) N/ B=================================================================================================================================== . E$ X$ T3 T1 m7 Y1472414 ALLEGRO_EDITOR SCHEM_FTB netrev changes pin-shape spacing rule in constraint region1 o3 {2 q0 ?4 x: ^) D6 ~
1494194 CONCEPT_HDL CORE Random display of the 'PHYS_NET_NAME' property in hierarchical designs - P7 p6 `) g; f6 Z# g& f1500190 ALLEGRO_EDITOR EDIT_ETCH Snake Router Creates Line-to-Line DRCs7 _. o5 a( g% L* ]6 Q- t
1501093 SIP_LAYOUT OTHER Package design variant shows wirebonds connected to a die which is not part of the variant 0 B$ X6 F8 s7 _) M, E0 Y1509184 ALLEGRO_EDITOR DATABASE BB vias in mirror have terminal pads suppressed by artwork, I9 `% C! ~! C/ \: O) p. C" i
1511397 SIP_LAYOUT TECHFILE Tech file exported from release 16.5 cannot be reused in SiP Layout in 16.5 or 16.6 / \. L, I* t1 r) O" L# b1511744 ALLEGRO_EDITOR OTHER Allegro PCB Editor removes property from component instance1 s1 K: L9 U. ~% Z: x2 f
1511761 SIG_INTEGRITY OTHER Allegro PCB Editor crashes on running the cns_show command. 5 r, O+ V4 E0 g1511787 ALLEGRO_EDITOR INTERFACES IPC-2581 not exporting overlapping shapes correctly. 7 ^4 M N! e1 t+ C! y' \1512071 ALLEGRO_EDITOR OTHER The color of 'SHAPE PROBLEMS' subclass is reflected in the color of 'NCLEGEND-1-4' subclass when executing PDF out3 e, Z5 m1 v3 d% ^* |& g
1513085 CONCEPT_HDL CORE NC pins combine with NC_1 and routed as one net in Allegro PCB Editor b( u8 H" ^+ t8 U. `& t, L1514469 CONCEPT_HDL CORE Unable to get rid of an underscore from the PHYS_NET_NAME property , y/ a! `8 y1 B) C8 o1515318 PCB_LIBRARIAN IMPORT_EXPORT Import Pin Table: 'CTRL + C' and 'CTRL + V' not working correctly 1 L5 F4 F* e- U7 l: v1516093 ALLEGRO_EDITOR PADS_IN Pads library translator does not translate slot orientation # n9 w% k) u N; W% @' A: V* T1517351 CONCEPT_HDL CORE Genview does not update an existing split symbol 0 u- [4 X- G/ {: e2 U( |1518032 CONCEPT_HDL SECTION How to get rid of error 'SPCOCN-2009 - Symbol has the SEC property but the required SEC_TYPE property is missing.'6 ~( r" i" }) m& F F" I
1518724 PCB_LIBRARIAN PTF_EDITOR PTF Editor is not saving changes / J! [7 ~; W! z* G) k1519518 CONCEPT_HDL OTHER Genview does not generate split symbols$ E U- L* F$ B$ {
1519623 CONCEPT_HDL CORE Differential pair added to a NetClass does not display 'NET_PHYSICAL_TYPE' on the canvas % @+ i: z5 U/ G1520207 CONCEPT_HDL CORE Genview crashes after renaming ports ! Q& `. p* y3 ?# ^, [) P 2 K1 `+ ~/ s0 G8 Z4 y3 I) ~+ z3 LDATE: 12-11-2015 HOTFIX VERSION: 062 + h' S1 O- e0 T t=================================================================================================================================== # `; P, ~9 S: _4 r$ R% U5 ACCRID PRODUCT PRODUCTLEVEL2 TITLE0 m8 g2 m- x+ ]) j
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1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output, {4 B9 E: D- @+ J
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file - E# v8 W* `& o6 B; f6 x" l1440509 ALLEGRO_EDITOR PLOTTING Ratsnest do not follow the refdes position when plotting the BOTTOM layer with the 'Mirror' option+ a2 _2 l. d$ o8 t7 [: e3 {: n) v
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC1 @0 H0 ]( g1 G' K+ V/ @ \
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view , N/ E& ]& y1 u: X" }8 Y7 ]1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked ! w$ ]5 v2 V8 U. {1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits. ! N+ H3 V) T2 I( D" w; W& q; M( C1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file 3 b/ y. a8 c" a- }% x+ H0 n& f1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding9 g4 p& {6 N, B# ^; d- E' E( d; ~
1490311 SCM OTHER Block Packaging reports duplication when it should not ) g% E. c' {3 B% {1 ^1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'8 f Q+ G7 k a G" k, H }) g
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message , m$ B% I6 f6 x$ P1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)" K8 r' Z J( r
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit + c6 R0 Z% C5 t9 \1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout3 ]9 T; G2 K. H. g/ F, y* U* q
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )5 }! i. P5 V+ m+ {! ^
1496286 ALLEGRO_EDITOR PLOTTING Export PDF is not exporting hidden, phantom, and dotted line types 8 d; y* W% s+ W W1499051 ALLEGRO_EDITOR PLOTTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape' & p, C: N2 B( z: k1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly ( G3 t) J' P w7 T6 N. |( S6 @1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this , n1 E7 V, S& K8 p. M" A. M1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch + t$ i$ \' m) c# N+ `% h1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default ; ?4 d' A1 ?- h/ A1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts8 X6 t$ A* I! u
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks3 F7 u$ m w7 ^
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out6 q3 D# p, T: u1 L' n0 e
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF " |4 a, q& r! L' X1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form, N$ h# E% H2 R0 w
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL) {; m0 K6 [# N1 }0 O
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings ) a9 S, i- O L/ l1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location 7 q$ d# R" U, `4 B* ?$ {1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized# }" P; G$ M. N0 t4 X3 d9 L
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary& s9 G9 Y. @/ @$ d' k5 S7 {
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items! z; z7 V0 d* v9 l1 }
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin; D/ q! \0 ~/ ?# t
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving1 i( P7 Y3 f6 c2 [
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None % W5 v e* J" E, Z: Y. a6 I3 B$ g/ x* c" P4 }
DATE: 11-20-2015 HOTFIX VERSION: 061 9 o5 U- P% c, J9 Q' R/ P" V k=================================================================================================================================== & E6 L( ^$ @" sCCRID PRODUCT PRODUCTLEVEL2 TITLE* ?4 l5 n$ B5 ]; `0 _/ Z
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1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value5 @7 C& a# q$ Z5 X4 Z8 Z
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init ! x+ M f! W0 T( v( v* U- M1413248 CONCEPT_HDL CORE Import from another TDO project makes the block read-only # V7 {2 g9 Z+ z% U! e1417429 ALLEGRO_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle / g. y$ `0 W* q. f' Q) ^ l1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins6 u6 t3 z" [( \+ Z* W
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set: y( x u9 S! a" `' s
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin4 s0 k p" r& l6 J* W$ G X
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools {3 K5 T& ?+ j% D! P
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename 4 Y: g: G( S$ T1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets4 F7 r1 F: y* l# [1 ` b
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL 9 w& e5 }% }. @4 x1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy) X1 l) h2 c, o9 Q8 b
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable $ y0 e% y. K2 | \8 B! J1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets# M1 _7 n# v0 p5 D: ^
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice # Q% G$ H% U) r7 a% ~6 \6 k; c( Q1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues 6 s+ M& \5 s$ j' X/ Z1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only5 [' b# C3 q" q9 ]+ D8 \
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project @+ z( }" y) o, ^0 j# d9 _# A [ x1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork. ! d( P* f7 T7 x2 E5 N1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility 0 v' Y/ d/ P) \1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems " |% Q Y& _. l9 T8 J% c- D1 t1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported# Q! U7 O) Z6 B2 v5 i" y" t6 ?' B2 k
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior 4 J: ~( }! w4 E5 ]' M+ N+ B# R1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board ' s" X, }1 d2 a" w7 n" g1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager - a% }# @! |7 K4 f5 v1490299 SCM OTHER ASA does not update revision properly $ n [" c' ~9 j' c7 Q, a" ]1490744 ALLEGRO_EDITOR SKILL axlChangeLine2Cline changes line to cline and places it on the TOP layer6 Q# Q$ s% N( j. e/ \9 a$ l
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints8 P' F# f; m) s( g7 o6 T. v" B
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working/ I+ m) G$ Y7 N1 y) @1 ^6 }; v' C) K
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong * B" Q* Z+ @+ p. X! C) d2 }$ e G1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash0 Y, v$ W2 V- G. n$ W0 K
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL : Y* C/ G% X) q& J; g& [' M2 y& v1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581 : t, l0 g! w& b& I @* E1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size ; b3 k- i) j7 x3 I3 Y) x1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root : ~3 j' N/ y4 ^0 f1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file # e' ]& y& G' I& r, E) Q% ^1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60作者: jacklee_47pn 时间: 2016-6-29 12:27
截至目前 071 版本， 2 |7 E0 l2 N% C有關 CAPTURE 最後補丁到 061 版。% y# I& `2 |8 \2 Z) _+ T
有關 PSPICE 最後補丁到 058 版。3 {0 ]6 a: N: h" |
只用上面所說的二項軟件的朋友，不用追補丁到處跑。作者: hermes 时间: 2016-8-17 13:05
何处下载？作者: jacklee_47pn 时间: 2016-8-18 07:41
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Hotfix_SPB16.60.073_wint_1of1补丁, k2 ~9 d- a9 J5 H9 y
5 e7 l( L1 d# R5 P/ Q* S t: ?) g8 \ http://pan.baidu.com/s/1i5jStCx( L7 u! V5 D2 @: h- Q8 H6 k0 h% K2 y3 s+ {6 t 作者: hermes 时间: 2016-8-22 09:13
已下载，谢谢!作者: jacklee_47pn 时间: 2016-9-2 06:37
新增 076-072 版的補丁內容 A1 Z+ t' Z% a& E* \
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DATE: 08-25-2016 HOTFIX VERSION: 076, q1 t/ ?# T+ u- z4 a
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1614667 SIG_INTEGRITY SIMULATION Different results from Probe in SI Base and SigXp % P' m) o) v( {! O* B8 g$ ?1615601 GRE IFP_INTERACTIVE Delete Bundle then try to delete plan lines results in fatal error% c7 @* p" n, Z( Q! k/ p% i' n) M
1616540 SIP_LAYOUT DRC_CONSTRAINTS Same net DRC Line-to-Line reappearing after dyn shape update 4 N9 I; f' X7 A8 a5 w. [ " ?; r: f) O9 p% v2 ?8 i* NDATE: 08-12-2016 HOTFIX VERSION: 075 @, C+ I; v- ]6 e' @+ F8 c===================================================================================================================================' [8 G; P3 |+ o9 K" e3 s! j
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 c* r- X& G7 L# F1 \' d) e: |5 D2 _
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1461626 CONCEPT_HDL CREFER Cross-references shown to the same pin on different block instances though the signal names differ 1 t/ X0 }( B/ B1 \ i1597000 CONCEPT_HDL INTERFACE_DESIGN Renaming NG does not work if >1 segments have NG names$ O% s& E+ |6 \/ Q3 |) }+ l4 z
1602801 SIG_INTEGRITY OTHER Dielectric Warning message when opening SiP tool.8 S/ g3 c' c+ }' h1 a1 I& S- Z* h" P
1606861 CONCEPT_HDL CORE Crash on Linux during Generate View 3 M' w# v3 j$ @+ b1608524 SIP_LAYOUT MANUFACTURING The Display Pin Text tool fails in the 16.6.073 version with a parseString error.0 c8 A4 S' J; d. z3 p. u
1609922 CONCEPT_HDL INFRA Launching Model Assignment crashes DE-HDL when the temp/edbDump.txt is read-only ' r; _6 V8 M6 K% r; T1612108 ALLEGRO_EDITOR OTHER Netlist Import is crashing with the .SAV message. 5 R ?* A: @, d* g$ G1 V4 P * {& n y' h( `0 d9 U QDATE: 07-22-2016 HOTFIX VERSION: 074 , p) _, }0 j/ F1 z$ C===================================================================================================================================$ V/ S0 |( `& b% |' I3 t
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1423889 ALLEGRO_EDITOR EDIT_ETCH AiDT gets poor routing result - [% ?9 u9 ], M& a& m7 t1547356 ALLEGRO_EDITOR EDIT_ETCH Results variations from ISR S034 to S066 , f* w; S0 t4 u: A5 l1568912 RF_PCB BE_IFF_IMPORT Route keepouts can only be imported once$ X; k; S3 W1 B+ _3 x9 p. ~
1574676 ORBITIO ALLEGRO_SIP_IF sip->oio eco doesn't work properly3 O3 j7 Y, K9 }6 `- Y: V5 N7 _
1580744 F2B PACKAGERXL ERROR(SPCODD-114): Duplicate physical part name NETSHORT found0 H8 i, `. \) [$ O5 ^
1582628 ADW TDA When one user takes an update of physical object while the other user is still checking in the object, TDO crashes - X; |, K0 v. }& j4 o& T& Z: V1584719 TDA CORE Caching errors coming for a board ref project while doing Block update 3 K6 c ^ z% |, R8 {8 \% z1587157 CONCEPT_HDL CONSTRAINT_MGR pstprop.net reports conflicts on nets with VOLTAGE properties% c2 @/ y9 S2 x
1587498 CONCEPT_HDL INTERFACE_DESIGN Possibility to tap bus bits removed - b5 {2 M! A8 c8 l$ `" I1588786 ALLEGRO_EDITOR OTHER strip_design reports "Design corrupted message" 1 y- V# }! p0 {2 ~- k) t4 F0 I1589252 CONCEPT_HDL CORE Search options go to page origo not chosen component 5 y! z2 }* f4 B+ c; n8 X) c1590538 CONCEPT_HDL DOC Open Archive shows unclear behavior , e2 c5 W+ I8 c% h: `# z$ P# e5 E. ]1590639 CONCEPT_HDL OTHER DEHDL crash when importing design 7 q1 G# s3 z( y1590651 CONCEPT_HDL INTERFACE_DESIGN DEHDL duplicate NetGroups created in Interface Browser and CM6 o h7 c( A. I) m3 ]
1594076 TDA CORE TDO is crashing on concurrent checkin when one of the user got blocks which are not modified$ b, M0 l% l0 d+ J: B( U
1594358 CONSTRAINT_MGR CONCEPT_HDL Enable hierarchical BOM fails for sub block with working variant view & B) T. @! _% } }3 x$ }' t, ~1596780 ALLEGRO_EDITOR SKILL PCB Editor crashes after doing SRM update and save# j# U! U1 ?2 u* a* a$ _
1597153 F2B DESIGNVARI ERROR SPCODD-53 in Variant Editor ; ~# U) }$ m: C3 Z2 O; H, l1597385 F2B DESIGNVARI Some 16.5 variant DNI parts are now appearing in 16.6 as X-OUT and some don't have X-OUT or DNI7 t; a7 I0 s: C: s& M
1597413 SIG_EXPLORER SIMULATION SigXp crashes when simulating with via that was added to canvas / X0 G6 A' V, {0 e7 P6 A1 Q7 W$ f+ I1598629 F2B PACKAGERXL Export Physical crashes& i% x& B6 K+ j4 U; G8 s* E
1599452 ALLEGRO_EDITOR ARTWORK Import Artwork, Mirror option does import pins or shapes.3 R n/ @4 A; f$ g
1599950 SCM OTHER Adding the GND net to parts/pins takes a long time.$ @. t4 V) W7 l9 o
1600226 RF_PCB AUTO_PLACE Fail to auto-place RF group 4 J4 v9 f5 B7 \$ E% e1601281 ALLEGRO_EDITOR OTHER STEP model link gets corrupted with SKILL axlLoadSymbol 1 g: Y: L* {, J) i) _$ C- l+ h/ E1601282 ALLEGRO_EDITOR OTHER Export Libraries will not export device files when there is a space in the folder name. 8 Q% l0 N6 r) R$ U8 [1602186 PCB_LIBRARIAN VERIFICATION con2con should work with PCB_Library_Manager license in 166 as 166 tools should work with 172 upgraded licenses " c i G& `) f1 W1602514 PCB_LIBRARIAN METADATA References to some primitives is missing in block metadata causing TDA errors for missing parts after join project0 m, V2 e- j; j4 C% f$ f
1602823 SIP_LAYOUT WIREBOND SiP Crashed during Add Wire command; |: O) j+ @5 p+ I9 f/ v
1602955 ALLEGRO_EDITOR SHAPE Shape no DRC when there is a Route Keepout in base layer. . b+ I6 }& m, [3 Z/ j5 n6 \1604223 CONCEPT_HDL CORE ERROR: SPCOCD-553: Connectivity Server Error " G/ M5 R4 O5 M3 [+ @4 R9 [1605310 TDA CORE TDA is crashing sometimes in the Join Project wizard * N5 O. ~+ E" g( `/ z* [3 H G9 E; X , A3 W" ]0 q! ?% }& d' K/ D5 ~7 WDATE: 06-24-2016 HOTFIX VERSION: 0734 Z8 |% B4 A; m; T* j1 u2 B
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1570032 ALLEGRO_EDITOR GRAPHICS Issue with 3D View* {& @2 Z- N4 e, U( L
1582103 ALLEGRO_EDITOR PADS_IN PADS Library Import creates additional filled shape not present in source data # m: Y! N7 L5 x& O; Z. E8 l1590954 ORBITIO ALLEGRO_SIP_IF import of brd file fails with "Undefined argument" error F1 n3 n8 W: n7 m! m
1591223 CONCEPT_HDL CORE Variant information does not display on lower level schematic5 p+ s' b; w( Y
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DATE: 06-3-2016 HOTFIX VERSION: 072 6 S' W, V/ R9 s2 _, a; g1 A=================================================================================================================================== : t0 w$ a* m; ~/ @0 D8 g* R& ECCRID PRODUCT PRODUCTLEVEL2 TITLE# p# r1 O# G, c& S3 n
=================================================================================================================================== * G/ c) ^: S' C5 _& k' I7 `1546151 CONCEPT_HDL CORE Add port, Genview, move pin on block - the pin name disappears' W6 b! l- e1 \( |; r# O
1566274 RF_PCB FE_IFF_IMPORT RF-PCB -> Import IFF crashes in DE-HDL/ I) @3 P( \/ b. m
1573039 ALLEGRO_EDITOR INTERFACES IDX returns control to the general interface prematurely during an incremental IDX export( j* O7 g2 y' V2 S: \$ q3 M9 O2 S
1573127 CONCEPT_HDL COPY_PROJECT copyproject creates incorrect view_pcb entry + m# X3 e- r* e" D& @# H1577381 CONCEPT_HDL CORE ERROR(SPCOCN-2128): The NetGroup structure does not match the PortGroup structure / `4 l5 i/ v* ], l+ U1580891 SCM REPORTS Dsreportgen crashes on different scenarios& J% Y6 c& d3 l# F9 q3 \6 O" f
1582863 CONCEPT_HDL CORE Generate View creates non existent ports - O8 O: {4 \' N; p! q: E1584317 CONCEPT_HDL CORE When packager fails, no option to open pxl.log file from design sync window.: {& S5 U7 r' o% B9 o& S0 ]8 }0 O