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标题:
SystemVerilog for Verification
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作者:
xuzwg
时间:
2016-5-4 16:14
标题:
SystemVerilog for Verification
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SystemVerilog for Verification:
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A Guide to Learning the Testbench Language Features
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1. VERIFICATION GUIDELINES 1
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1.1 Introduction 1
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1.2 The Verification Process 2
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1.3 The Verification Plan 4
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1.4 The Verification Methodology Manual 4
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1.5 Basic Testbench Functionality 5
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1.6 Directed Testing 5
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1.7 Methodology Basics 7
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1.8 Constrained-Random Stimulus 8
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1.9 What Should You Randomize? 10
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1.10 Functional Coverage 13
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1.11 Testbench Components 15
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1.12 Layered Testbench 16
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1.13 Building a Layered Testbench 22
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1.14 Simulation Environment Phases 23
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1.15 Maximum Code Reuse 24
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1.16 Testbench Performance 24
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1.17 Conclusion 25
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2. DATA TYPES 27
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2.1 Introduction 27
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2.2 Built-in Data Types 27
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2.3 Fixed-Size Arrays 29
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2.4 Dynamic Arrays 34
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2.5 Queues 36
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2.6 Associative Arrays 37
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2.7 Linked Lists 39
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2.8 Array Methods 40
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2.9 Choosing a Storage Type 42
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2.10 Creating New Types with typedef 45
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2.11 Creating User-Defined Structures 46
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2.12 Enumerated Types 47
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2.13 Constants 51
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2.14 Strings 51
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2.15 Expression Width 52
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2.16 Net Types 53
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2.17 Conclusion 53
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3. PROCEDURAL STATEMENTS AND ROUTINES 55
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3.1 Introduction 55
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3.2 Procedural Statements 55
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3.3 Tasks, Functions, and Void Functions 56
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3.4 Task and Function Overview 57
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3.5 Routine Arguments 57
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3.6 Returning from a Routine 62
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3.7 Local Data Storage 62
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3.8 Time Values 64
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3.9 Conclusion 65
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4. BASIC OOP 67
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4.1 Introduction 67
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4.2 Think of Nouns, not Verbs 67
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4.3 Your First Class 68
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4.4 Where to Define a Class 69
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4.5 OOP Terminology 69
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4.6 Creating New Objects 70
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4.7 Object Deallocation 74
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4.8 Using Objects 76
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4.9 Static Variables vs. Global Variables 76
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4.10 Class Routines 78
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4.11 Defining Routines Outside of the Class 79
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4.12 Scoping Rules 81
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4.13 Using One Class Inside Another 85
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4.14 Understanding Dynamic Objects 87
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4.15 Copying Objects 91
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4.16 Public vs. Private 95
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Contents ix
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4.17 Straying Off Course 96
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4.18 Building a Testbench 96
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4.19 Conclusion 97
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5. CONNECTING THE TESTBENCH AND DESIGN 99
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5.1 Introduction 99
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5.2 Separating the Testbench and Design 99
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5.3 The Interface Construct 102
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5.4 Stimulus Timing 108
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5.5 Interface Driving and Sampling 114
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5.6 Connecting It All Together 121
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5.7 Top-Level Scope 121
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5.8 Program – Module Interactions 123
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5.9 SystemVerilog Assertions 124
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5.10 The Four-Port ATM Router 126
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5.11 Conclusion 134
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6. RANDOMIZATION 135
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6.1 Introduction 135
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6.2 What to Randomize 136
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6.3 Randomization in SystemVerilog 138
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6.4 Constraint Details 141
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6.5 Solution Probabilities 149
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6.6 Controlling Multiple Constraint Blocks 154
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6.7 Valid Constraints 154
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6.8 In-line Constraints 155
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6.9 The pre_randomize and post_randomize Functions 156
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6.10 Constraints Tips and Techniques 158
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6.11 Common Randomization Problems 164
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6.12 Iterative and Array Constraints 165
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6.13 Atomic Stimulus Generation vs. Scenario Generation 172
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6.14 Random Control 175
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6.15 Random Generators 177
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6.16 Random Device Configuration 180
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6.17 Conclusion 182
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7. THREADS AND INTERPROCESS COMMUNICATION 183
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7.1 Introduction 183
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7.2 Working with Threads 184
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7.3 Interprocess Communication 194
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7.4 Events 195
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7.5 Semaphores 199
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7.6 Mailboxes 201
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7.7 Building a Testbench with Threads and IPC 210
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7.8 Conclusion 214
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8. ADVANCED OOP AND GUIDELINES 215
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8.1 Introduction 215
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8.2 Introduction to Inheritance 216
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8.3 Factory Patterns 221
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8.4 Type Casting and Virtual Methods 225
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8.5 Composition, Inheritance, and Alternatives 228
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8.6 Copying an Object 233
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8.7 Callbacks 236
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8.8 Conclusion 240
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9. FUNCTIONAL COVERAGE 241
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9.1 Introduction 241
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9.2 Coverage Types 243
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9.3 Functional Coverage Strategies 246
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9.4 Simple Functional Coverage Example 248
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9.5 Anatomy of a Cover Group 251
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9.6 Triggering a Cover Group 253
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9.7 Data Sampling 256
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9.8 Cross Coverage 265
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9.9 Coverage Options 272
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9.10 Parameterized Cover Groups 274
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9.11 Analyzing Coverage Data 275
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9.12 Measuring Coverage Statistics During Simulation 276
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9.13 Conclusion 277
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10. ADVANCED INTERFACES 279
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10.1 Introduction 279
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10.2 Virtual Interfaces with the ATM Router 279
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10.3 Connecting to Multiple Design Configurations 284
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10.4 Procedural Code in an Interface 290
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10.5 Conclusion 294
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References 295
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Index 297
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作者:
xuzwg
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2016-5-4 16:14
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