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标题:
数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。
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作者:
zhangsong123
时间:
2016-4-13 18:01
标题:
数码管倒计时和蜂鸣器同步的问题，麻烦大神们进来看看，指教一二。
通过Verilog HDL用数码管设计了一个40s的倒计时，想在10s之后加上一个蜂鸣器，无奈本人初学FPGA，苦试多次无果，故来此请教各位大神，能帮我在40s倒计时上面加上一个蜂鸣器吗，跪求了，谢谢！！！！module led_rxd(clk,rst_n,SOS_En_Sig,led,led_seg);
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input clk,rst_n;
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output [7:0]led;
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output [5:0]led_seg;
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output SOS_En_Sig;
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parameter seg_num0=8'hc0,
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seg_num1=8'hf9,
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seg_num2=8'ha4,
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seg_num3=8'hb0,
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seg_num4=8'h99,
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seg_num5=8'h92,
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seg_num6=8'h82,
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seg_num7=8'hf8,
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seg_num8=8'h80,
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seg_num9=8'h90;
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parameter seg_en0=6'b111110,
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seg_en1=6'b111101,
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seg_en2=6'b111011,
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seg_en3=6'b110111,
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seg_en4=6'b101111,
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seg_en5=6'b011111;
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reg [26:0]count;
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reg [3:0] count1;
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reg [3:0] count2;
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reg [7:0] led_reg;
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reg [5:0] led_seg_reg;
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always@(posedge clk or negedge rst_n)
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if(!rst_n) count<=27'd0;
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else if(count==27'd49_999_999) count<=27'd0;
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else count<=count+1'b1;
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wire clk_div=(count==27'd49_999_999);
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always@(posedge clk_div or negedge rst_n)
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if(!rst_n)
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begin
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count1<=4'd0;
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count2<=4'd4;
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end
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else if((count1==4'd0)&&(count2==4'd0))
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begin
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count1<=4'd0;
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count2<=4'd4;
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end
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else if(count1==4'd0)
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begin
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count2<= count2-1'b1;
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count1<=4'd9;
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end
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else count1<=count1-1'b1;
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reg [26:0]count_1ms;//
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always@(posedge clk or negedge rst_n)
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if(!rst_n) count_1ms<=27'd0;
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else if(count_1ms==27'd49_999) count_1ms<=27'd0;
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else count_1ms<=count_1ms+1'b1;
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wire clk_dis=(count_1ms==27'd49_999);//
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//
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reg [1:0]state;
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always@(posedge clk_dis or negedge rst_n)
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if(!rst_n)
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begin
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led_reg<=8'hff;
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led_seg_reg<=6'b111111;
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state<=2'b00;
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end
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else if(state==2'b00)
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begin
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state<=2'b01;
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led_seg_reg<=6'b111101;
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case(count2)
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4'd0: led_reg<=seg_num0;
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4'd1: led_reg<=seg_num1;
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4'd2:led_reg<=seg_num2;
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4'd3: led_reg<=seg_num3;
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4'd4: led_reg<=seg_num4;
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4'd5: led_reg<=seg_num5;
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4'd6: led_reg<=seg_num6;
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4'd7: led_reg<=seg_num7;
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4'd8: led_reg<=seg_num8;
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4'd9: led_reg<=seg_num9;
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default: led_reg<=seg_num0;
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endcase
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end
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else if(state==2'b01)
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begin
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state<=2'b00;
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led_seg_reg<=6'b111110;
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case(count1)
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4'd0:led_reg<=seg_num0;
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4'd1:led_reg<=seg_num1;
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4'd2:led_reg<=seg_num2;
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4'd3:led_reg<=seg_num3;
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4'd4:led_reg<=seg_num4;
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4'd5:led_reg<=seg_num5;
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4'd6:led_reg<=seg_num6;
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4'd7:led_reg<=seg_num7;
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4'd8:led_reg<=seg_num8;
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4'd9:led_reg<=seg_num9;
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default:led_reg<=seg_num0;
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endcase
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end
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reg isEn;
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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begin
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isEn<=1'b0;
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end
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else
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begin
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isEn<=1'b1;
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end
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assign led=led_reg;
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assign led_seg=led_seg_reg;
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assign SOS_En_Sig=isEn;
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endmodule
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