标题: Hotfix_SPB16.60.054更新 [打印本页] 作者: zgyzgy 时间: 2015-8-3 11:54 标题: Hotfix_SPB16.60.054更新 DATE: 07-31-2015 HOTFIX VERSION: 054 9 {) z3 x7 C3 ~=================================================================================================================================== . S# G! l1 F' r" K- j, [CCRID PRODUCT PRODUCTLEVEL2 TITLE j: X1 w. e8 @- m5 L=================================================================================================================================== : x2 t2 A5 p+ k# W Y b6 |694479 CONCEPT_HDL OTHER Need version control of symbols in DE-HDL " M8 \- L" G( ]2 f2 }& J& e' {695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions/ W3 x, ~! ^$ }& }2 {+ L' E: h
1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List 8 w, n( P' Q% |# |1357843 ALLEGRO_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate" C5 @$ S+ _' h' L# w# m3 `
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees 2 i& I5 p2 e2 W1 Q; [2 ?$ d1 t1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias 2 @, P% v/ G% I' Q$ M1412635 APD DATABASE APD crashes on saving design 3 q2 h- Z' U+ T$ t: C' N* r1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices( {2 H9 W1 P1 F5 p& P3 M& Y
1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation , G" @+ r7 g4 h" x+ ?+ e9 n1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes. ) l6 f, M" f8 H1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50 0 _1 S7 V/ e3 ^! o* T. v" g! a' k1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"/ F1 I0 Q2 c' ]- f" ~- S
1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module2 a- l7 j R7 c# `
1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated/ p$ S8 @( _$ o5 E$ e: @+ a
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output8 u6 J" I6 C( p
1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification8 J8 h& ~/ c/ K" L- s2 n
1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.: X% s- G% k& d. }, _4 Z" ^
1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets0 u! t& q( W6 v8 I' e5 K$ h* u; r
1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor 9 c7 S$ D9 ?1 C: Q. `( F' R) R1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow 1 Q8 x1 y# W# u z3 ]1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed 3 g4 w% V z$ I" L1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board ' ^2 }! f/ r- B) G+ G! e8 B1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks ; Z I% {% T" b2 ~# C1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports( \4 G' m/ K* d& Q
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC 0 l1 e5 { F! G2 |3 ]5 O5 e1 y1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary* X: H N0 i, a K
1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash. - R: M" d T) j% t' A b1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1* u3 n7 S4 H+ E& [0 @