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标题: Cadence 16.6 Hotfix_SPB16.60.038 [打印本页]
作者: streetflower    时间: 2014-11-14 17:14
标题: Cadence 16.6 Hotfix_SPB16.60.038
本帖最后由 streetflower 于 2014-11-14 17:14 编辑 5 n3 u0 f* {0 U$ v! m

! a, G8 D2 v* t8 h& F7 @; C+ p% @Cadence 16.6 Hotfix_SPB16.60.038
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http://pan.baidu.com/s/1gdCb4cV
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DATE: 10-31-2014   HOTFIX VERSION: 038
2 b4 M6 c5 k1 a: u- g# s5 v===================================================================================================================================# k% @1 c5 j. k+ y- ?. \* G  z+ D6 ~
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE0 h/ ]. i# Q/ j. s4 k7 ]% M2 P
===================================================================================================================================
8 X& {0 {; {1 I' Z# r( a! v1103937 PCB_LIBRARIAN  VERIFICATION     con2con should not have any need for a graphical terminal9 X2 C0 l5 A' u& H# N4 q
1107843 FSP            OTHER            Support for lrf and lmf in archived project
( r' J+ S/ ?  y" M0 f4 f9 Z# O1123765 CAPTURE        GENERAL          .OLBlck file not deleted if library is closed in Capture
; k( b) k3 ?: H1169740 FSP            OTHER            Ability to import "Assigned Pin" column to connect Generic connector and FPGA.% P; W, s. K( B4 v) V
1172641 FSP            FPGA_SUPPORT     Support for 5SGSMD5K2F40I2N device
- {2 B/ T: l( b9 `2 ^) [& F4 x1177760 CAPTURE        OTHER            IC pins cannot be cross probed from Capture to PCB Editor
5 }7 F* }/ |) x9 S. x1195672 ALLEGRO_EDITOR PLACEMENT        Place replicate update should update component value text" k! y3 l. q& W5 A; O+ Z
1206563 FSP            GUI              Spreadsheet import support for xc3s400afg400
& i1 N0 e+ v  o  g1 n  j: f: ?! g1208169 FSP            FPGA_SUPPORT     New FPGA model request  _$ z; W. x) l8 w  e& b( j1 Q) w
1224428 ALLEGRO_EDITOR PLACEMENT        Get message "W-(SPMHGE-579): Unable to complete path to circuit for all selections" when updating place replicate circuit
  Z6 X- h1 A+ i& m& f. l) K. ^' v& F1230064 ALLEGRO_EDITOR INTERACTIV       Place replicate is trying to match dimensions: z7 R6 }+ F9 T, Z+ O. l3 j( R' j
1253986 CONCEPT_HDL    CORE             Not able to define Source when adding property to a selected group. u6 z5 X$ ]6 j' O- }8 x
1266615 ADW            SHOPINGCART      Error(SPDWUB-48) while placing the part from the shopping cart6 \) M+ a% N% {( }
1269658 ALLEGRO_EDITOR EDIT_ETCH        Ratsnest disappears near pin when routing
8 O, J3 ]# A6 y3 J2 O; `6 ^1270158 CONCEPT_HDL    CONSTRAINT_MGR   Orphan nets are visible in CM but not in DE-HDL, k# i% `. ~1 R, g! \) V+ Q+ O
1275042 CONCEPT_HDL    COMP_BROWSER     Unit specifier 'HC' not found in UNITS environment while placing the part on schematic
9 B% `& h# U" S. ?0 G: Y: ~$ Q1276269 ALLEGRO_EDITOR TESTPREP         On creating a fixture, a test point is generated but refs are not visible.
6 f$ A1 n# J/ a) k' q( V1278037 SIP_LAYOUT     ASSY_RULE_CHECK  DRC soldermask to finger check required for cases when the finger has no wire attached
4 y4 S) ^& Z9 M* @  d3 |. p! g4 y1278475 ALLEGRO_EDITOR DATABASE         Import Logic changes VIA net names to GND
* {% Q5 C+ O1 S$ u& ?1279162 SIP_LAYOUT     DIE_ABSTRACT_IF  Add codesign die should default shrink/scribe settings from die abstract if abstract contains this information.% z1 ^' r. h9 ^# ?5 j3 m: e; q: h
1282358 SIP_LAYOUT     OTHER            Why are IC/PKG symbols always mirrored when placed on a sip design?
5 d: Z- @$ E( @: s  t* S1283439 CAPTURE        ANNOTATE         Inter Sheet Refs placed on top of Off Page Connector name) j* v) P2 ^$ Y8 w6 [# T
1284809 ALLEGRO_EDITOR INTERACTIV       Using the Fix icon in the toolbar will not apply the Fixed property to Groups
# n1 ~5 |$ W& w1286277 CAPTURE        SCHEMATICS       Capture crashes on adding Bezier curves# l: C/ U9 v- }" n* u. z
1286354 CONCEPT_HDL    CORE             The GENERATE_SCH_METADATA 'ON' directive causes significant DE-HDL performance degradation
; G: a. @$ O* s1286617 CONCEPT_HDL    CORE             Generate View failure
# ^- M0 Z2 K, i5 y, g1287020 CAPTURE        OTHER            Option to disable Autobackup
+ z" a+ F5 z; g3 x7 J/ r1 l1287100 FSP            DESIGN_SETTINGS  FSP global edit of Capture library paths, y( ^, R2 @8 H: g$ t$ @  e
1287877 CONCEPT_HDL    CHECKPLUS        Graphic check in CheckPlus hangs with sch_something view
2 S8 L/ v- E' D1289056 ADW            OTHER            MKnet program to also read the alim.auto from ADW_CONF_ROOT4 ]6 t. ~" X+ o
1289107 CONCEPT_HDL    CORE             Find with Schematic Selection fails after clicking Find All three times5 L" D0 l. O3 l6 v# {: M% [
1289175 CAPTURE        OPTIONS          Autobackup changes timestamp of each and every part in the library.1 `. m7 \2 W: K  f/ ^+ x
1289447 TDA            CORE             Undo Check-out removes new design data from local area$ B" y' N4 M! f' W
1289677 ALLEGRO_EDITOR SHAPE            Complex shape filling fails without DRC
. l5 S7 _) l/ _) t7 f1289755 ALLEGRO_EDITOR EDIT_ETCH        Timing Vision Display error2 r7 ?0 u; S6 I
1289913 ALLEGRO_EDITOR EDIT_ETCH        Enhance the fanout function to speed up the layout design in Allegro PCB Editor.8 B+ L5 B( c+ N% v- p$ I
1290136 ALLEGRO_EDITOR EDIT_ETCH        Unable to connect IC pin to ground. E3 E. K" X2 }1 M* H
1290426 SIP_LAYOUT     LOGIC            Deleting a distributed codesign component from parts list does not remove the component information from the design database% D4 |1 I; {; H0 n' d
1291888 ALLEGRO_EDITOR INTERACTIV       Property DYN_DELETED_ISLAND is not added on all the voids created by Delete Island command
: B/ q1 [* H5 k: I0 [1292206 ALLEGRO_EDITOR OTHER            Allow netname to be visible for pin/cline when viewed in Allegro PDF Publisher# U+ Z) @8 z3 a6 ~( \
1292234 APD            SHAPE            Shape does not Void around Clines and Vias due to some corruption0 j( \% D2 U3 E) v
1292877 ALLEGRO_EDITOR DATABASE         DB doctor fixed void boundary but deleted all boundary without detail information.
  c+ P- w( y7 t" U6 q( I; f- Z1293041 ADW            COMPONENT_BROWSE Component Browser does not show results if you filter on the PPL and an additional column 6 r/ i& A; F0 W' j, U2 F  M
1293188 ALLEGRO_EDITOR EDIT_ETCH        fanout function(via in pad) deleted the cline & thermal
5 ^* \! t7 P( j( A  E1293626 CONCEPT_HDL    CORE             Delete Page command could not delete the dependency file (page2.csd).
* ?; P6 Y% Q/ _/ [: C$ M" j1293710 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes during copy fanout
) a# B4 T( v* x% \/ w( w. K; j1294355 PSPICE         SIMULATOR        Function "ddt( )" behavior in DC sweep analysis
; W* }9 H6 L2 Z4 f' ~1295232 CAPTURE        SCHEMATIC_EDITOR Remove from group changes not reflected consistently in Part Manager
' _/ i5 Y3 o% Y. t' ~7 C1295434 ALLEGRO_EDITOR INTERACTIV       Enable Pin Name to be imported into a .BRD and display this in the show info output as done in APD and SIP
4 e  }6 t3 b# B* z- y0 u1296583 ALLEGRO_EDITOR FSP_PINSWAP      Crash for FSP Auto Pinswap with PCB Editor
  ~( @) d7 _4 W% A9 i, C+ Y& a7 V3 a1297095 ADW            LRM              LRM replaces incorrect part in schematic.
0 S" l. n- p+ c1297685 F2B            DESIGNVARI       'Could not open xmodules.dat file' Error during 'Save'.
6 ~9 v% c" ~; ~) O  i% P' }; V- u; k( v1297835 ALLEGRO_EDITOR INTERACTIV       DFA-Driven Interactive Placement not working correctly for components on bottom side3 L* b" P9 q! R+ w$ X0 m
1297870 SIP_LAYOUT     ASSY_RULE_CHECK  Wire to Wire Optical short ADRC reports wrong DRC violation, I0 r* K/ L, T% A+ P
1297994 ALLEGRO_EDITOR INTERACTIV       When moving a via and splitting the stack, the via moves off the design work surface.6 Q, A0 b2 V  A$ O+ K
1298129 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Phase tuning should have option to Allow DRCs
. y$ b! x. ?& W* y1299050 ADW            PCBCACHE         Need a way to turn off all project ptf file backup files under flatlib
* a. c; P1 M7 b5 ?% o, r1299873 CONCEPT_HDL    CORE             DE-HDL window size and position is not saved on exit( |; a3 v( j8 {0 v) r$ V. Z
1300101 ALLEGRO_EDITOR GRAPHICS         Inconsistency in symbol editor and PCB Editor while showing 3D view
* Z  l* q8 U! r2 Q1300557 ALLEGRO_EDITOR EDIT_ETCH        Move Component with "Slide Etch" or "Stretch Etch" removes DYN_CLEARANCE_OVERSIZE from clines
4 z8 k# \7 l2 y  m1300806 ALLEGRO_EDITOR GRAPHICS         Stroke command in 16.6 works differently as compared with earlier versions
# Q; W' t. r2 \: U1302103 CONCEPT_HDL    CONSTRAINT_MGR   DE-HDL CM startup time on large hierarchical is extremely large(6-8 min)
( g" I" j! v4 y9 }+ c1302939 ALLEGRO_EDITOR PARTITION        Place replicate modules lost with design partition4 @# J6 O1 a$ i4 l
1303078 CAPTURE        STABILITY        Capture crashes on View -- Status Bar with no design open
* n" S* S- F( {' W0 R3 y+ ?1303106 ALLEGRO_EDITOR SKILL            Creating shape with SKILL script does not work on SPB16.5 and SPB16.6.
- b- P, C4 t6 x( l1303442 ALLEGRO_EDITOR EDIT_ETCH        auto-interactive convert corner function crashes PCB Editor
- V0 H" q* A) }5 I1303921 ADW            COMPONENT_BROWSE Datasheets with spaces are not viewable in component browser
4 J8 x( t+ s& E( ]8 |5 F1304042 APD            LOGIC            ERROR(SPMHUT-43):netin command is not working for .mcm.9 g# I# U2 j( p. X
1304725 ALLEGRO_EDITOR INTERACTIV       Value 0 in Allegro Text Setup not valid anymore
2 A. ?& A- ?7 @9 P. X1304734 ALLEGRO_EDITOR PADS_IN          PADS_IN does not follow the settings in the options file0 R. s# x1 x( J2 h
1304882 CONCEPT_HDL    CORE             Hierarchy Viewer jumps up to the top on File Save
3 t+ ~, }8 J6 L; m; B. ]$ M  D1305147 ALLEGRO_EDITOR MANUFACT         Auto silk result is unstable.
9 Y  m- z+ W4 o3 ^1306323 ALLEGRO_EDITOR INTERACTIV       Mirror command does not seem to work correctly.( X) F2 u4 K, h
1306468 ALLEGRO_EDITOR DATABASE         Dbdoctor Crash
8 p3 y0 m; X2 i1 v! H' n% O# B1307277 SIP_LAYOUT     IMPORT_DATA      Wants BGA Text-In Wizard to maintain Pad layer set in the text file instead of defaulting to Bottom layer.
, a+ |7 e, Q" ?, X# F1307367 FSP            FPGA_SUPPORT     FSP user needs 5SGSMD5K3F40I3N/5SGSED6K3F40I3N in FPGA models.
9 s! Z8 \  f' B% M1307478 ALLEGRO_EDITOR MENTOR           unable to do PADS Library translation.7 H) f* l: h% u4 A7 T7 H
1307626 ALLEGRO_EDITOR INTERACTIV       Pick window is different for command and from GUI
3 o' C6 U4 A3 v8 R" h1307785 ASI_PI         GUI              Decap Configuration GUI does not update until you deselect then select GND
$ y) m/ \) z8 A/ I1308163 SIP_LAYOUT     ORBITIO_IF       Importing OrbitIO with multiple packages and XDA file into SIP layout results in incomplete data4 L  s: h8 Z) _+ P  l* f
1308289 SIP_LAYOUT     ORBITIO_IF       Import OrbitIO into existing SIP database fails. Testing an ECO type of design flow
: p, q: U8 n& x1309315 CAPTURE        ANNOTATE         Incremental annotation is not giving correct refdes in case of attached complex hierarchical design
4 A; I. k9 a0 |' L  e1310614 CONCEPT_HDL    CORE             Part Manager creates bogus directory on linux system3 V" b4 l: u/ t5 v. ~% w; y
1311184 CAPTURE        NETLIST_ALLEGRO  Incorrect warning for DEVICE property value in netlisting.7 p6 [* H1 l2 V5 u3 T- S2 s5 f
1311719 ALLEGRO_EDITOR INTERACTIV       Allegro Component will not place on the canvas" C6 w3 U1 |! _. I$ @$ N( y
1311757 CONCEPT_HDL    CORE             Cannot change a property from instance level to non-instance level' A0 p* V- D2 Z/ F9 i& s
1311848 CONSTRAINT_MGR OTHER            PFE is adding a capacitor after creating PI CSet
. J: p; o8 J. r0 S) d! v3 Z1312553 CONCEPT_HDL    CORE             Customer could not add their net property after deleting it.; a( x" b' s5 u( X4 t9 b
1313068 APD            DIE_ESCAPE       die escape gen: Cannot route from pad of Via Structure.3 y. X: u) v* k/ x
1313239 CONSTRAINT_MGR CONCEPT_HDL      Diff pair constraints disappear if xnet is created for them in Editor/ A6 K' ~/ A( K7 G
1313850 ALLEGRO_EDITOR PLACEMENT        Place Replicate ignores fillet at pins
: ]/ r& _8 O. |. q7 ]1314207 ALLEGRO_EDITOR OTHER            PCB Editor crash when rotating IPF data; `' s/ \& [5 i& m2 Q% U% ^2 Y
1314467 ALLEGRO_EDITOR INTERACTIV       With high_speed option selected, PCB Editor crashes on move operation
: ]% k" ?3 N- [% S1314921 ALLEGRO_EDITOR PLACEMENT        RATS are wrongly displayed.
: T. i5 o2 B- l# G( P3 h$ U, q5 m1314973 CAPTURE        OTHER            Cannot cross-probe all pins from Capture2 W4 V- T8 l$ C) J8 q* ~
1316295 ALLEGRO_EDITOR OTHER            .brd extension is removed after running DB Doctor from PCB Editor Utilities.1 Y  L* F3 N8 \* N5 w
1316757 ALLEGRO_EDITOR DRC_CONSTR       Spacing constraint error on negative layer" U, {* _4 u5 p& ?
1316959 ALLEGRO_EDITOR PARTITION        Exported soft boundary partition2 symbol still cannot move out of partition boundary: _9 ~2 C9 E! p5 O9 P4 Y/ h# s) T
1317157 SIP_LAYOUT     DIE_STACK_EDITOR After moving the Dies to different layers a Wirebond has changed the connection from the pin to a shape.
: ?. j) z1 |) {. b' J" j1317480 ALLEGRO_EDITOR SYMBOL           Allegro DB check "SPMHA1-247 Illegal mirror error"
& j+ \( \! T: y( d# m" \/ J1317614 ADW            COMPONENT_BROWSE Datasheet_Url is not opening the file browser correctly2 t  E7 @0 d% Y0 M# m* A
1317876 APD            COLOR            APD crashes when executing Color Dialog for Nets/ {- z5 T5 p8 y
1320028 FSP            DE-HDL_SCHEMATIC Error (10002: Cannot find a ppt part that matches the instance properties
# k) V1 Q# L% `9 h  w- c+ ]1320438 ALLEGRO_EDITOR GRAPHICS         Could not save DFA spreadsheet3 e0 C8 U# V! u& ^7 G7 D/ x
1322600 CONCEPT_HDL    CONSTRAINT_MGR   Cannot extract xnet topology due to missing model even if the model is present) N; g% f3 o: U/ O) `! P, O& S
1323327 CONCEPT_HDL    CONSTRAINT_MGR   Deleting Ref Electrical CSet from Diff Pair removes it from a Matched Group in DE-HDL
& o, E3 K4 l# W  i0 a! m) T1325230 CONCEPT_HDL    CORE             DE-HDL crashes once the design is loaded.! u( D' E9 R* I5 G4 B8 d5 C* }
1325644 F2B            PACKAGERXL       CDS_LOCATION/$PN not deleted from property file(dcf) backannotation warnings! z0 h. F+ S6 a. j7 y% r9 S- ]
1325905 CONCEPT_HDL    CORE             Schematic page import causes re-sectioning of the pins.' P% R3 C* b/ X" @5 e% ^* l0 h' [7 i
1326163 SIP_LAYOUT     OTHER            SiP Layout - Void Adjacent Layer - Include option to ignore same net object when voiding1 h+ b4 ?# n. L2 L8 [  z
1326696 CONCEPT_HDL    CORE             Cannot get concepthdl -product to invoke with the high speed already available
4 N$ q( l, K' d% g5 e6 U1327367 CONCEPT_HDL    CORE             Crash when saving after adding block pin  w$ J2 z8 ~% T+ E: A0 J" {& k
1327569 ADW            LRM              LRM does not update the headers if the part number is also changed
' T8 k) z. G9 ]- d: z1329271 ALLEGRO_EDITOR DRC_CONSTR       Multithreading DRC check is flagging a DRC on the TOP Layer for Route Keepout that has the property ?SHAPES_ALLOWED? ON.
" U# ~# @0 F/ ?5 g6 M1329587 CONCEPT_HDL    CORE             Using the GROUP command does NOT place all objects in the group back on grid
8 _$ {! ?  \1 F1330913 CONCEPT_HDL    COMP_BROWSER     Empty value in PTF file9 I- l. U; x$ s
1332728 SIG_INTEGRITY  OTHER            Signal model assignment form returning SYNTAX ERROR on Linux 5.0 5.7 and 5.9 with hotfix s036 and s037.
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作者: nathon    时间: 2014-11-14 21:25
打了这个补丁，生成的钻孔文件cam350不认识，怎么回事？
作者: menghunabc    时间: 2014-11-16 12:33
怎么感觉打了补丁 和没有打之前一样的呢？
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作者: menghunabc    时间: 2014-11-16 12:37
更新了038的补丁 怎么还是004啊？

QQ图片20141116123825.jpg (40.34 KB, 下载次数: 2)

QQ图片20141116123825.jpg
作者: menghunabc    时间: 2014-11-16 13:42
:'(:'(:'( 原理图开不了了
作者: ann_wz    时间: 2014-11-16 19:13
难道这个补丁有问题
作者: kevin890505    时间: 2014-11-16 19:16
打了已经一阵子了，表示这一版本把许多测试内容，变更为正式功能，进步很大，新的功能强势的很。cadence给人的感觉是，本软件的目标就是，软件极度智能，PCB难度大幅度降低，设计周期大幅度缩小。NB的软件不需要解释啊。
作者: 墨客的秋天    时间: 2014-11-16 20:04
补丁有问题啊
作者: wangxs_song    时间: 2014-11-16 20:29
墨客的秋天 发表于 2014-11-16 20:04
% o$ ]5 G: Z9 j8 ]+ L5 ?补丁有问题啊

7 g; i6 w/ K# o 大多情况都是自己的问题，只是还没有足够去发现和反省而已。  166的补丁每次都有新改进，智能程度也越来越高了......只是.......
作者: waiwai788    时间: 2014-11-16 20:50
已经安装了，目前没发现问题，不知道是我用的太简单了？呵呵支持
作者: nathon    时间: 2014-11-16 21:49
钻孔文件打不开我觉的是cam350的问题。有人用genesis吗？不知能否打开？https://www.eda365.com/thread-102901-1-1.html
作者: sinfy    时间: 2014-12-4 14:36
不错，支持，我也下一个
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作者: sinfy    时间: 2014-12-4 14:37
正需要呢，谢谢了
作者: streetflower    时间: 2014-12-4 17:04
sinfy 发表于 2014-12-4 14:37$ L6 ^  S$ W. N' A7 L1 D
正需要呢，谢谢了
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去下最新的039
: t6 s" m0 i; \+ THotfix_SPB16.60.039
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