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标题: 问题，求回答，关于SerDes仿真问题 [打印本页]

作者: shirley_zong 时间: 2014-10-17 15:50
标题: 问题，求回答，关于SerDes仿真问题
使用AMI模型仿真SerDes，SerDes发送端需要添加电容，我在仿真的时候发现，电容的影响很大。情况如下：
使用ADS仿真器，加入理想的电容，电容值为0.022nf。
现象：1、如果去掉电容，眼高大概50多mV
         2、通道里面只加入电容，眼高会在200多mV
         3、加入电容以及package和两个过孔，还没有添加传输线，眼睛就已经闭合了
问题:1、以上属于什么问题
      2、如何解决这一问题

还请各位大师帮忙解决一下困惑

另外一问，SerDes总线Tx加电容的作用，明白是隔直通交。想知道更具体的

谢谢

作者: Coziness_yang 时间: 2014-10-17 16:16
请问你在这里面怎么加入电容模型的？电容的模型带宽又是多少？
电容模型不仅是隔直通交，他在高频时还有寄身电感以及电阻等，这些都会影响仿真结果。

作者: shirley_zong 时间: 2014-10-17 16:38
我就在ADS里面添加了0.022nf的理想电容，其他的没有考虑

作者: shirley_zong 时间: 2014-10-17 16:40
电容模型不仅是隔直通交，他在高频时还有寄身电感以及电阻等：然后加入电容的作用呢？如果不加电容，从仿真的眼图看更好一些，不明白为什么要加电容？

作者: cousins 时间: 2014-10-17 16:49
加串联电容的目的之一是滤除低频噪声。SerDes生成的逻辑门里都不可避免的会引入这类噪声，这个隔直电容不仅仅是起到隔直，同时还要考虑容值造成的占空比问题，level降低，所以不宜过大，也不宜过小，通常会根据你的带宽确定一个范围。你在仿真的时候是无法了解到IC电路系统内的噪声的，你所关注的并且所能做的是通道内的影响。

作者: shirley_zong 时间: 2014-10-17 17:37
我电容的带宽根据什么选择呢，数据率。如何计算？还有我按照原理图选择的是0.022nf的电容。我的信号的数据率为14Gpbs？

作者: cousins 时间: 2014-10-18 09:25
一个经验：电容高频模型等效的相移小于二十分之一波长，若只考虑理想电容，自然是容值越大越好，然而实际电容高频模型里有电感，电容，电阻等参数，由于工艺水平限制，往往0201大小的电容以及安装时焊盘和过孔的寄生参数已经很难不断减小，因此电容并非越大越好，要保证这些参数最后产生的相移都在这个经验范围内才不会影响到抖动规格。
So...

作者: Head4psi 时间: 2014-10-18 17:12
本帖最后由 Head4psi 于 2014-10-18 22:29 编辑

cousins 发表于 2014-10-18 09:258 I$ W; f- A/ j# C3 T
一个经验：电容高频模型等效的相移小于二十分之一波长，若只考虑理想电容，自然是容值越大越好，然而实际电 ...

DC Blocking Capacitor Value
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I shall begin with a quote from my newsletter vol 4, #15, "When to use AC coupling":

[size=11.8181819915771px]To estimate the degree of DC wander possible when passing a particular code through a certain high pass filter HPF(f), first set up a complimentary filter LPF(f), defined thus:
[size=11.8181819915771px]LPF(f) = 1 - HPF(f)
[size=11.8181819915771px]Then pass the data code through the filter LPF(f) and look for the worst-case output. The magnitude of the output of LPF(f) equals the magnitude of the worst-case DC-wander error you will experience when passing your signal through HPF(f).

If that article is not familiar to you, take a moment now to look it over, as the remainder of this text builds on that theme: www.sigcon.com/Pubs/news/4_15.htm

Filter Theory (Review)

The remainder of this article requires that you know the relaxation time constant associated with a high-pass R-C filter.

If your transmission setup is terminated at both ends with impedance Z0, as is customary with very high-speed links, then the total resistance in series with your DC blocking capacitor equals twice the line impedance, or 2Z0. A DC-blocking capacitor C placed in series with your serial link creates a simple high-pass filter [HPF] with a time constant:

That statement assumes your line is terminated at both ends.

If, on the other hand, your source happens to be a low-impedance driver and the line terminated only at its far end with impedance Z0 then the time constant becomes a different value:

In either case the related complementary filter [1-HPF(f)] has the same time constant as HPF(f).

I shall assume in the following analysis that your transmission line is terminated at both ends. If that is not the case, you must modify all the equations below.

Approach

I propose that we develop an expression for the maximal size of the output from the complementary low-pass filter LPF(f). That expression relates the maximum amount DC wander to the time constant,τ and thus to the value of capacitance.

If you know how much wander your system can tolerate, as determined from analysis of your eye margin budget, you can then calculate the capacitance required to achieve that goal.

To read along with the following analysis you need to know how a one-pole LPF reacts to one individual bit.

Figure 1 —Response of low-pass filter to a single bit with unit amplitude.

A single bit of duration T when presented to the input to the LPF causes the LPF output to rise in a linear fashion during the bit interval, falling slowly with time constant τ, thereafter back to zero. This approximation assumes that τ vastly exceeds T, a condition consistent with the idea of a DC-blocking application.

If you transmit N similar bits in a row, it is a good bet that the LPF filter output will pump up to a value of NT/τ.

How many bits in a row might you ever see? That is a very important question to ask about your data code; answers vary widely depending on who designed your code and whether they considered DC balance.

I am going to define a term now, called running-disparity, or RD, that will help you understand how data codes are built. Every sequence of code bits x[n] implies a corresponding sequence RD[n], where:

RD[n] equals the sum of all bits up to and including bit x[n]

It is helpful in constructing these arguments if you think of a binary data sequence as having values +1 and -1 (or, more generally, +A and -A). For a DC-balanced sequence, the RD never strays far from zero.

In fact, one excellent way to specify the degree of DC balance in a data code is to call out the maximum excursion of RD.

Those of you well versed in calculus may be thinking that RD looks like an integrating operation. Precisely.

Here is a basic theorem about RD.

IF your data code guarantees |RD|<n
THEN the DC wander signal z(t) is bounded by:

Where:

n is the bound on RD, in numbers of baud intervals,
A is the binary signal amplitude (+/-A),
T is the coded bit interval, and
<Greek-tau> is the HPF filter time constant.5 U, c* R5 r3 B) i+ B

This RD theorem assumes that the filter response is a single-pole filter with a monotonic step response (no zeros).

With the RD theorem and the relation τ=2Z0C in hand, a specification M for the maximum permissible amplitude of DC wander then determines the required (minimum) value of capacitance C:

Where:

n is the bound on RD, in numbers of baud intervals,
A is the binary signal amplitude, in volts, assuming the signal swings from -A to +A,
T is the coded bit interval,
M is the maximum permissible amplitude of DC wander, in volts, and
Z0 is the transmission line impedance (assumes both-ends termination).
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Any value of capacitance larger than this amount will work.

The following sections review four popular data codes showing the values of n appropriate for each.

作者: cousins 时间: 2014-10-18 20:21

Head4psi 发表于 2014-10-18 17:12
$ p% J" C# J8 C8 Z: `* nDC Blocking Capacitor ValueDetail please refer to Dr. Howard Johnson's webside:http://www.sigcon ...

是的，这是howard关于容值选择的完整选择方式。支持使用。原理上也是为了控制相移

作者: shirley_zong 时间: 2014-10-20 11:46

cousins 发表于 2014-10-18 09:25( W$ y4 U0 ~/ f4 [5 F
一个经验：电容高频模型等效的相移小于二十分之一波长，若只考虑理想电容，自然是容值越大越好，然而实际电 ...

那如果我不加电容会怎么样呢？

作者: cousins 时间: 2014-10-20 12:43
没有隔直，可能会出现DC shift
而且低频噪声引入会造成单调性，占空比，相位抖动的问题。

作者: jamesytl 时间: 2014-11-20 08:45
顶一个！

作者: jamesytl 时间: 2014-11-21 08:23

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